gem5  v20.1.0.0
decoder.cc
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1 /*
2  * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  *
33  * Authors: John Slice
34  * Anthony Gutierrez
35  */
36 
37 #include "arch/gcn3/gpu_decoder.hh"
38 
39 #include <vector>
40 
43 
44 namespace Gcn3ISA
45 {
47  {
48  } // Decoder
49 
51  {
52  } // ~Decoder
53 
567  };
568 
1338  };
1339 
1597  };
1598 
1728  };
1729 
1859  };
1860 
1878  };
1879 
2009  };
2010 
2076  };
2077 
2335  };
2336 
2466  };
2467 
2597  };
2598 
2604  };
2605 
2863  };
2864 
3122  };
3123 
3124  GPUStaticInst*
3126  {
3127  InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
3129  return (this->*method)(mach_inst);
3130  } // decode
3131 
3132  GPUStaticInst*
3134  {
3135  InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
3136  IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
3137  return (this->*method)(iFmt);
3138  } // subDecode_OP_VOPC
3139 
3140  GPUStaticInst*
3142  {
3143  InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
3144  IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
3145  return (this->*method)(iFmt);
3146  } // subDecode_OP_VOP1
3147 
3148  GPUStaticInst*
3150  {
3151  InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
3152  IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
3153  return (this->*method)(iFmt);
3154  } // subDecode_OP_SOP1
3155 
3156  GPUStaticInst*
3158  {
3159  InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
3160  IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
3161  return (this->*method)(iFmt);
3162  } // subDecode_OP_SOPC
3163 
3164  GPUStaticInst*
3166  {
3167  InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
3168  IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
3169  return (this->*method)(iFmt);
3170  } // subDecode_OP_SOPP
3171 
3172  GPUStaticInst*
3174  {
3175  InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
3176  IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
3177  return (this->*method)(iFmt);
3178  } // subDecode_OP_SMEM
3179 
3180  GPUStaticInst*
3182  {
3183  InFmt_VOP3 *enc = &iFmt->iFmt_VOP3;
3185  return (this->*method)(iFmt);
3186  } // subDecode_OPU_VOP3
3187 
3188  GPUStaticInst*
3190  {
3191  InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
3193  return (this->*method)(iFmt);
3194  } // subDecode_OP_VINTRP
3195 
3196  GPUStaticInst*
3198  {
3199  InFmt_DS *enc = &iFmt->iFmt_DS;
3200  IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
3201  return (this->*method)(iFmt);
3202  } // subDecode_OP_DS
3203 
3204  GPUStaticInst*
3206  {
3207  InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
3208  IsaDecodeMethod method = tableSubDecode_OP_FLAT[enc->OP];
3209  return (this->*method)(iFmt);
3210  } // subDecode_OP_FLAT
3211 
3212  GPUStaticInst*
3214  {
3215  InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
3217  return (this->*method)(iFmt);
3218  } // subDecode_OP_MUBUF
3219 
3220  GPUStaticInst*
3222  {
3223  InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
3225  return (this->*method)(iFmt);
3226  } // subDecode_OP_MTBUF
3227 
3228  GPUStaticInst*
3230  {
3231  InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
3232  IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
3233  return (this->*method)(iFmt);
3234  } // subDecode_OP_MIMG
3235 
3236  GPUStaticInst*
3238  {
3239  return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
3240  } // decode_OP_VOP2__V_CNDMASK_B32
3241 
3242  GPUStaticInst*
3244  {
3245  return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
3246  } // decode_OP_VOP2__V_ADD_F32
3247 
3248  GPUStaticInst*
3250  {
3251  return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
3252  } // decode_OP_VOP2__V_SUB_F32
3253 
3254  GPUStaticInst*
3256  {
3257  return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
3258  } // decode_OP_VOP2__V_SUBREV_F32
3259 
3260  GPUStaticInst*
3262  {
3263  return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
3264  } // decode_OP_VOP2__V_MUL_LEGACY_F32
3265 
3266  GPUStaticInst*
3268  {
3269  return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
3270  } // decode_OP_VOP2__V_MUL_F32
3271 
3272  GPUStaticInst*
3274  {
3275  return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
3276  } // decode_OP_VOP2__V_MUL_I32_I24
3277 
3278  GPUStaticInst*
3280  {
3281  return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
3282  } // decode_OP_VOP2__V_MUL_HI_I32_I24
3283 
3284  GPUStaticInst*
3286  {
3287  return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
3288  } // decode_OP_VOP2__V_MUL_U32_U24
3289 
3290  GPUStaticInst*
3292  {
3293  return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
3294  } // decode_OP_VOP2__V_MUL_HI_U32_U24
3295 
3296  GPUStaticInst*
3298  {
3299  return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
3300  } // decode_OP_VOP2__V_MIN_F32
3301 
3302  GPUStaticInst*
3304  {
3305  return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
3306  } // decode_OP_VOP2__V_MAX_F32
3307 
3308  GPUStaticInst*
3310  {
3311  return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
3312  } // decode_OP_VOP2__V_MIN_I32
3313 
3314  GPUStaticInst*
3316  {
3317  return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
3318  } // decode_OP_VOP2__V_MAX_I32
3319 
3320  GPUStaticInst*
3322  {
3323  return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
3324  } // decode_OP_VOP2__V_MIN_U32
3325 
3326  GPUStaticInst*
3328  {
3329  return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
3330  } // decode_OP_VOP2__V_MAX_U32
3331 
3332  GPUStaticInst*
3334  {
3335  return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
3336  } // decode_OP_VOP2__V_LSHRREV_B32
3337 
3338  GPUStaticInst*
3340  {
3341  return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
3342  } // decode_OP_VOP2__V_ASHRREV_I32
3343 
3344  GPUStaticInst*
3346  {
3347  return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
3348  } // decode_OP_VOP2__V_LSHLREV_B32
3349 
3350  GPUStaticInst*
3352  {
3353  return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
3354  } // decode_OP_VOP2__V_AND_B32
3355 
3356  GPUStaticInst*
3358  {
3359  return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
3360  } // decode_OP_VOP2__V_OR_B32
3361 
3362  GPUStaticInst*
3364  {
3365  return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
3366  } // decode_OP_VOP2__V_XOR_B32
3367 
3368  GPUStaticInst*
3370  {
3371  return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
3372  } // decode_OP_VOP2__V_MAC_F32
3373 
3374  GPUStaticInst*
3376  {
3377  return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
3378  } // decode_OP_VOP2__V_MADMK_F32
3379 
3380  GPUStaticInst*
3382  {
3383  return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
3384  } // decode_OP_VOP2__V_MADAK_F32
3385 
3386  GPUStaticInst*
3388  {
3389  return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
3390  } // decode_OP_VOP2__V_ADD_U32
3391 
3392  GPUStaticInst*
3394  {
3395  return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
3396  } // decode_OP_VOP2__V_SUB_U32
3397 
3398  GPUStaticInst*
3400  {
3401  return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
3402  } // decode_OP_VOP2__V_SUBREV_U32
3403 
3404  GPUStaticInst*
3406  {
3407  return new Inst_VOP2__V_ADDC_U32(&iFmt->iFmt_VOP2);
3408  } // decode_OP_VOP2__V_ADDC_U32
3409 
3410  GPUStaticInst*
3412  {
3413  return new Inst_VOP2__V_SUBB_U32(&iFmt->iFmt_VOP2);
3414  } // decode_OP_VOP2__V_SUBB_U32
3415 
3416  GPUStaticInst*
3418  {
3419  return new Inst_VOP2__V_SUBBREV_U32(&iFmt->iFmt_VOP2);
3420  } // decode_OP_VOP2__V_SUBBREV_U32
3421 
3422  GPUStaticInst*
3424  {
3425  return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
3426  } // decode_OP_VOP2__V_ADD_F16
3427 
3428  GPUStaticInst*
3430  {
3431  return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
3432  } // decode_OP_VOP2__V_SUB_F16
3433 
3434  GPUStaticInst*
3436  {
3437  return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
3438  } // decode_OP_VOP2__V_SUBREV_F16
3439 
3440  GPUStaticInst*
3442  {
3443  return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
3444  } // decode_OP_VOP2__V_MUL_F16
3445 
3446  GPUStaticInst*
3448  {
3449  return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
3450  } // decode_OP_VOP2__V_MAC_F16
3451 
3452  GPUStaticInst*
3454  {
3455  return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
3456  } // decode_OP_VOP2__V_MADMK_F16
3457 
3458  GPUStaticInst*
3460  {
3461  return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
3462  } // decode_OP_VOP2__V_MADAK_F16
3463 
3464  GPUStaticInst*
3466  {
3467  return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
3468  } // decode_OP_VOP2__V_ADD_U16
3469 
3470  GPUStaticInst*
3472  {
3473  return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
3474  } // decode_OP_VOP2__V_SUB_U16
3475 
3476  GPUStaticInst*
3478  {
3479  return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
3480  } // decode_OP_VOP2__V_SUBREV_U16
3481 
3482  GPUStaticInst*
3484  {
3485  return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
3486  } // decode_OP_VOP2__V_MUL_LO_U16
3487 
3488  GPUStaticInst*
3490  {
3491  return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
3492  } // decode_OP_VOP2__V_LSHLREV_B16
3493 
3494  GPUStaticInst*
3496  {
3497  return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
3498  } // decode_OP_VOP2__V_LSHRREV_B16
3499 
3500  GPUStaticInst*
3502  {
3503  return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
3504  } // decode_OP_VOP2__V_ASHRREV_I16
3505 
3506  GPUStaticInst*
3508  {
3509  return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
3510  } // decode_OP_VOP2__V_MAX_F16
3511 
3512  GPUStaticInst*
3514  {
3515  return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
3516  } // decode_OP_VOP2__V_MIN_F16
3517 
3518  GPUStaticInst*
3520  {
3521  return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
3522  } // decode_OP_VOP2__V_MAX_U16
3523 
3524  GPUStaticInst*
3526  {
3527  return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
3528  } // decode_OP_VOP2__V_MAX_I16
3529 
3530  GPUStaticInst*
3532  {
3533  return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
3534  } // decode_OP_VOP2__V_MIN_U16
3535 
3536  GPUStaticInst*
3538  {
3539  return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
3540  } // decode_OP_VOP2__V_MIN_I16
3541 
3542  GPUStaticInst*
3544  {
3545  return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
3546  } // decode_OP_VOP2__V_LDEXP_F16
3547 
3548  GPUStaticInst*
3550  {
3551  return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
3552  } // decode_OP_SOP2__S_ADD_U32
3553 
3554  GPUStaticInst*
3556  {
3557  return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
3558  } // decode_OP_SOP2__S_SUB_U32
3559 
3560  GPUStaticInst*
3562  {
3563  return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
3564  } // decode_OP_SOP2__S_ADD_I32
3565 
3566  GPUStaticInst*
3568  {
3569  return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
3570  } // decode_OP_SOP2__S_SUB_I32
3571 
3572  GPUStaticInst*
3574  {
3575  return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
3576  } // decode_OP_SOP2__S_ADDC_U32
3577 
3578  GPUStaticInst*
3580  {
3581  return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
3582  } // decode_OP_SOP2__S_SUBB_U32
3583 
3584  GPUStaticInst*
3586  {
3587  return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
3588  } // decode_OP_SOP2__S_MIN_I32
3589 
3590  GPUStaticInst*
3592  {
3593  return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
3594  } // decode_OP_SOP2__S_MIN_U32
3595 
3596  GPUStaticInst*
3598  {
3599  return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
3600  } // decode_OP_SOP2__S_MAX_I32
3601 
3602  GPUStaticInst*
3604  {
3605  return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
3606  } // decode_OP_SOP2__S_MAX_U32
3607 
3608  GPUStaticInst*
3610  {
3611  return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
3612  } // decode_OP_SOP2__S_CSELECT_B32
3613 
3614  GPUStaticInst*
3616  {
3617  return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
3618  } // decode_OP_SOP2__S_CSELECT_B64
3619 
3620  GPUStaticInst*
3622  {
3623  return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
3624  } // decode_OP_SOP2__S_AND_B32
3625 
3626  GPUStaticInst*
3628  {
3629  return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
3630  } // decode_OP_SOP2__S_AND_B64
3631 
3632  GPUStaticInst*
3634  {
3635  return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
3636  } // decode_OP_SOP2__S_OR_B32
3637 
3638  GPUStaticInst*
3640  {
3641  return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
3642  } // decode_OP_SOP2__S_OR_B64
3643 
3644  GPUStaticInst*
3646  {
3647  return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
3648  } // decode_OP_SOP2__S_XOR_B32
3649 
3650  GPUStaticInst*
3652  {
3653  return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
3654  } // decode_OP_SOP2__S_XOR_B64
3655 
3656  GPUStaticInst*
3658  {
3659  return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
3660  } // decode_OP_SOP2__S_ANDN2_B32
3661 
3662  GPUStaticInst*
3664  {
3665  return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
3666  } // decode_OP_SOP2__S_ANDN2_B64
3667 
3668  GPUStaticInst*
3670  {
3671  return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
3672  } // decode_OP_SOP2__S_ORN2_B32
3673 
3674  GPUStaticInst*
3676  {
3677  return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
3678  } // decode_OP_SOP2__S_ORN2_B64
3679 
3680  GPUStaticInst*
3682  {
3683  return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
3684  } // decode_OP_SOP2__S_NAND_B32
3685 
3686  GPUStaticInst*
3688  {
3689  return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
3690  } // decode_OP_SOP2__S_NAND_B64
3691 
3692  GPUStaticInst*
3694  {
3695  return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
3696  } // decode_OP_SOP2__S_NOR_B32
3697 
3698  GPUStaticInst*
3700  {
3701  return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
3702  } // decode_OP_SOP2__S_NOR_B64
3703 
3704  GPUStaticInst*
3706  {
3707  return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
3708  } // decode_OP_SOP2__S_XNOR_B32
3709 
3710  GPUStaticInst*
3712  {
3713  return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
3714  } // decode_OP_SOP2__S_XNOR_B64
3715 
3716  GPUStaticInst*
3718  {
3719  return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
3720  } // decode_OP_SOP2__S_LSHL_B32
3721 
3722  GPUStaticInst*
3724  {
3725  return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
3726  } // decode_OP_SOP2__S_LSHL_B64
3727 
3728  GPUStaticInst*
3730  {
3731  return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
3732  } // decode_OP_SOP2__S_LSHR_B32
3733 
3734  GPUStaticInst*
3736  {
3737  return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
3738  } // decode_OP_SOP2__S_LSHR_B64
3739 
3740  GPUStaticInst*
3742  {
3743  return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
3744  } // decode_OP_SOP2__S_ASHR_I32
3745 
3746  GPUStaticInst*
3748  {
3749  return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
3750  } // decode_OP_SOP2__S_ASHR_I64
3751 
3752  GPUStaticInst*
3754  {
3755  return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
3756  } // decode_OP_SOP2__S_BFM_B32
3757 
3758  GPUStaticInst*
3760  {
3761  return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
3762  } // decode_OP_SOP2__S_BFM_B64
3763 
3764  GPUStaticInst*
3766  {
3767  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
3768  } // decode_OP_SOP2__S_MUL_I32
3769 
3770  GPUStaticInst*
3772  {
3773  return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
3774  } // decode_OP_SOP2__S_BFE_U32
3775 
3776  GPUStaticInst*
3778  {
3779  return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
3780  } // decode_OP_SOP2__S_BFE_I32
3781 
3782  GPUStaticInst*
3784  {
3785  return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
3786  } // decode_OP_SOP2__S_BFE_U64
3787 
3788  GPUStaticInst*
3790  {
3791  return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
3792  } // decode_OP_SOP2__S_BFE_I64
3793 
3794  GPUStaticInst*
3796  {
3797  return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
3798  } // decode_OP_SOP2__S_CBRANCH_G_FORK
3799 
3800  GPUStaticInst*
3802  {
3803  return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
3804  } // decode_OP_SOP2__S_ABSDIFF_I32
3805 
3806  GPUStaticInst*
3808  {
3809  return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
3810  } // decode_OP_SOP2__S_RFE_RESTORE_B64
3811 
3812  GPUStaticInst*
3814  {
3815  return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
3816  } // decode_OP_SOPK__S_MOVK_I32
3817 
3818  GPUStaticInst*
3820  {
3821  return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
3822  } // decode_OP_SOPK__S_CMOVK_I32
3823 
3824  GPUStaticInst*
3826  {
3827  return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
3828  } // decode_OP_SOPK__S_CMPK_EQ_I32
3829 
3830  GPUStaticInst*
3832  {
3833  return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
3834  } // decode_OP_SOPK__S_CMPK_LG_I32
3835 
3836  GPUStaticInst*
3838  {
3839  return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
3840  } // decode_OP_SOPK__S_CMPK_GT_I32
3841 
3842  GPUStaticInst*
3844  {
3845  return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
3846  } // decode_OP_SOPK__S_CMPK_GE_I32
3847 
3848  GPUStaticInst*
3850  {
3851  return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
3852  } // decode_OP_SOPK__S_CMPK_LT_I32
3853 
3854  GPUStaticInst*
3856  {
3857  return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
3858  } // decode_OP_SOPK__S_CMPK_LE_I32
3859 
3860  GPUStaticInst*
3862  {
3863  return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
3864  } // decode_OP_SOPK__S_CMPK_EQ_U32
3865 
3866  GPUStaticInst*
3868  {
3869  return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
3870  } // decode_OP_SOPK__S_CMPK_LG_U32
3871 
3872  GPUStaticInst*
3874  {
3875  return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
3876  } // decode_OP_SOPK__S_CMPK_GT_U32
3877 
3878  GPUStaticInst*
3880  {
3881  return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
3882  } // decode_OP_SOPK__S_CMPK_GE_U32
3883 
3884  GPUStaticInst*
3886  {
3887  return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
3888  } // decode_OP_SOPK__S_CMPK_LT_U32
3889 
3890  GPUStaticInst*
3892  {
3893  return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
3894  } // decode_OP_SOPK__S_CMPK_LE_U32
3895 
3896  GPUStaticInst*
3898  {
3899  return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
3900  } // decode_OP_SOPK__S_ADDK_I32
3901 
3902  GPUStaticInst*
3904  {
3905  return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
3906  } // decode_OP_SOPK__S_MULK_I32
3907 
3908  GPUStaticInst*
3910  {
3911  return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
3912  } // decode_OP_SOPK__S_CBRANCH_I_FORK
3913 
3914  GPUStaticInst*
3916  {
3917  return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
3918  } // decode_OP_SOPK__S_GETREG_B32
3919 
3920  GPUStaticInst*
3922  {
3923  return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
3924  } // decode_OP_SOPK__S_SETREG_B32
3925 
3926  GPUStaticInst*
3928  {
3929  return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
3930  } // decode_OP_SOPK__S_SETREG_IMM32_B32
3931 
3932  GPUStaticInst*
3934  {
3935  return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
3936  } // decode_OP_EXP
3937 
3938  GPUStaticInst*
3940  {
3941  return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3);
3942  } // decode_OPU_VOP3__V_CMP_CLASS_F32
3943 
3944  GPUStaticInst*
3946  {
3947  return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3);
3948  } // decode_OPU_VOP3__V_CMPX_CLASS_F32
3949 
3950  GPUStaticInst*
3952  {
3953  return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3);
3954  } // decode_OPU_VOP3__V_CMP_CLASS_F64
3955 
3956  GPUStaticInst*
3958  {
3959  return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3);
3960  } // decode_OPU_VOP3__V_CMPX_CLASS_F64
3961 
3962  GPUStaticInst*
3964  {
3965  return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3);
3966  } // decode_OPU_VOP3__V_CMP_CLASS_F16
3967 
3968  GPUStaticInst*
3970  {
3971  return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3);
3972  } // decode_OPU_VOP3__V_CMPX_CLASS_F16
3973 
3974  GPUStaticInst*
3976  {
3977  return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3);
3978  } // decode_OPU_VOP3__V_CMP_F_F16
3979 
3980  GPUStaticInst*
3982  {
3983  return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3);
3984  } // decode_OPU_VOP3__V_CMP_LT_F16
3985 
3986  GPUStaticInst*
3988  {
3989  return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3);
3990  } // decode_OPU_VOP3__V_CMP_EQ_F16
3991 
3992  GPUStaticInst*
3994  {
3995  return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3);
3996  } // decode_OPU_VOP3__V_CMP_LE_F16
3997 
3998  GPUStaticInst*
4000  {
4001  return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3);
4002  } // decode_OPU_VOP3__V_CMP_GT_F16
4003 
4004  GPUStaticInst*
4006  {
4007  return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3);
4008  } // decode_OPU_VOP3__V_CMP_LG_F16
4009 
4010  GPUStaticInst*
4012  {
4013  return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3);
4014  } // decode_OPU_VOP3__V_CMP_GE_F16
4015 
4016  GPUStaticInst*
4018  {
4019  return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3);
4020  } // decode_OPU_VOP3__V_CMP_O_F16
4021 
4022  GPUStaticInst*
4024  {
4025  return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3);
4026  } // decode_OPU_VOP3__V_CMP_U_F16
4027 
4028  GPUStaticInst*
4030  {
4031  return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3);
4032  } // decode_OPU_VOP3__V_CMP_NGE_F16
4033 
4034  GPUStaticInst*
4036  {
4037  return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3);
4038  } // decode_OPU_VOP3__V_CMP_NLG_F16
4039 
4040  GPUStaticInst*
4042  {
4043  return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3);
4044  } // decode_OPU_VOP3__V_CMP_NGT_F16
4045 
4046  GPUStaticInst*
4048  {
4049  return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3);
4050  } // decode_OPU_VOP3__V_CMP_NLE_F16
4051 
4052  GPUStaticInst*
4054  {
4055  return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3);
4056  } // decode_OPU_VOP3__V_CMP_NEQ_F16
4057 
4058  GPUStaticInst*
4060  {
4061  return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3);
4062  } // decode_OPU_VOP3__V_CMP_NLT_F16
4063 
4064  GPUStaticInst*
4066  {
4067  return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3);
4068  } // decode_OPU_VOP3__V_CMP_TRU_F16
4069 
4070  GPUStaticInst*
4072  {
4073  return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3);
4074  } // decode_OPU_VOP3__V_CMPX_F_F16
4075 
4076  GPUStaticInst*
4078  {
4079  return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3);
4080  } // decode_OPU_VOP3__V_CMPX_LT_F16
4081 
4082  GPUStaticInst*
4084  {
4085  return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3);
4086  } // decode_OPU_VOP3__V_CMPX_EQ_F16
4087 
4088  GPUStaticInst*
4090  {
4091  return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3);
4092  } // decode_OPU_VOP3__V_CMPX_LE_F16
4093 
4094  GPUStaticInst*
4096  {
4097  return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3);
4098  } // decode_OPU_VOP3__V_CMPX_GT_F16
4099 
4100  GPUStaticInst*
4102  {
4103  return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3);
4104  } // decode_OPU_VOP3__V_CMPX_LG_F16
4105 
4106  GPUStaticInst*
4108  {
4109  return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3);
4110  } // decode_OPU_VOP3__V_CMPX_GE_F16
4111 
4112  GPUStaticInst*
4114  {
4115  return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3);
4116  } // decode_OPU_VOP3__V_CMPX_O_F16
4117 
4118  GPUStaticInst*
4120  {
4121  return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3);
4122  } // decode_OPU_VOP3__V_CMPX_U_F16
4123 
4124  GPUStaticInst*
4126  {
4127  return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3);
4128  } // decode_OPU_VOP3__V_CMPX_NGE_F16
4129 
4130  GPUStaticInst*
4132  {
4133  return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3);
4134  } // decode_OPU_VOP3__V_CMPX_NLG_F16
4135 
4136  GPUStaticInst*
4138  {
4139  return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3);
4140  } // decode_OPU_VOP3__V_CMPX_NGT_F16
4141 
4142  GPUStaticInst*
4144  {
4145  return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3);
4146  } // decode_OPU_VOP3__V_CMPX_NLE_F16
4147 
4148  GPUStaticInst*
4150  {
4151  return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3);
4152  } // decode_OPU_VOP3__V_CMPX_NEQ_F16
4153 
4154  GPUStaticInst*
4156  {
4157  return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3);
4158  } // decode_OPU_VOP3__V_CMPX_NLT_F16
4159 
4160  GPUStaticInst*
4162  {
4163  return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3);
4164  } // decode_OPU_VOP3__V_CMPX_TRU_F16
4165 
4166  GPUStaticInst*
4168  {
4169  return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3);
4170  } // decode_OPU_VOP3__V_CMP_F_F32
4171 
4172  GPUStaticInst*
4174  {
4175  return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3);
4176  } // decode_OPU_VOP3__V_CMP_LT_F32
4177 
4178  GPUStaticInst*
4180  {
4181  return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3);
4182  } // decode_OPU_VOP3__V_CMP_EQ_F32
4183 
4184  GPUStaticInst*
4186  {
4187  return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3);
4188  } // decode_OPU_VOP3__V_CMP_LE_F32
4189 
4190  GPUStaticInst*
4192  {
4193  return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3);
4194  } // decode_OPU_VOP3__V_CMP_GT_F32
4195 
4196  GPUStaticInst*
4198  {
4199  return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3);
4200  } // decode_OPU_VOP3__V_CMP_LG_F32
4201 
4202  GPUStaticInst*
4204  {
4205  return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3);
4206  } // decode_OPU_VOP3__V_CMP_GE_F32
4207 
4208  GPUStaticInst*
4210  {
4211  return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3);
4212  } // decode_OPU_VOP3__V_CMP_O_F32
4213 
4214  GPUStaticInst*
4216  {
4217  return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3);
4218  } // decode_OPU_VOP3__V_CMP_U_F32
4219 
4220  GPUStaticInst*
4222  {
4223  return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3);
4224  } // decode_OPU_VOP3__V_CMP_NGE_F32
4225 
4226  GPUStaticInst*
4228  {
4229  return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3);
4230  } // decode_OPU_VOP3__V_CMP_NLG_F32
4231 
4232  GPUStaticInst*
4234  {
4235  return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3);
4236  } // decode_OPU_VOP3__V_CMP_NGT_F32
4237 
4238  GPUStaticInst*
4240  {
4241  return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3);
4242  } // decode_OPU_VOP3__V_CMP_NLE_F32
4243 
4244  GPUStaticInst*
4246  {
4247  return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3);
4248  } // decode_OPU_VOP3__V_CMP_NEQ_F32
4249 
4250  GPUStaticInst*
4252  {
4253  return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3);
4254  } // decode_OPU_VOP3__V_CMP_NLT_F32
4255 
4256  GPUStaticInst*
4258  {
4259  return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3);
4260  } // decode_OPU_VOP3__V_CMP_TRU_F32
4261 
4262  GPUStaticInst*
4264  {
4265  return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3);
4266  } // decode_OPU_VOP3__V_CMPX_F_F32
4267 
4268  GPUStaticInst*
4270  {
4271  return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3);
4272  } // decode_OPU_VOP3__V_CMPX_LT_F32
4273 
4274  GPUStaticInst*
4276  {
4277  return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3);
4278  } // decode_OPU_VOP3__V_CMPX_EQ_F32
4279 
4280  GPUStaticInst*
4282  {
4283  return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3);
4284  } // decode_OPU_VOP3__V_CMPX_LE_F32
4285 
4286  GPUStaticInst*
4288  {
4289  return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3);
4290  } // decode_OPU_VOP3__V_CMPX_GT_F32
4291 
4292  GPUStaticInst*
4294  {
4295  return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3);
4296  } // decode_OPU_VOP3__V_CMPX_LG_F32
4297 
4298  GPUStaticInst*
4300  {
4301  return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3);
4302  } // decode_OPU_VOP3__V_CMPX_GE_F32
4303 
4304  GPUStaticInst*
4306  {
4307  return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3);
4308  } // decode_OPU_VOP3__V_CMPX_O_F32
4309 
4310  GPUStaticInst*
4312  {
4313  return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3);
4314  } // decode_OPU_VOP3__V_CMPX_U_F32
4315 
4316  GPUStaticInst*
4318  {
4319  return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3);
4320  } // decode_OPU_VOP3__V_CMPX_NGE_F32
4321 
4322  GPUStaticInst*
4324  {
4325  return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3);
4326  } // decode_OPU_VOP3__V_CMPX_NLG_F32
4327 
4328  GPUStaticInst*
4330  {
4331  return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3);
4332  } // decode_OPU_VOP3__V_CMPX_NGT_F32
4333 
4334  GPUStaticInst*
4336  {
4337  return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3);
4338  } // decode_OPU_VOP3__V_CMPX_NLE_F32
4339 
4340  GPUStaticInst*
4342  {
4343  return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3);
4344  } // decode_OPU_VOP3__V_CMPX_NEQ_F32
4345 
4346  GPUStaticInst*
4348  {
4349  return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3);
4350  } // decode_OPU_VOP3__V_CMPX_NLT_F32
4351 
4352  GPUStaticInst*
4354  {
4355  return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3);
4356  } // decode_OPU_VOP3__V_CMPX_TRU_F32
4357 
4358  GPUStaticInst*
4360  {
4361  return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3);
4362  } // decode_OPU_VOP3__V_CMP_F_F64
4363 
4364  GPUStaticInst*
4366  {
4367  return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3);
4368  } // decode_OPU_VOP3__V_CMP_LT_F64
4369 
4370  GPUStaticInst*
4372  {
4373  return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3);
4374  } // decode_OPU_VOP3__V_CMP_EQ_F64
4375 
4376  GPUStaticInst*
4378  {
4379  return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3);
4380  } // decode_OPU_VOP3__V_CMP_LE_F64
4381 
4382  GPUStaticInst*
4384  {
4385  return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3);
4386  } // decode_OPU_VOP3__V_CMP_GT_F64
4387 
4388  GPUStaticInst*
4390  {
4391  return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3);
4392  } // decode_OPU_VOP3__V_CMP_LG_F64
4393 
4394  GPUStaticInst*
4396  {
4397  return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3);
4398  } // decode_OPU_VOP3__V_CMP_GE_F64
4399 
4400  GPUStaticInst*
4402  {
4403  return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3);
4404  } // decode_OPU_VOP3__V_CMP_O_F64
4405 
4406  GPUStaticInst*
4408  {
4409  return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3);
4410  } // decode_OPU_VOP3__V_CMP_U_F64
4411 
4412  GPUStaticInst*
4414  {
4415  return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3);
4416  } // decode_OPU_VOP3__V_CMP_NGE_F64
4417 
4418  GPUStaticInst*
4420  {
4421  return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3);
4422  } // decode_OPU_VOP3__V_CMP_NLG_F64
4423 
4424  GPUStaticInst*
4426  {
4427  return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3);
4428  } // decode_OPU_VOP3__V_CMP_NGT_F64
4429 
4430  GPUStaticInst*
4432  {
4433  return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3);
4434  } // decode_OPU_VOP3__V_CMP_NLE_F64
4435 
4436  GPUStaticInst*
4438  {
4439  return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3);
4440  } // decode_OPU_VOP3__V_CMP_NEQ_F64
4441 
4442  GPUStaticInst*
4444  {
4445  return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3);
4446  } // decode_OPU_VOP3__V_CMP_NLT_F64
4447 
4448  GPUStaticInst*
4450  {
4451  return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3);
4452  } // decode_OPU_VOP3__V_CMP_TRU_F64
4453 
4454  GPUStaticInst*
4456  {
4457  return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3);
4458  } // decode_OPU_VOP3__V_CMPX_F_F64
4459 
4460  GPUStaticInst*
4462  {
4463  return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3);
4464  } // decode_OPU_VOP3__V_CMPX_LT_F64
4465 
4466  GPUStaticInst*
4468  {
4469  return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3);
4470  } // decode_OPU_VOP3__V_CMPX_EQ_F64
4471 
4472  GPUStaticInst*
4474  {
4475  return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3);
4476  } // decode_OPU_VOP3__V_CMPX_LE_F64
4477 
4478  GPUStaticInst*
4480  {
4481  return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3);
4482  } // decode_OPU_VOP3__V_CMPX_GT_F64
4483 
4484  GPUStaticInst*
4486  {
4487  return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3);
4488  } // decode_OPU_VOP3__V_CMPX_LG_F64
4489 
4490  GPUStaticInst*
4492  {
4493  return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3);
4494  } // decode_OPU_VOP3__V_CMPX_GE_F64
4495 
4496  GPUStaticInst*
4498  {
4499  return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3);
4500  } // decode_OPU_VOP3__V_CMPX_O_F64
4501 
4502  GPUStaticInst*
4504  {
4505  return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3);
4506  } // decode_OPU_VOP3__V_CMPX_U_F64
4507 
4508  GPUStaticInst*
4510  {
4511  return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3);
4512  } // decode_OPU_VOP3__V_CMPX_NGE_F64
4513 
4514  GPUStaticInst*
4516  {
4517  return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3);
4518  } // decode_OPU_VOP3__V_CMPX_NLG_F64
4519 
4520  GPUStaticInst*
4522  {
4523  return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3);
4524  } // decode_OPU_VOP3__V_CMPX_NGT_F64
4525 
4526  GPUStaticInst*
4528  {
4529  return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3);
4530  } // decode_OPU_VOP3__V_CMPX_NLE_F64
4531 
4532  GPUStaticInst*
4534  {
4535  return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3);
4536  } // decode_OPU_VOP3__V_CMPX_NEQ_F64
4537 
4538  GPUStaticInst*
4540  {
4541  return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3);
4542  } // decode_OPU_VOP3__V_CMPX_NLT_F64
4543 
4544  GPUStaticInst*
4546  {
4547  return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3);
4548  } // decode_OPU_VOP3__V_CMPX_TRU_F64
4549 
4550  GPUStaticInst*
4552  {
4553  return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3);
4554  } // decode_OPU_VOP3__V_CMP_F_I16
4555 
4556  GPUStaticInst*
4558  {
4559  return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3);
4560  } // decode_OPU_VOP3__V_CMP_LT_I16
4561 
4562  GPUStaticInst*
4564  {
4565  return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3);
4566  } // decode_OPU_VOP3__V_CMP_EQ_I16
4567 
4568  GPUStaticInst*
4570  {
4571  return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3);
4572  } // decode_OPU_VOP3__V_CMP_LE_I16
4573 
4574  GPUStaticInst*
4576  {
4577  return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3);
4578  } // decode_OPU_VOP3__V_CMP_GT_I16
4579 
4580  GPUStaticInst*
4582  {
4583  return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3);
4584  } // decode_OPU_VOP3__V_CMP_NE_I16
4585 
4586  GPUStaticInst*
4588  {
4589  return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3);
4590  } // decode_OPU_VOP3__V_CMP_GE_I16
4591 
4592  GPUStaticInst*
4594  {
4595  return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3);
4596  } // decode_OPU_VOP3__V_CMP_T_I16
4597 
4598  GPUStaticInst*
4600  {
4601  return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3);
4602  } // decode_OPU_VOP3__V_CMP_F_U16
4603 
4604  GPUStaticInst*
4606  {
4607  return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3);
4608  } // decode_OPU_VOP3__V_CMP_LT_U16
4609 
4610  GPUStaticInst*
4612  {
4613  return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3);
4614  } // decode_OPU_VOP3__V_CMP_EQ_U16
4615 
4616  GPUStaticInst*
4618  {
4619  return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3);
4620  } // decode_OPU_VOP3__V_CMP_LE_U16
4621 
4622  GPUStaticInst*
4624  {
4625  return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3);
4626  } // decode_OPU_VOP3__V_CMP_GT_U16
4627 
4628  GPUStaticInst*
4630  {
4631  return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3);
4632  } // decode_OPU_VOP3__V_CMP_NE_U16
4633 
4634  GPUStaticInst*
4636  {
4637  return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3);
4638  } // decode_OPU_VOP3__V_CMP_GE_U16
4639 
4640  GPUStaticInst*
4642  {
4643  return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3);
4644  } // decode_OPU_VOP3__V_CMP_T_U16
4645 
4646  GPUStaticInst*
4648  {
4649  return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3);
4650  } // decode_OPU_VOP3__V_CMPX_F_I16
4651 
4652  GPUStaticInst*
4654  {
4655  return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3);
4656  } // decode_OPU_VOP3__V_CMPX_LT_I16
4657 
4658  GPUStaticInst*
4660  {
4661  return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3);
4662  } // decode_OPU_VOP3__V_CMPX_EQ_I16
4663 
4664  GPUStaticInst*
4666  {
4667  return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3);
4668  } // decode_OPU_VOP3__V_CMPX_LE_I16
4669 
4670  GPUStaticInst*
4672  {
4673  return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3);
4674  } // decode_OPU_VOP3__V_CMPX_GT_I16
4675 
4676  GPUStaticInst*
4678  {
4679  return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3);
4680  } // decode_OPU_VOP3__V_CMPX_NE_I16
4681 
4682  GPUStaticInst*
4684  {
4685  return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3);
4686  } // decode_OPU_VOP3__V_CMPX_GE_I16
4687 
4688  GPUStaticInst*
4690  {
4691  return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3);
4692  } // decode_OPU_VOP3__V_CMPX_T_I16
4693 
4694  GPUStaticInst*
4696  {
4697  return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3);
4698  } // decode_OPU_VOP3__V_CMPX_F_U16
4699 
4700  GPUStaticInst*
4702  {
4703  return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3);
4704  } // decode_OPU_VOP3__V_CMPX_LT_U16
4705 
4706  GPUStaticInst*
4708  {
4709  return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3);
4710  } // decode_OPU_VOP3__V_CMPX_EQ_U16
4711 
4712  GPUStaticInst*
4714  {
4715  return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3);
4716  } // decode_OPU_VOP3__V_CMPX_LE_U16
4717 
4718  GPUStaticInst*
4720  {
4721  return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3);
4722  } // decode_OPU_VOP3__V_CMPX_GT_U16
4723 
4724  GPUStaticInst*
4726  {
4727  return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3);
4728  } // decode_OPU_VOP3__V_CMPX_NE_U16
4729 
4730  GPUStaticInst*
4732  {
4733  return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3);
4734  } // decode_OPU_VOP3__V_CMPX_GE_U16
4735 
4736  GPUStaticInst*
4738  {
4739  return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3);
4740  } // decode_OPU_VOP3__V_CMPX_T_U16
4741 
4742  GPUStaticInst*
4744  {
4745  return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3);
4746  } // decode_OPU_VOP3__V_CMP_F_I32
4747 
4748  GPUStaticInst*
4750  {
4751  return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3);
4752  } // decode_OPU_VOP3__V_CMP_LT_I32
4753 
4754  GPUStaticInst*
4756  {
4757  return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3);
4758  } // decode_OPU_VOP3__V_CMP_EQ_I32
4759 
4760  GPUStaticInst*
4762  {
4763  return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3);
4764  } // decode_OPU_VOP3__V_CMP_LE_I32
4765 
4766  GPUStaticInst*
4768  {
4769  return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3);
4770  } // decode_OPU_VOP3__V_CMP_GT_I32
4771 
4772  GPUStaticInst*
4774  {
4775  return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3);
4776  } // decode_OPU_VOP3__V_CMP_NE_I32
4777 
4778  GPUStaticInst*
4780  {
4781  return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3);
4782  } // decode_OPU_VOP3__V_CMP_GE_I32
4783 
4784  GPUStaticInst*
4786  {
4787  return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3);
4788  } // decode_OPU_VOP3__V_CMP_T_I32
4789 
4790  GPUStaticInst*
4792  {
4793  return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3);
4794  } // decode_OPU_VOP3__V_CMP_F_U32
4795 
4796  GPUStaticInst*
4798  {
4799  return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3);
4800  } // decode_OPU_VOP3__V_CMP_LT_U32
4801 
4802  GPUStaticInst*
4804  {
4805  return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3);
4806  } // decode_OPU_VOP3__V_CMP_EQ_U32
4807 
4808  GPUStaticInst*
4810  {
4811  return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3);
4812  } // decode_OPU_VOP3__V_CMP_LE_U32
4813 
4814  GPUStaticInst*
4816  {
4817  return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3);
4818  } // decode_OPU_VOP3__V_CMP_GT_U32
4819 
4820  GPUStaticInst*
4822  {
4823  return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3);
4824  } // decode_OPU_VOP3__V_CMP_NE_U32
4825 
4826  GPUStaticInst*
4828  {
4829  return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3);
4830  } // decode_OPU_VOP3__V_CMP_GE_U32
4831 
4832  GPUStaticInst*
4834  {
4835  return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3);
4836  } // decode_OPU_VOP3__V_CMP_T_U32
4837 
4838  GPUStaticInst*
4840  {
4841  return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3);
4842  } // decode_OPU_VOP3__V_CMPX_F_I32
4843 
4844  GPUStaticInst*
4846  {
4847  return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3);
4848  } // decode_OPU_VOP3__V_CMPX_LT_I32
4849 
4850  GPUStaticInst*
4852  {
4853  return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3);
4854  } // decode_OPU_VOP3__V_CMPX_EQ_I32
4855 
4856  GPUStaticInst*
4858  {
4859  return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3);
4860  } // decode_OPU_VOP3__V_CMPX_LE_I32
4861 
4862  GPUStaticInst*
4864  {
4865  return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3);
4866  } // decode_OPU_VOP3__V_CMPX_GT_I32
4867 
4868  GPUStaticInst*
4870  {
4871  return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3);
4872  } // decode_OPU_VOP3__V_CMPX_NE_I32
4873 
4874  GPUStaticInst*
4876  {
4877  return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3);
4878  } // decode_OPU_VOP3__V_CMPX_GE_I32
4879 
4880  GPUStaticInst*
4882  {
4883  return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3);
4884  } // decode_OPU_VOP3__V_CMPX_T_I32
4885 
4886  GPUStaticInst*
4888  {
4889  return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3);
4890  } // decode_OPU_VOP3__V_CMPX_F_U32
4891 
4892  GPUStaticInst*
4894  {
4895  return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3);
4896  } // decode_OPU_VOP3__V_CMPX_LT_U32
4897 
4898  GPUStaticInst*
4900  {
4901  return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3);
4902  } // decode_OPU_VOP3__V_CMPX_EQ_U32
4903 
4904  GPUStaticInst*
4906  {
4907  return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3);
4908  } // decode_OPU_VOP3__V_CMPX_LE_U32
4909 
4910  GPUStaticInst*
4912  {
4913  return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3);
4914  } // decode_OPU_VOP3__V_CMPX_GT_U32
4915 
4916  GPUStaticInst*
4918  {
4919  return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3);
4920  } // decode_OPU_VOP3__V_CMPX_NE_U32
4921 
4922  GPUStaticInst*
4924  {
4925  return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3);
4926  } // decode_OPU_VOP3__V_CMPX_GE_U32
4927 
4928  GPUStaticInst*
4930  {
4931  return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3);
4932  } // decode_OPU_VOP3__V_CMPX_T_U32
4933 
4934  GPUStaticInst*
4936  {
4937  return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3);
4938  } // decode_OPU_VOP3__V_CMP_F_I64
4939 
4940  GPUStaticInst*
4942  {
4943  return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3);
4944  } // decode_OPU_VOP3__V_CMP_LT_I64
4945 
4946  GPUStaticInst*
4948  {
4949  return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3);
4950  } // decode_OPU_VOP3__V_CMP_EQ_I64
4951 
4952  GPUStaticInst*
4954  {
4955  return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3);
4956  } // decode_OPU_VOP3__V_CMP_LE_I64
4957 
4958  GPUStaticInst*
4960  {
4961  return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3);
4962  } // decode_OPU_VOP3__V_CMP_GT_I64
4963 
4964  GPUStaticInst*
4966  {
4967  return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3);
4968  } // decode_OPU_VOP3__V_CMP_NE_I64
4969 
4970  GPUStaticInst*
4972  {
4973  return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3);
4974  } // decode_OPU_VOP3__V_CMP_GE_I64
4975 
4976  GPUStaticInst*
4978  {
4979  return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3);
4980  } // decode_OPU_VOP3__V_CMP_T_I64
4981 
4982  GPUStaticInst*
4984  {
4985  return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3);
4986  } // decode_OPU_VOP3__V_CMP_F_U64
4987 
4988  GPUStaticInst*
4990  {
4991  return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3);
4992  } // decode_OPU_VOP3__V_CMP_LT_U64
4993 
4994  GPUStaticInst*
4996  {
4997  return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3);
4998  } // decode_OPU_VOP3__V_CMP_EQ_U64
4999 
5000  GPUStaticInst*
5002  {
5003  return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3);
5004  } // decode_OPU_VOP3__V_CMP_LE_U64
5005 
5006  GPUStaticInst*
5008  {
5009  return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3);
5010  } // decode_OPU_VOP3__V_CMP_GT_U64
5011 
5012  GPUStaticInst*
5014  {
5015  return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3);
5016  } // decode_OPU_VOP3__V_CMP_NE_U64
5017 
5018  GPUStaticInst*
5020  {
5021  return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3);
5022  } // decode_OPU_VOP3__V_CMP_GE_U64
5023 
5024  GPUStaticInst*
5026  {
5027  return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3);
5028  } // decode_OPU_VOP3__V_CMP_T_U64
5029 
5030  GPUStaticInst*
5032  {
5033  return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3);
5034  } // decode_OPU_VOP3__V_CMPX_F_I64
5035 
5036  GPUStaticInst*
5038  {
5039  return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3);
5040  } // decode_OPU_VOP3__V_CMPX_LT_I64
5041 
5042  GPUStaticInst*
5044  {
5045  return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3);
5046  } // decode_OPU_VOP3__V_CMPX_EQ_I64
5047 
5048  GPUStaticInst*
5050  {
5051  return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3);
5052  } // decode_OPU_VOP3__V_CMPX_LE_I64
5053 
5054  GPUStaticInst*
5056  {
5057  return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3);
5058  } // decode_OPU_VOP3__V_CMPX_GT_I64
5059 
5060  GPUStaticInst*
5062  {
5063  return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3);
5064  } // decode_OPU_VOP3__V_CMPX_NE_I64
5065 
5066  GPUStaticInst*
5068  {
5069  return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3);
5070  } // decode_OPU_VOP3__V_CMPX_GE_I64
5071 
5072  GPUStaticInst*
5074  {
5075  return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3);
5076  } // decode_OPU_VOP3__V_CMPX_T_I64
5077 
5078  GPUStaticInst*
5080  {
5081  return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3);
5082  } // decode_OPU_VOP3__V_CMPX_F_U64
5083 
5084  GPUStaticInst*
5086  {
5087  return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3);
5088  } // decode_OPU_VOP3__V_CMPX_LT_U64
5089 
5090  GPUStaticInst*
5092  {
5093  return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3);
5094  } // decode_OPU_VOP3__V_CMPX_EQ_U64
5095 
5096  GPUStaticInst*
5098  {
5099  return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3);
5100  } // decode_OPU_VOP3__V_CMPX_LE_U64
5101 
5102  GPUStaticInst*
5104  {
5105  return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3);
5106  } // decode_OPU_VOP3__V_CMPX_GT_U64
5107 
5108  GPUStaticInst*
5110  {
5111  return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3);
5112  } // decode_OPU_VOP3__V_CMPX_NE_U64
5113 
5114  GPUStaticInst*
5116  {
5117  return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3);
5118  } // decode_OPU_VOP3__V_CMPX_GE_U64
5119 
5120  GPUStaticInst*
5122  {
5123  return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3);
5124  } // decode_OPU_VOP3__V_CMPX_T_U64
5125 
5126  GPUStaticInst*
5128  {
5129  return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3);
5130  } // decode_OPU_VOP3__V_CNDMASK_B32
5131 
5132  GPUStaticInst*
5134  {
5135  return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3);
5136  } // decode_OPU_VOP3__V_ADD_F32
5137 
5138  GPUStaticInst*
5140  {
5141  return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3);
5142  } // decode_OPU_VOP3__V_SUB_F32
5143 
5144  GPUStaticInst*
5146  {
5147  return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3);
5148  } // decode_OPU_VOP3__V_SUBREV_F32
5149 
5150  GPUStaticInst*
5152  {
5153  return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3);
5154  } // decode_OPU_VOP3__V_MUL_LEGACY_F32
5155 
5156  GPUStaticInst*
5158  {
5159  return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3);
5160  } // decode_OPU_VOP3__V_MUL_F32
5161 
5162  GPUStaticInst*
5164  {
5165  return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3);
5166  } // decode_OPU_VOP3__V_MUL_I32_I24
5167 
5168  GPUStaticInst*
5170  {
5171  return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3);
5172  } // decode_OPU_VOP3__V_MUL_HI_I32_I24
5173 
5174  GPUStaticInst*
5176  {
5177  return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3);
5178  } // decode_OPU_VOP3__V_MUL_U32_U24
5179 
5180  GPUStaticInst*
5182  {
5183  return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3);
5184  } // decode_OPU_VOP3__V_MUL_HI_U32_U24
5185 
5186  GPUStaticInst*
5188  {
5189  return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3);
5190  } // decode_OPU_VOP3__V_MIN_F32
5191 
5192  GPUStaticInst*
5194  {
5195  return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3);
5196  } // decode_OPU_VOP3__V_MAX_F32
5197 
5198  GPUStaticInst*
5200  {
5201  return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3);
5202  } // decode_OPU_VOP3__V_MIN_I32
5203 
5204  GPUStaticInst*
5206  {
5207  return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3);
5208  } // decode_OPU_VOP3__V_MAX_I32
5209 
5210  GPUStaticInst*
5212  {
5213  return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3);
5214  } // decode_OPU_VOP3__V_MIN_U32
5215 
5216  GPUStaticInst*
5218  {
5219  return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3);
5220  } // decode_OPU_VOP3__V_MAX_U32
5221 
5222  GPUStaticInst*
5224  {
5225  return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3);
5226  } // decode_OPU_VOP3__V_LSHRREV_B32
5227 
5228  GPUStaticInst*
5230  {
5231  return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3);
5232  } // decode_OPU_VOP3__V_ASHRREV_I32
5233 
5234  GPUStaticInst*
5236  {
5237  return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3);
5238  } // decode_OPU_VOP3__V_LSHLREV_B32
5239 
5240  GPUStaticInst*
5242  {
5243  return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3);
5244  } // decode_OPU_VOP3__V_AND_B32
5245 
5246  GPUStaticInst*
5248  {
5249  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3);
5250  } // decode_OPU_VOP3__V_OR_B32
5251 
5252  GPUStaticInst*
5254  {
5255  return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3);
5256  } // decode_OPU_VOP3__V_XOR_B32
5257 
5258  GPUStaticInst*
5260  {
5261  return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3);
5262  } // decode_OPU_VOP3__V_MAC_F32
5263 
5264  GPUStaticInst*
5266  {
5267  return new Inst_VOP3__V_ADD_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5268  } // decode_OPU_VOP3__V_ADD_U32
5269 
5270  GPUStaticInst*
5272  {
5273  return new Inst_VOP3__V_SUB_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5274  } // decode_OPU_VOP3__V_SUB_U32
5275 
5276  GPUStaticInst*
5278  {
5279  return new Inst_VOP3__V_SUBREV_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5280  } // decode_OPU_VOP3__V_SUBREV_U32
5281 
5282  GPUStaticInst*
5284  {
5285  return new Inst_VOP3__V_ADDC_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5286  } // decode_OPU_VOP3__V_ADDC_U32
5287 
5288  GPUStaticInst*
5290  {
5291  return new Inst_VOP3__V_SUBB_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5292  } // decode_OPU_VOP3__V_SUBB_U32
5293 
5294  GPUStaticInst*
5296  {
5297  return new Inst_VOP3__V_SUBBREV_U32(&iFmt->iFmt_VOP3_SDST_ENC);
5298  } // decode_OPU_VOP3__V_SUBBREV_U32
5299 
5300  GPUStaticInst*
5302  {
5303  return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3);
5304  } // decode_OPU_VOP3__V_ADD_F16
5305 
5306  GPUStaticInst*
5308  {
5309  return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3);
5310  } // decode_OPU_VOP3__V_SUB_F16
5311 
5312  GPUStaticInst*
5314  {
5315  return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3);
5316  } // decode_OPU_VOP3__V_SUBREV_F16
5317 
5318  GPUStaticInst*
5320  {
5321  return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3);
5322  } // decode_OPU_VOP3__V_MUL_F16
5323 
5324  GPUStaticInst*
5326  {
5327  return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3);
5328  } // decode_OPU_VOP3__V_MAC_F16
5329 
5330  GPUStaticInst*
5332  {
5333  return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3);
5334  } // decode_OPU_VOP3__V_ADD_U16
5335 
5336  GPUStaticInst*
5338  {
5339  return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3);
5340  } // decode_OPU_VOP3__V_SUB_U16
5341 
5342  GPUStaticInst*
5344  {
5345  return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3);
5346  } // decode_OPU_VOP3__V_SUBREV_U16
5347 
5348  GPUStaticInst*
5350  {
5351  return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3);
5352  } // decode_OPU_VOP3__V_MUL_LO_U16
5353 
5354  GPUStaticInst*
5356  {
5357  return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3);
5358  } // decode_OPU_VOP3__V_LSHLREV_B16
5359 
5360  GPUStaticInst*
5362  {
5363  return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3);
5364  } // decode_OPU_VOP3__V_LSHRREV_B16
5365 
5366  GPUStaticInst*
5368  {
5369  return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3);
5370  } // decode_OPU_VOP3__V_ASHRREV_I16
5371 
5372  GPUStaticInst*
5374  {
5375  return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3);
5376  } // decode_OPU_VOP3__V_MAX_F16
5377 
5378  GPUStaticInst*
5380  {
5381  return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3);
5382  } // decode_OPU_VOP3__V_MIN_F16
5383 
5384  GPUStaticInst*
5386  {
5387  return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3);
5388  } // decode_OPU_VOP3__V_MAX_U16
5389 
5390  GPUStaticInst*
5392  {
5393  return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3);
5394  } // decode_OPU_VOP3__V_MAX_I16
5395 
5396  GPUStaticInst*
5398  {
5399  return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3);
5400  } // decode_OPU_VOP3__V_MIN_U16
5401 
5402  GPUStaticInst*
5404  {
5405  return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3);
5406  } // decode_OPU_VOP3__V_MIN_I16
5407 
5408  GPUStaticInst*
5410  {
5411  return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3);
5412  } // decode_OPU_VOP3__V_LDEXP_F16
5413 
5414  GPUStaticInst*
5416  {
5417  return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3);
5418  } // decode_OPU_VOP3__V_NOP
5419 
5420  GPUStaticInst*
5422  {
5423  return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3);
5424  } // decode_OPU_VOP3__V_MOV_B32
5425 
5426  GPUStaticInst*
5428  {
5429  return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3);
5430  } // decode_OPU_VOP3__V_CVT_I32_F64
5431 
5432  GPUStaticInst*
5434  {
5435  return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3);
5436  } // decode_OPU_VOP3__V_CVT_F64_I32
5437 
5438  GPUStaticInst*
5440  {
5441  return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3);
5442  } // decode_OPU_VOP3__V_CVT_F32_I32
5443 
5444  GPUStaticInst*
5446  {
5447  return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3);
5448  } // decode_OPU_VOP3__V_CVT_F32_U32
5449 
5450  GPUStaticInst*
5452  {
5453  return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3);
5454  } // decode_OPU_VOP3__V_CVT_U32_F32
5455 
5456  GPUStaticInst*
5458  {
5459  return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3);
5460  } // decode_OPU_VOP3__V_CVT_I32_F32
5461 
5462  GPUStaticInst*
5464  {
5465  return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3);
5466  } // decode_OPU_VOP3__V_MOV_FED_B32
5467 
5468  GPUStaticInst*
5470  {
5471  return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3);
5472  } // decode_OPU_VOP3__V_CVT_F16_F32
5473 
5474  GPUStaticInst*
5476  {
5477  return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3);
5478  } // decode_OPU_VOP3__V_CVT_F32_F16
5479 
5480  GPUStaticInst*
5482  {
5483  return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3);
5484  } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
5485 
5486  GPUStaticInst*
5488  {
5489  return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3);
5490  } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
5491 
5492  GPUStaticInst*
5494  {
5495  return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3);
5496  } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
5497 
5498  GPUStaticInst*
5500  {
5501  return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3);
5502  } // decode_OPU_VOP3__V_CVT_F32_F64
5503 
5504  GPUStaticInst*
5506  {
5507  return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3);
5508  } // decode_OPU_VOP3__V_CVT_F64_F32
5509 
5510  GPUStaticInst*
5512  {
5513  return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3);
5514  } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
5515 
5516  GPUStaticInst*
5518  {
5519  return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3);
5520  } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
5521 
5522  GPUStaticInst*
5524  {
5525  return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3);
5526  } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
5527 
5528  GPUStaticInst*
5530  {
5531  return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3);
5532  } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
5533 
5534  GPUStaticInst*
5536  {
5537  return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3);
5538  } // decode_OPU_VOP3__V_CVT_U32_F64
5539 
5540  GPUStaticInst*
5542  {
5543  return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3);
5544  } // decode_OPU_VOP3__V_CVT_F64_U32
5545 
5546  GPUStaticInst*
5548  {
5549  return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3);
5550  } // decode_OPU_VOP3__V_TRUNC_F64
5551 
5552  GPUStaticInst*
5554  {
5555  return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3);
5556  } // decode_OPU_VOP3__V_CEIL_F64
5557 
5558  GPUStaticInst*
5560  {
5561  return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3);
5562  } // decode_OPU_VOP3__V_RNDNE_F64
5563 
5564  GPUStaticInst*
5566  {
5567  return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3);
5568  } // decode_OPU_VOP3__V_FLOOR_F64
5569 
5570  GPUStaticInst*
5572  {
5573  return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3);
5574  } // decode_OPU_VOP3__V_FRACT_F32
5575 
5576  GPUStaticInst*
5578  {
5579  return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3);
5580  } // decode_OPU_VOP3__V_TRUNC_F32
5581 
5582  GPUStaticInst*
5584  {
5585  return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3);
5586  } // decode_OPU_VOP3__V_CEIL_F32
5587 
5588  GPUStaticInst*
5590  {
5591  return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3);
5592  } // decode_OPU_VOP3__V_RNDNE_F32
5593 
5594  GPUStaticInst*
5596  {
5597  return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3);
5598  } // decode_OPU_VOP3__V_FLOOR_F32
5599 
5600  GPUStaticInst*
5602  {
5603  return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3);
5604  } // decode_OPU_VOP3__V_EXP_F32
5605 
5606  GPUStaticInst*
5608  {
5609  return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3);
5610  } // decode_OPU_VOP3__V_LOG_F32
5611 
5612  GPUStaticInst*
5614  {
5615  return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3);
5616  } // decode_OPU_VOP3__V_RCP_F32
5617 
5618  GPUStaticInst*
5620  {
5621  return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3);
5622  } // decode_OPU_VOP3__V_RCP_IFLAG_F32
5623 
5624  GPUStaticInst*
5626  {
5627  return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3);
5628  } // decode_OPU_VOP3__V_RSQ_F32
5629 
5630  GPUStaticInst*
5632  {
5633  return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3);
5634  } // decode_OPU_VOP3__V_RCP_F64
5635 
5636  GPUStaticInst*
5638  {
5639  return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3);
5640  } // decode_OPU_VOP3__V_RSQ_F64
5641 
5642  GPUStaticInst*
5644  {
5645  return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3);
5646  } // decode_OPU_VOP3__V_SQRT_F32
5647 
5648  GPUStaticInst*
5650  {
5651  return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3);
5652  } // decode_OPU_VOP3__V_SQRT_F64
5653 
5654  GPUStaticInst*
5656  {
5657  return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3);
5658  } // decode_OPU_VOP3__V_SIN_F32
5659 
5660  GPUStaticInst*
5662  {
5663  return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3);
5664  } // decode_OPU_VOP3__V_COS_F32
5665 
5666  GPUStaticInst*
5668  {
5669  return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3);
5670  } // decode_OPU_VOP3__V_NOT_B32
5671 
5672  GPUStaticInst*
5674  {
5675  return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3);
5676  } // decode_OPU_VOP3__V_BFREV_B32
5677 
5678  GPUStaticInst*
5680  {
5681  return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3);
5682  } // decode_OPU_VOP3__V_FFBH_U32
5683 
5684  GPUStaticInst*
5686  {
5687  return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3);
5688  } // decode_OPU_VOP3__V_FFBL_B32
5689 
5690  GPUStaticInst*
5692  {
5693  return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3);
5694  } // decode_OPU_VOP3__V_FFBH_I32
5695 
5696  GPUStaticInst*
5698  {
5699  return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3);
5700  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
5701 
5702  GPUStaticInst*
5704  {
5705  return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3);
5706  } // decode_OPU_VOP3__V_FREXP_MANT_F64
5707 
5708  GPUStaticInst*
5710  {
5711  return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3);
5712  } // decode_OPU_VOP3__V_FRACT_F64
5713 
5714  GPUStaticInst*
5716  {
5717  return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3);
5718  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
5719 
5720  GPUStaticInst*
5722  {
5723  return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3);
5724  } // decode_OPU_VOP3__V_FREXP_MANT_F32
5725 
5726  GPUStaticInst*
5728  {
5729  return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3);
5730  } // decode_OPU_VOP3__V_CLREXCP
5731 
5732  GPUStaticInst*
5734  {
5735  return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3);
5736  } // decode_OPU_VOP3__V_CVT_F16_U16
5737 
5738  GPUStaticInst*
5740  {
5741  return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3);
5742  } // decode_OPU_VOP3__V_CVT_F16_I16
5743 
5744  GPUStaticInst*
5746  {
5747  return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3);
5748  } // decode_OPU_VOP3__V_CVT_U16_F16
5749 
5750  GPUStaticInst*
5752  {
5753  return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3);
5754  } // decode_OPU_VOP3__V_CVT_I16_F16
5755 
5756  GPUStaticInst*
5758  {
5759  return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3);
5760  } // decode_OPU_VOP3__V_RCP_F16
5761 
5762  GPUStaticInst*
5764  {
5765  return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3);
5766  } // decode_OPU_VOP3__V_SQRT_F16
5767 
5768  GPUStaticInst*
5770  {
5771  return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3);
5772  } // decode_OPU_VOP3__V_RSQ_F16
5773 
5774  GPUStaticInst*
5776  {
5777  return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3);
5778  } // decode_OPU_VOP3__V_LOG_F16
5779 
5780  GPUStaticInst*
5782  {
5783  return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3);
5784  } // decode_OPU_VOP3__V_EXP_F16
5785 
5786  GPUStaticInst*
5788  {
5789  return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3);
5790  } // decode_OPU_VOP3__V_FREXP_MANT_F16
5791 
5792  GPUStaticInst*
5794  {
5795  return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3);
5796  } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
5797 
5798  GPUStaticInst*
5800  {
5801  return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3);
5802  } // decode_OPU_VOP3__V_FLOOR_F16
5803 
5804  GPUStaticInst*
5806  {
5807  return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3);
5808  } // decode_OPU_VOP3__V_CEIL_F16
5809 
5810  GPUStaticInst*
5812  {
5813  return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3);
5814  } // decode_OPU_VOP3__V_TRUNC_F16
5815 
5816  GPUStaticInst*
5818  {
5819  return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3);
5820  } // decode_OPU_VOP3__V_RNDNE_F16
5821 
5822  GPUStaticInst*
5824  {
5825  return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3);
5826  } // decode_OPU_VOP3__V_FRACT_F16
5827 
5828  GPUStaticInst*
5830  {
5831  return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3);
5832  } // decode_OPU_VOP3__V_SIN_F16
5833 
5834  GPUStaticInst*
5836  {
5837  return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3);
5838  } // decode_OPU_VOP3__V_COS_F16
5839 
5840  GPUStaticInst*
5842  {
5843  return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3);
5844  } // decode_OPU_VOP3__V_EXP_LEGACY_F32
5845 
5846  GPUStaticInst*
5848  {
5849  return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3);
5850  } // decode_OPU_VOP3__V_LOG_LEGACY_F32
5851 
5852  GPUStaticInst*
5854  {
5855  return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3);
5856  } // decode_OPU_VOP3__V_MAD_LEGACY_F32
5857 
5858  GPUStaticInst*
5860  {
5861  return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3);
5862  } // decode_OPU_VOP3__V_MAD_F32
5863 
5864  GPUStaticInst*
5866  {
5867  return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3);
5868  } // decode_OPU_VOP3__V_MAD_I32_I24
5869 
5870  GPUStaticInst*
5872  {
5873  return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3);
5874  } // decode_OPU_VOP3__V_MAD_U32_U24
5875 
5876  GPUStaticInst*
5878  {
5879  return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3);
5880  } // decode_OPU_VOP3__V_CUBEID_F32
5881 
5882  GPUStaticInst*
5884  {
5885  return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3);
5886  } // decode_OPU_VOP3__V_CUBESC_F32
5887 
5888  GPUStaticInst*
5890  {
5891  return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3);
5892  } // decode_OPU_VOP3__V_CUBETC_F32
5893 
5894  GPUStaticInst*
5896  {
5897  return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3);
5898  } // decode_OPU_VOP3__V_CUBEMA_F32
5899 
5900  GPUStaticInst*
5902  {
5903  return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3);
5904  } // decode_OPU_VOP3__V_BFE_U32
5905 
5906  GPUStaticInst*
5908  {
5909  return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3);
5910  } // decode_OPU_VOP3__V_BFE_I32
5911 
5912  GPUStaticInst*
5914  {
5915  return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3);
5916  } // decode_OPU_VOP3__V_BFI_B32
5917 
5918  GPUStaticInst*
5920  {
5921  return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3);
5922  } // decode_OPU_VOP3__V_FMA_F32
5923 
5924  GPUStaticInst*
5926  {
5927  return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3);
5928  } // decode_OPU_VOP3__V_FMA_F64
5929 
5930  GPUStaticInst*
5932  {
5933  return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3);
5934  } // decode_OPU_VOP3__V_LERP_U8
5935 
5936  GPUStaticInst*
5938  {
5939  return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3);
5940  } // decode_OPU_VOP3__V_ALIGNBIT_B32
5941 
5942  GPUStaticInst*
5944  {
5945  return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3);
5946  } // decode_OPU_VOP3__V_ALIGNBYTE_B32
5947 
5948  GPUStaticInst*
5950  {
5951  return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3);
5952  } // decode_OPU_VOP3__V_MIN3_F32
5953 
5954  GPUStaticInst*
5956  {
5957  return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3);
5958  } // decode_OPU_VOP3__V_MIN3_I32
5959 
5960  GPUStaticInst*
5962  {
5963  return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3);
5964  } // decode_OPU_VOP3__V_MIN3_U32
5965 
5966  GPUStaticInst*
5968  {
5969  return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3);
5970  } // decode_OPU_VOP3__V_MAX3_F32
5971 
5972  GPUStaticInst*
5974  {
5975  return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3);
5976  } // decode_OPU_VOP3__V_MAX3_I32
5977 
5978  GPUStaticInst*
5980  {
5981  return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3);
5982  } // decode_OPU_VOP3__V_MAX3_U32
5983 
5984  GPUStaticInst*
5986  {
5987  return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3);
5988  } // decode_OPU_VOP3__V_MED3_F32
5989 
5990  GPUStaticInst*
5992  {
5993  return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3);
5994  } // decode_OPU_VOP3__V_MED3_I32
5995 
5996  GPUStaticInst*
5998  {
5999  return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3);
6000  } // decode_OPU_VOP3__V_MED3_U32
6001 
6002  GPUStaticInst*
6004  {
6005  return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3);
6006  } // decode_OPU_VOP3__V_SAD_U8
6007 
6008  GPUStaticInst*
6010  {
6011  return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3);
6012  } // decode_OPU_VOP3__V_SAD_HI_U8
6013 
6014  GPUStaticInst*
6016  {
6017  return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3);
6018  } // decode_OPU_VOP3__V_SAD_U16
6019 
6020  GPUStaticInst*
6022  {
6023  return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3);
6024  } // decode_OPU_VOP3__V_SAD_U32
6025 
6026  GPUStaticInst*
6028  {
6029  return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3);
6030  } // decode_OPU_VOP3__V_CVT_PK_U8_F32
6031 
6032  GPUStaticInst*
6034  {
6035  return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3);
6036  } // decode_OPU_VOP3__V_DIV_FIXUP_F32
6037 
6038  GPUStaticInst*
6040  {
6041  return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3);
6042  } // decode_OPU_VOP3__V_DIV_FIXUP_F64
6043 
6044  GPUStaticInst*
6046  {
6048  } // decode_OPU_VOP3__V_DIV_SCALE_F32
6049 
6050  GPUStaticInst*
6052  {
6054  } // decode_OPU_VOP3__V_DIV_SCALE_F64
6055 
6056  GPUStaticInst*
6058  {
6059  return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3);
6060  } // decode_OPU_VOP3__V_DIV_FMAS_F32
6061 
6062  GPUStaticInst*
6064  {
6065  return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3);
6066  } // decode_OPU_VOP3__V_DIV_FMAS_F64
6067 
6068  GPUStaticInst*
6070  {
6071  return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3);
6072  } // decode_OPU_VOP3__V_MSAD_U8
6073 
6074  GPUStaticInst*
6076  {
6077  return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3);
6078  } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
6079 
6080  GPUStaticInst*
6082  {
6083  return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3);
6084  } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
6085 
6086  GPUStaticInst*
6088  {
6089  return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3);
6090  } // decode_OPU_VOP3__V_MQSAD_U32_U8
6091 
6092  GPUStaticInst*
6094  {
6095  return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3_SDST_ENC);
6096  } // decode_OPU_VOP3__V_MAD_U64_U32
6097 
6098  GPUStaticInst*
6100  {
6101  return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3_SDST_ENC);
6102  } // decode_OPU_VOP3__V_MAD_I64_I32
6103 
6104  GPUStaticInst*
6106  {
6107  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3);
6108  } // decode_OPU_VOP3__V_MAD_F16
6109 
6110  GPUStaticInst*
6112  {
6113  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3);
6114  } // decode_OPU_VOP3__V_MAD_U16
6115 
6116  GPUStaticInst*
6118  {
6119  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3);
6120  } // decode_OPU_VOP3__V_MAD_I16
6121 
6122  GPUStaticInst*
6124  {
6125  return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3);
6126  } // decode_OPU_VOP3__V_PERM_B32
6127 
6128  GPUStaticInst*
6130  {
6131  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3);
6132  } // decode_OPU_VOP3__V_FMA_F16
6133 
6134  GPUStaticInst*
6136  {
6137  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3);
6138  } // decode_OPU_VOP3__V_DIV_FIXUP_F16
6139 
6140  GPUStaticInst*
6142  {
6143  return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3);
6144  } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
6145 
6146  GPUStaticInst*
6148  {
6149  return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3);
6150  } // decode_OPU_VOP3__V_INTERP_P1_F32
6151 
6152  GPUStaticInst*
6154  {
6155  return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3);
6156  } // decode_OPU_VOP3__V_INTERP_P2_F32
6157 
6158  GPUStaticInst*
6160  {
6161  return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3);
6162  } // decode_OPU_VOP3__V_INTERP_MOV_F32
6163 
6164  GPUStaticInst*
6166  {
6167  return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3);
6168  } // decode_OPU_VOP3__V_INTERP_P1LL_F16
6169 
6170  GPUStaticInst*
6172  {
6173  return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3);
6174  } // decode_OPU_VOP3__V_INTERP_P1LV_F16
6175 
6176  GPUStaticInst*
6178  {
6179  return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3);
6180  } // decode_OPU_VOP3__V_INTERP_P2_F16
6181 
6182  GPUStaticInst*
6184  {
6185  return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3);
6186  } // decode_OPU_VOP3__V_ADD_F64
6187 
6188  GPUStaticInst*
6190  {
6191  return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3);
6192  } // decode_OPU_VOP3__V_MUL_F64
6193 
6194  GPUStaticInst*
6196  {
6197  return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3);
6198  } // decode_OPU_VOP3__V_MIN_F64
6199 
6200  GPUStaticInst*
6202  {
6203  return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3);
6204  } // decode_OPU_VOP3__V_MAX_F64
6205 
6206  GPUStaticInst*
6208  {
6209  return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3);
6210  } // decode_OPU_VOP3__V_LDEXP_F64
6211 
6212  GPUStaticInst*
6214  {
6215  return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3);
6216  } // decode_OPU_VOP3__V_MUL_LO_U32
6217 
6218  GPUStaticInst*
6220  {
6221  return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3);
6222  } // decode_OPU_VOP3__V_MUL_HI_U32
6223 
6224  GPUStaticInst*
6226  {
6227  return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3);
6228  } // decode_OPU_VOP3__V_MUL_HI_I32
6229 
6230  GPUStaticInst*
6232  {
6233  return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3);
6234  } // decode_OPU_VOP3__V_LDEXP_F32
6235 
6236  GPUStaticInst*
6238  {
6239  return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3);
6240  } // decode_OPU_VOP3__V_READLANE_B32
6241 
6242  GPUStaticInst*
6244  {
6245  return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3);
6246  } // decode_OPU_VOP3__V_WRITELANE_B32
6247 
6248  GPUStaticInst*
6250  {
6251  return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3);
6252  } // decode_OPU_VOP3__V_BCNT_U32_B32
6253 
6254  GPUStaticInst*
6256  {
6257  return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3);
6258  } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
6259 
6260  GPUStaticInst*
6262  {
6263  return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3);
6264  } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
6265 
6266  GPUStaticInst*
6268  {
6269  return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3);
6270  } // decode_OPU_VOP3__V_LSHLREV_B64
6271 
6272  GPUStaticInst*
6274  {
6275  return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3);
6276  } // decode_OPU_VOP3__V_LSHRREV_B64
6277 
6278  GPUStaticInst*
6280  {
6281  return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3);
6282  } // decode_OPU_VOP3__V_ASHRREV_I64
6283 
6284  GPUStaticInst*
6286  {
6287  return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3);
6288  } // decode_OPU_VOP3__V_TRIG_PREOP_F64
6289 
6290  GPUStaticInst*
6292  {
6293  return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3);
6294  } // decode_OPU_VOP3__V_BFM_B32
6295 
6296  GPUStaticInst*
6298  {
6299  return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3);
6300  } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
6301 
6302  GPUStaticInst*
6304  {
6305  return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3);
6306  } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
6307 
6308  GPUStaticInst*
6310  {
6311  return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3);
6312  } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
6313 
6314  GPUStaticInst*
6316  {
6317  return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3);
6318  } // decode_OPU_VOP3__V_CVT_PK_U16_U32
6319 
6320  GPUStaticInst*
6322  {
6323  return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3);
6324  } // decode_OPU_VOP3__V_CVT_PK_I16_I32
6325 
6326  GPUStaticInst*
6328  {
6329  return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
6330  } // decode_OP_DS__DS_ADD_U32
6331 
6332  GPUStaticInst*
6334  {
6335  return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
6336  } // decode_OP_DS__DS_SUB_U32
6337 
6338  GPUStaticInst*
6340  {
6341  return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
6342  } // decode_OP_DS__DS_RSUB_U32
6343 
6344  GPUStaticInst*
6346  {
6347  return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
6348  } // decode_OP_DS__DS_INC_U32
6349 
6350  GPUStaticInst*
6352  {
6353  return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
6354  } // decode_OP_DS__DS_DEC_U32
6355 
6356  GPUStaticInst*
6358  {
6359  return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
6360  } // decode_OP_DS__DS_MIN_I32
6361 
6362  GPUStaticInst*
6364  {
6365  return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
6366  } // decode_OP_DS__DS_MAX_I32
6367 
6368  GPUStaticInst*
6370  {
6371  return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
6372  } // decode_OP_DS__DS_MIN_U32
6373 
6374  GPUStaticInst*
6376  {
6377  return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
6378  } // decode_OP_DS__DS_MAX_U32
6379 
6380  GPUStaticInst*
6382  {
6383  return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
6384  } // decode_OP_DS__DS_AND_B32
6385 
6386  GPUStaticInst*
6388  {
6389  return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
6390  } // decode_OP_DS__DS_OR_B32
6391 
6392  GPUStaticInst*
6394  {
6395  return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
6396  } // decode_OP_DS__DS_XOR_B32
6397 
6398  GPUStaticInst*
6400  {
6401  return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
6402  } // decode_OP_DS__DS_MSKOR_B32
6403 
6404  GPUStaticInst*
6406  {
6407  return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
6408  } // decode_OP_DS__DS_WRITE_B32
6409 
6410  GPUStaticInst*
6412  {
6413  return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
6414  } // decode_OP_DS__DS_WRITE2_B32
6415 
6416  GPUStaticInst*
6418  {
6419  return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
6420  } // decode_OP_DS__DS_WRITE2ST64_B32
6421 
6422  GPUStaticInst*
6424  {
6425  return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
6426  } // decode_OP_DS__DS_CMPST_B32
6427 
6428  GPUStaticInst*
6430  {
6431  return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
6432  } // decode_OP_DS__DS_CMPST_F32
6433 
6434  GPUStaticInst*
6436  {
6437  return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
6438  } // decode_OP_DS__DS_MIN_F32
6439 
6440  GPUStaticInst*
6442  {
6443  return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
6444  } // decode_OP_DS__DS_MAX_F32
6445 
6446  GPUStaticInst*
6448  {
6449  return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
6450  } // decode_OP_DS__DS_NOP
6451 
6452  GPUStaticInst*
6454  {
6455  return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
6456  } // decode_OP_DS__DS_ADD_F32
6457 
6458  GPUStaticInst*
6460  {
6461  return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
6462  } // decode_OP_DS__DS_WRITE_B8
6463 
6464  GPUStaticInst*
6466  {
6467  return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
6468  } // decode_OP_DS__DS_WRITE_B16
6469 
6470  GPUStaticInst*
6472  {
6473  return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
6474  } // decode_OP_DS__DS_ADD_RTN_U32
6475 
6476  GPUStaticInst*
6478  {
6479  return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
6480  } // decode_OP_DS__DS_SUB_RTN_U32
6481 
6482  GPUStaticInst*
6484  {
6485  return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
6486  } // decode_OP_DS__DS_RSUB_RTN_U32
6487 
6488  GPUStaticInst*
6490  {
6491  return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
6492  } // decode_OP_DS__DS_INC_RTN_U32
6493 
6494  GPUStaticInst*
6496  {
6497  return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
6498  } // decode_OP_DS__DS_DEC_RTN_U32
6499 
6500  GPUStaticInst*
6502  {
6503  return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
6504  } // decode_OP_DS__DS_MIN_RTN_I32
6505 
6506  GPUStaticInst*
6508  {
6509  return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
6510  } // decode_OP_DS__DS_MAX_RTN_I32
6511 
6512  GPUStaticInst*
6514  {
6515  return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
6516  } // decode_OP_DS__DS_MIN_RTN_U32
6517 
6518  GPUStaticInst*
6520  {
6521  return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
6522  } // decode_OP_DS__DS_MAX_RTN_U32
6523 
6524  GPUStaticInst*
6526  {
6527  return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
6528  } // decode_OP_DS__DS_AND_RTN_B32
6529 
6530  GPUStaticInst*
6532  {
6533  return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
6534  } // decode_OP_DS__DS_OR_RTN_B32
6535 
6536  GPUStaticInst*
6538  {
6539  return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
6540  } // decode_OP_DS__DS_XOR_RTN_B32
6541 
6542  GPUStaticInst*
6544  {
6545  return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
6546  } // decode_OP_DS__DS_MSKOR_RTN_B32
6547 
6548  GPUStaticInst*
6550  {
6551  return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
6552  } // decode_OP_DS__DS_WRXCHG_RTN_B32
6553 
6554  GPUStaticInst*
6556  {
6557  return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
6558  } // decode_OP_DS__DS_WRXCHG2_RTN_B32
6559 
6560  GPUStaticInst*
6562  {
6563  return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
6564  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
6565 
6566  GPUStaticInst*
6568  {
6569  return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
6570  } // decode_OP_DS__DS_CMPST_RTN_B32
6571 
6572  GPUStaticInst*
6574  {
6575  return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
6576  } // decode_OP_DS__DS_CMPST_RTN_F32
6577 
6578  GPUStaticInst*
6580  {
6581  return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
6582  } // decode_OP_DS__DS_MIN_RTN_F32
6583 
6584  GPUStaticInst*
6586  {
6587  return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
6588  } // decode_OP_DS__DS_MAX_RTN_F32
6589 
6590  GPUStaticInst*
6592  {
6593  return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
6594  } // decode_OP_DS__DS_WRAP_RTN_B32
6595 
6596  GPUStaticInst*
6598  {
6599  return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
6600  } // decode_OP_DS__DS_ADD_RTN_F32
6601 
6602  GPUStaticInst*
6604  {
6605  return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
6606  } // decode_OP_DS__DS_READ_B32
6607 
6608  GPUStaticInst*
6610  {
6611  return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
6612  } // decode_OP_DS__DS_READ2_B32
6613 
6614  GPUStaticInst*
6616  {
6617  return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
6618  } // decode_OP_DS__DS_READ2ST64_B32
6619 
6620  GPUStaticInst*
6622  {
6623  return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
6624  } // decode_OP_DS__DS_READ_I8
6625 
6626  GPUStaticInst*
6628  {
6629  return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
6630  } // decode_OP_DS__DS_READ_U8
6631 
6632  GPUStaticInst*
6634  {
6635  return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
6636  } // decode_OP_DS__DS_READ_I16
6637 
6638  GPUStaticInst*
6640  {
6641  return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
6642  } // decode_OP_DS__DS_READ_U16
6643 
6644  GPUStaticInst*
6646  {
6647  return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
6648  } // decode_OP_DS__DS_SWIZZLE_B32
6649 
6650  GPUStaticInst*
6652  {
6653  return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
6654  } // decode_OP_DS__DS_PERMUTE_B32
6655 
6656  GPUStaticInst*
6658  {
6659  return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
6660  } // decode_OP_DS__DS_BPERMUTE_B32
6661 
6662  GPUStaticInst*
6664  {
6665  return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
6666  } // decode_OP_DS__DS_ADD_U64
6667 
6668  GPUStaticInst*
6670  {
6671  return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
6672  } // decode_OP_DS__DS_SUB_U64
6673 
6674  GPUStaticInst*
6676  {
6677  return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
6678  } // decode_OP_DS__DS_RSUB_U64
6679 
6680  GPUStaticInst*
6682  {
6683  return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
6684  } // decode_OP_DS__DS_INC_U64
6685 
6686  GPUStaticInst*
6688  {
6689  return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
6690  } // decode_OP_DS__DS_DEC_U64
6691 
6692  GPUStaticInst*
6694  {
6695  return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
6696  } // decode_OP_DS__DS_MIN_I64
6697 
6698  GPUStaticInst*
6700  {
6701  return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
6702  } // decode_OP_DS__DS_MAX_I64
6703 
6704  GPUStaticInst*
6706  {
6707  return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
6708  } // decode_OP_DS__DS_MIN_U64
6709 
6710  GPUStaticInst*
6712  {
6713  return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
6714  } // decode_OP_DS__DS_MAX_U64
6715 
6716  GPUStaticInst*
6718  {
6719  return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
6720  } // decode_OP_DS__DS_AND_B64
6721 
6722  GPUStaticInst*
6724  {
6725  return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
6726  } // decode_OP_DS__DS_OR_B64
6727 
6728  GPUStaticInst*
6730  {
6731  return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
6732  } // decode_OP_DS__DS_XOR_B64
6733 
6734  GPUStaticInst*
6736  {
6737  return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
6738  } // decode_OP_DS__DS_MSKOR_B64
6739 
6740  GPUStaticInst*
6742  {
6743  return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
6744  } // decode_OP_DS__DS_WRITE_B64
6745 
6746  GPUStaticInst*
6748  {
6749  return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
6750  } // decode_OP_DS__DS_WRITE2_B64
6751 
6752  GPUStaticInst*
6754  {
6755  return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
6756  } // decode_OP_DS__DS_WRITE2ST64_B64
6757 
6758  GPUStaticInst*
6760  {
6761  return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
6762  } // decode_OP_DS__DS_CMPST_B64
6763 
6764  GPUStaticInst*
6766  {
6767  return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
6768  } // decode_OP_DS__DS_CMPST_F64
6769 
6770  GPUStaticInst*
6772  {
6773  return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
6774  } // decode_OP_DS__DS_MIN_F64
6775 
6776  GPUStaticInst*
6778  {
6779  return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
6780  } // decode_OP_DS__DS_MAX_F64
6781 
6782  GPUStaticInst*
6784  {
6785  return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
6786  } // decode_OP_DS__DS_ADD_RTN_U64
6787 
6788  GPUStaticInst*
6790  {
6791  return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
6792  } // decode_OP_DS__DS_SUB_RTN_U64
6793 
6794  GPUStaticInst*
6796  {
6797  return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
6798  } // decode_OP_DS__DS_RSUB_RTN_U64
6799 
6800  GPUStaticInst*
6802  {
6803  return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
6804  } // decode_OP_DS__DS_INC_RTN_U64
6805 
6806  GPUStaticInst*
6808  {
6809  return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
6810  } // decode_OP_DS__DS_DEC_RTN_U64
6811 
6812  GPUStaticInst*
6814  {
6815  return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
6816  } // decode_OP_DS__DS_MIN_RTN_I64
6817 
6818  GPUStaticInst*
6820  {
6821  return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
6822  } // decode_OP_DS__DS_MAX_RTN_I64
6823 
6824  GPUStaticInst*
6826  {
6827  return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
6828  } // decode_OP_DS__DS_MIN_RTN_U64
6829 
6830  GPUStaticInst*
6832  {
6833  return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
6834  } // decode_OP_DS__DS_MAX_RTN_U64
6835 
6836  GPUStaticInst*
6838  {
6839  return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
6840  } // decode_OP_DS__DS_AND_RTN_B64
6841 
6842  GPUStaticInst*
6844  {
6845  return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
6846  } // decode_OP_DS__DS_OR_RTN_B64
6847 
6848  GPUStaticInst*
6850  {
6851  return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
6852  } // decode_OP_DS__DS_XOR_RTN_B64
6853 
6854  GPUStaticInst*
6856  {
6857  return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
6858  } // decode_OP_DS__DS_MSKOR_RTN_B64
6859 
6860  GPUStaticInst*
6862  {
6863  return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
6864  } // decode_OP_DS__DS_WRXCHG_RTN_B64
6865 
6866  GPUStaticInst*
6868  {
6869  return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
6870  } // decode_OP_DS__DS_WRXCHG2_RTN_B64
6871 
6872  GPUStaticInst*
6874  {
6875  return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
6876  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
6877 
6878  GPUStaticInst*
6880  {
6881  return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
6882  } // decode_OP_DS__DS_CMPST_RTN_B64
6883 
6884  GPUStaticInst*
6886  {
6887  return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
6888  } // decode_OP_DS__DS_CMPST_RTN_F64
6889 
6890  GPUStaticInst*
6892  {
6893  return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
6894  } // decode_OP_DS__DS_MIN_RTN_F64
6895 
6896  GPUStaticInst*
6898  {
6899  return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
6900  } // decode_OP_DS__DS_MAX_RTN_F64
6901 
6902  GPUStaticInst*
6904  {
6905  return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
6906  } // decode_OP_DS__DS_READ_B64
6907 
6908  GPUStaticInst*
6910  {
6911  return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
6912  } // decode_OP_DS__DS_READ2_B64
6913 
6914  GPUStaticInst*
6916  {
6917  return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
6918  } // decode_OP_DS__DS_READ2ST64_B64
6919 
6920  GPUStaticInst*
6922  {
6923  return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
6924  } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
6925 
6926  GPUStaticInst*
6928  {
6929  return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
6930  } // decode_OP_DS__DS_ADD_SRC2_U32
6931 
6932  GPUStaticInst*
6934  {
6935  return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
6936  } // decode_OP_DS__DS_SUB_SRC2_U32
6937 
6938  GPUStaticInst*
6940  {
6941  return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
6942  } // decode_OP_DS__DS_RSUB_SRC2_U32
6943 
6944  GPUStaticInst*
6946  {
6947  return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
6948  } // decode_OP_DS__DS_INC_SRC2_U32
6949 
6950  GPUStaticInst*
6952  {
6953  return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
6954  } // decode_OP_DS__DS_DEC_SRC2_U32
6955 
6956  GPUStaticInst*
6958  {
6959  return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
6960  } // decode_OP_DS__DS_MIN_SRC2_I32
6961 
6962  GPUStaticInst*
6964  {
6965  return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
6966  } // decode_OP_DS__DS_MAX_SRC2_I32
6967 
6968  GPUStaticInst*
6970  {
6971  return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
6972  } // decode_OP_DS__DS_MIN_SRC2_U32
6973 
6974  GPUStaticInst*
6976  {
6977  return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
6978  } // decode_OP_DS__DS_MAX_SRC2_U32
6979 
6980  GPUStaticInst*
6982  {
6983  return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
6984  } // decode_OP_DS__DS_AND_SRC2_B32
6985 
6986  GPUStaticInst*
6988  {
6989  return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
6990  } // decode_OP_DS__DS_OR_SRC2_B32
6991 
6992  GPUStaticInst*
6994  {
6995  return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
6996  } // decode_OP_DS__DS_XOR_SRC2_B32
6997 
6998  GPUStaticInst*
7000  {
7001  return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
7002  } // decode_OP_DS__DS_WRITE_SRC2_B32
7003 
7004  GPUStaticInst*
7006  {
7007  return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
7008  } // decode_OP_DS__DS_MIN_SRC2_F32
7009 
7010  GPUStaticInst*
7012  {
7013  return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
7014  } // decode_OP_DS__DS_MAX_SRC2_F32
7015 
7016  GPUStaticInst*
7018  {
7019  return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
7020  } // decode_OP_DS__DS_ADD_SRC2_F32
7021 
7022  GPUStaticInst*
7024  {
7025  return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
7026  } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
7027 
7028  GPUStaticInst*
7030  {
7031  return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
7032  } // decode_OP_DS__DS_GWS_INIT
7033 
7034  GPUStaticInst*
7036  {
7037  return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
7038  } // decode_OP_DS__DS_GWS_SEMA_V
7039 
7040  GPUStaticInst*
7042  {
7043  return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
7044  } // decode_OP_DS__DS_GWS_SEMA_BR
7045 
7046  GPUStaticInst*
7048  {
7049  return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
7050  } // decode_OP_DS__DS_GWS_SEMA_P
7051 
7052  GPUStaticInst*
7054  {
7055  return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
7056  } // decode_OP_DS__DS_GWS_BARRIER
7057 
7058  GPUStaticInst*
7060  {
7061  return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
7062  } // decode_OP_DS__DS_CONSUME
7063 
7064  GPUStaticInst*
7066  {
7067  return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
7068  } // decode_OP_DS__DS_APPEND
7069 
7070  GPUStaticInst*
7072  {
7073  return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
7074  } // decode_OP_DS__DS_ORDERED_COUNT
7075 
7076  GPUStaticInst*
7078  {
7079  return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
7080  } // decode_OP_DS__DS_ADD_SRC2_U64
7081 
7082  GPUStaticInst*
7084  {
7085  return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
7086  } // decode_OP_DS__DS_SUB_SRC2_U64
7087 
7088  GPUStaticInst*
7090  {
7091  return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
7092  } // decode_OP_DS__DS_RSUB_SRC2_U64
7093 
7094  GPUStaticInst*
7096  {
7097  return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
7098  } // decode_OP_DS__DS_INC_SRC2_U64
7099 
7100  GPUStaticInst*
7102  {
7103  return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
7104  } // decode_OP_DS__DS_DEC_SRC2_U64
7105 
7106  GPUStaticInst*
7108  {
7109  return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
7110  } // decode_OP_DS__DS_MIN_SRC2_I64
7111 
7112  GPUStaticInst*
7114  {
7115  return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
7116  } // decode_OP_DS__DS_MAX_SRC2_I64
7117 
7118  GPUStaticInst*
7120  {
7121  return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
7122  } // decode_OP_DS__DS_MIN_SRC2_U64
7123 
7124  GPUStaticInst*
7126  {
7127  return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
7128  } // decode_OP_DS__DS_MAX_SRC2_U64
7129 
7130  GPUStaticInst*
7132  {
7133  return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
7134  } // decode_OP_DS__DS_AND_SRC2_B64
7135 
7136  GPUStaticInst*
7138  {
7139  return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
7140  } // decode_OP_DS__DS_OR_SRC2_B64
7141 
7142  GPUStaticInst*
7144  {
7145  return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
7146  } // decode_OP_DS__DS_XOR_SRC2_B64
7147 
7148  GPUStaticInst*
7150  {
7151  return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
7152  } // decode_OP_DS__DS_WRITE_SRC2_B64
7153 
7154  GPUStaticInst*
7156  {
7157  return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
7158  } // decode_OP_DS__DS_MIN_SRC2_F64
7159 
7160  GPUStaticInst*
7162  {
7163  return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
7164  } // decode_OP_DS__DS_MAX_SRC2_F64
7165 
7166  GPUStaticInst*
7168  {
7169  return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
7170  } // decode_OP_DS__DS_WRITE_B96
7171 
7172  GPUStaticInst*
7174  {
7175  return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
7176  } // decode_OP_DS__DS_WRITE_B128
7177 
7178  GPUStaticInst*
7180  {
7181  return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
7182  } // decode_OP_DS__DS_READ_B96
7183 
7184  GPUStaticInst*
7186  {
7187  return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
7188  } // decode_OP_DS__DS_READ_B128
7189 
7190  GPUStaticInst*
7192  {
7193  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
7194  } // decode_OP_FLAT__FLAT_LOAD_UBYTE
7195 
7196  GPUStaticInst*
7198  {
7199  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
7200  } // decode_OP_FLAT__FLAT_LOAD_SBYTE
7201 
7202  GPUStaticInst*
7204  {
7205  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
7206  } // decode_OP_FLAT__FLAT_LOAD_USHORT
7207 
7208  GPUStaticInst*
7210  {
7211  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
7212  } // decode_OP_FLAT__FLAT_LOAD_SSHORT
7213 
7214  GPUStaticInst*
7216  {
7217  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
7218  } // decode_OP_FLAT__FLAT_LOAD_DWORD
7219 
7220  GPUStaticInst*
7222  {
7223  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
7224  } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
7225 
7226  GPUStaticInst*
7228  {
7229  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
7230  } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
7231 
7232  GPUStaticInst*
7234  {
7235  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
7236  } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
7237 
7238  GPUStaticInst*
7240  {
7241  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
7242  } // decode_OP_FLAT__FLAT_STORE_BYTE
7243 
7244  GPUStaticInst*
7246  {
7247  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
7248  } // decode_OP_FLAT__FLAT_STORE_SHORT
7249 
7250  GPUStaticInst*
7252  {
7253  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
7254  } // decode_OP_FLAT__FLAT_STORE_DWORD
7255 
7256  GPUStaticInst*
7258  {
7259  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
7260  } // decode_OP_FLAT__FLAT_STORE_DWORDX2
7261 
7262  GPUStaticInst*
7264  {
7265  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
7266  } // decode_OP_FLAT__FLAT_STORE_DWORDX3
7267 
7268  GPUStaticInst*
7270  {
7271  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
7272  } // decode_OP_FLAT__FLAT_STORE_DWORDX4
7273 
7274  GPUStaticInst*
7276  {
7277  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
7278  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
7279 
7280  GPUStaticInst*
7282  {
7283  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
7284  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
7285 
7286  GPUStaticInst*
7288  {
7289  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
7290  } // decode_OP_FLAT__FLAT_ATOMIC_ADD
7291 
7292  GPUStaticInst*
7294  {
7295  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
7296  } // decode_OP_FLAT__FLAT_ATOMIC_SUB
7297 
7298  GPUStaticInst*
7300  {
7301  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
7302  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
7303 
7304  GPUStaticInst*
7306  {
7307  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
7308  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
7309 
7310  GPUStaticInst*
7312  {
7313  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
7314  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
7315 
7316  GPUStaticInst*
7318  {
7319  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
7320  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
7321 
7322  GPUStaticInst*
7324  {
7325  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
7326  } // decode_OP_FLAT__FLAT_ATOMIC_AND
7327 
7328  GPUStaticInst*
7330  {
7331  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
7332  } // decode_OP_FLAT__FLAT_ATOMIC_OR
7333 
7334  GPUStaticInst*
7336  {
7337  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
7338  } // decode_OP_FLAT__FLAT_ATOMIC_XOR
7339 
7340  GPUStaticInst*
7342  {
7343  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
7344  } // decode_OP_FLAT__FLAT_ATOMIC_INC
7345 
7346  GPUStaticInst*
7348  {
7349  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
7350  } // decode_OP_FLAT__FLAT_ATOMIC_DEC
7351 
7352  GPUStaticInst*
7354  {
7355  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
7356  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
7357 
7358  GPUStaticInst*
7360  {
7361  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
7362  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
7363 
7364  GPUStaticInst*
7366  {
7367  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
7368  } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
7369 
7370  GPUStaticInst*
7372  {
7373  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
7374  } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
7375 
7376  GPUStaticInst*
7378  {
7379  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
7380  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
7381 
7382  GPUStaticInst*
7384  {
7385  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
7386  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
7387 
7388  GPUStaticInst*
7390  {
7391  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
7392  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
7393 
7394  GPUStaticInst*
7396  {
7397  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
7398  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
7399 
7400  GPUStaticInst*
7402  {
7403  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
7404  } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
7405 
7406  GPUStaticInst*
7408  {
7409  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
7410  } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
7411 
7412  GPUStaticInst*
7414  {
7415  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
7416  } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
7417 
7418  GPUStaticInst*
7420  {
7421  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
7422  } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
7423 
7424  GPUStaticInst*
7426  {
7427  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
7428  } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
7429 
7430  GPUStaticInst*
7432  {
7433  return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
7434  } // decode_OP_MIMG__IMAGE_LOAD
7435 
7436  GPUStaticInst*
7438  {
7439  return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
7440  } // decode_OP_MIMG__IMAGE_LOAD_MIP
7441 
7442  GPUStaticInst*
7444  {
7445  return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
7446  } // decode_OP_MIMG__IMAGE_LOAD_PCK
7447 
7448  GPUStaticInst*
7450  {
7451  return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
7452  } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
7453 
7454  GPUStaticInst*
7456  {
7457  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
7458  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
7459 
7460  GPUStaticInst*
7462  {
7463  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
7464  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
7465 
7466  GPUStaticInst*
7468  {
7469  return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
7470  } // decode_OP_MIMG__IMAGE_STORE
7471 
7472  GPUStaticInst*
7474  {
7475  return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
7476  } // decode_OP_MIMG__IMAGE_STORE_MIP
7477 
7478  GPUStaticInst*
7480  {
7481  return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
7482  } // decode_OP_MIMG__IMAGE_STORE_PCK
7483 
7484  GPUStaticInst*
7486  {
7487  return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
7488  } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
7489 
7490  GPUStaticInst*
7492  {
7493  return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
7494  } // decode_OP_MIMG__IMAGE_GET_RESINFO
7495 
7496  GPUStaticInst*
7498  {
7499  return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
7500  } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
7501 
7502  GPUStaticInst*
7504  {
7505  return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
7506  } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
7507 
7508  GPUStaticInst*
7510  {
7511  return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
7512  } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
7513 
7514  GPUStaticInst*
7516  {
7517  return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
7518  } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
7519 
7520  GPUStaticInst*
7522  {
7523  return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
7524  } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
7525 
7526  GPUStaticInst*
7528  {
7529  return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
7530  } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
7531 
7532  GPUStaticInst*
7534  {
7535  return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
7536  } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
7537 
7538  GPUStaticInst*
7540  {
7541  return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
7542  } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
7543 
7544  GPUStaticInst*
7546  {
7547  return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
7548  } // decode_OP_MIMG__IMAGE_ATOMIC_AND
7549 
7550  GPUStaticInst*
7552  {
7553  return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
7554  } // decode_OP_MIMG__IMAGE_ATOMIC_OR
7555 
7556  GPUStaticInst*
7558  {
7559  return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
7560  } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
7561 
7562  GPUStaticInst*
7564  {
7565  return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
7566  } // decode_OP_MIMG__IMAGE_ATOMIC_INC
7567 
7568  GPUStaticInst*
7570  {
7571  return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
7572  } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
7573 
7574  GPUStaticInst*
7576  {
7577  return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
7578  } // decode_OP_MIMG__IMAGE_SAMPLE
7579 
7580  GPUStaticInst*
7582  {
7583  return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
7584  } // decode_OP_MIMG__IMAGE_SAMPLE_CL
7585 
7586  GPUStaticInst*
7588  {
7589  return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
7590  } // decode_OP_MIMG__IMAGE_SAMPLE_D
7591 
7592  GPUStaticInst*
7594  {
7595  return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
7596  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
7597 
7598  GPUStaticInst*
7600  {
7601  return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
7602  } // decode_OP_MIMG__IMAGE_SAMPLE_L
7603 
7604  GPUStaticInst*
7606  {
7607  return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
7608  } // decode_OP_MIMG__IMAGE_SAMPLE_B
7609 
7610  GPUStaticInst*
7612  {
7613  return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
7614  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
7615 
7616  GPUStaticInst*
7618  {
7619  return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
7620  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
7621 
7622  GPUStaticInst*
7624  {
7625  return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
7626  } // decode_OP_MIMG__IMAGE_SAMPLE_C
7627 
7628  GPUStaticInst*
7630  {
7631  return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
7632  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
7633 
7634  GPUStaticInst*
7636  {
7637  return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
7638  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
7639 
7640  GPUStaticInst*
7642  {
7643  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
7644  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
7645 
7646  GPUStaticInst*
7648  {
7649  return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
7650  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
7651 
7652  GPUStaticInst*
7654  {
7655  return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
7656  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
7657 
7658  GPUStaticInst*
7660  {
7661  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
7662  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
7663 
7664  GPUStaticInst*
7666  {
7667  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
7668  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
7669 
7670  GPUStaticInst*
7672  {
7673  return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
7674  } // decode_OP_MIMG__IMAGE_SAMPLE_O
7675 
7676  GPUStaticInst*
7678  {
7679  return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
7680  } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
7681 
7682  GPUStaticInst*
7684  {
7685  return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
7686  } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
7687 
7688  GPUStaticInst*
7690  {
7691  return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
7692  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
7693 
7694  GPUStaticInst*
7696  {
7697  return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
7698  } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
7699 
7700  GPUStaticInst*
7702  {
7703  return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
7704  } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
7705 
7706  GPUStaticInst*
7708  {
7709  return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
7710  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
7711 
7712  GPUStaticInst*
7714  {
7715  return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
7716  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
7717 
7718  GPUStaticInst*
7720  {
7721  return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
7722  } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
7723 
7724  GPUStaticInst*
7726  {
7727  return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
7728  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
7729 
7730  GPUStaticInst*
7732  {
7733  return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
7734  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
7735 
7736  GPUStaticInst*
7738  {
7739  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
7740  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
7741 
7742  GPUStaticInst*
7744  {
7745  return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
7746  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
7747 
7748  GPUStaticInst*
7750  {
7751  return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
7752  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
7753 
7754  GPUStaticInst*
7756  {
7757  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
7758  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
7759 
7760  GPUStaticInst*
7762  {
7763  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
7764  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
7765 
7766  GPUStaticInst*
7768  {
7769  return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
7770  } // decode_OP_MIMG__IMAGE_GATHER4
7771 
7772  GPUStaticInst*
7774  {
7775  return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
7776  } // decode_OP_MIMG__IMAGE_GATHER4_CL
7777 
7778  GPUStaticInst*
7780  {
7781  return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
7782  } // decode_OP_MIMG__IMAGE_GATHER4_L
7783 
7784  GPUStaticInst*
7786  {
7787  return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
7788  } // decode_OP_MIMG__IMAGE_GATHER4_B
7789 
7790  GPUStaticInst*
7792  {
7793  return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
7794  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
7795 
7796  GPUStaticInst*
7798  {
7799  return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
7800  } // decode_OP_MIMG__IMAGE_GATHER4_LZ
7801 
7802  GPUStaticInst*
7804  {
7805  return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
7806  } // decode_OP_MIMG__IMAGE_GATHER4_C
7807 
7808  GPUStaticInst*
7810  {
7811  return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
7812  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
7813 
7814  GPUStaticInst*
7816  {
7817  return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
7818  } // decode_OP_MIMG__IMAGE_GATHER4_C_L
7819 
7820  GPUStaticInst*
7822  {
7823  return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
7824  } // decode_OP_MIMG__IMAGE_GATHER4_C_B
7825 
7826  GPUStaticInst*
7828  {
7829  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
7830  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
7831 
7832  GPUStaticInst*
7834  {
7835  return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
7836  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
7837 
7838  GPUStaticInst*
7840  {
7841  return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
7842  } // decode_OP_MIMG__IMAGE_GATHER4_O
7843 
7844  GPUStaticInst*
7846  {
7847  return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
7848  } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
7849 
7850  GPUStaticInst*
7852  {
7853  return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
7854  } // decode_OP_MIMG__IMAGE_GATHER4_L_O
7855 
7856  GPUStaticInst*
7858  {
7859  return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
7860  } // decode_OP_MIMG__IMAGE_GATHER4_B_O
7861 
7862  GPUStaticInst*
7864  {
7865  return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
7866  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
7867 
7868  GPUStaticInst*
7870  {
7871  return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
7872  } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
7873 
7874  GPUStaticInst*
7876  {
7877  return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
7878  } // decode_OP_MIMG__IMAGE_GATHER4_C_O
7879 
7880  GPUStaticInst*
7882  {
7883  return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
7884  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
7885 
7886  GPUStaticInst*
7888  {
7889  return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
7890  } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
7891 
7892  GPUStaticInst*
7894  {
7895  return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
7896  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
7897 
7898  GPUStaticInst*
7900  {
7901  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
7902  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
7903 
7904  GPUStaticInst*
7906  {
7907  return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
7908  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
7909 
7910  GPUStaticInst*
7912  {
7913  return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
7914  } // decode_OP_MIMG__IMAGE_GET_LOD
7915 
7916  GPUStaticInst*
7918  {
7919  return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
7920  } // decode_OP_MIMG__IMAGE_SAMPLE_CD
7921 
7922  GPUStaticInst*
7924  {
7925  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
7926  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
7927 
7928  GPUStaticInst*
7930  {
7931  return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
7932  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
7933 
7934  GPUStaticInst*
7936  {
7937  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
7938  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
7939 
7940  GPUStaticInst*
7942  {
7943  return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
7944  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
7945 
7946  GPUStaticInst*
7948  {
7949  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
7950  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
7951 
7952  GPUStaticInst*
7954  {
7955  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
7956  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
7957 
7958  GPUStaticInst*
7960  {
7961  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
7962  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
7963 
7964  GPUStaticInst*
7966  {
7967  return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
7968  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
7969 
7970  GPUStaticInst*
7972  {
7974  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
7975 
7976  GPUStaticInst*
7978  {
7980  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
7981 
7982  GPUStaticInst*
7984  {
7986  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
7987 
7988  GPUStaticInst*
7990  {
7992  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
7993 
7994  GPUStaticInst*
7996  {
7998  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
7999 
8000  GPUStaticInst*
8002  {
8004  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
8005 
8006  GPUStaticInst*
8008  {
8010  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
8011 
8012  GPUStaticInst*
8014  {
8016  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
8017 
8018  GPUStaticInst*
8020  {
8022  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
8023 
8024  GPUStaticInst*
8026  {
8028  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
8029 
8030  GPUStaticInst*
8032  {
8034  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
8035 
8036  GPUStaticInst*
8038  {
8040  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
8041 
8042  GPUStaticInst*
8044  {
8046  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
8047 
8048  GPUStaticInst*
8050  {
8052  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
8053 
8054  GPUStaticInst*
8056  {
8057  return new
8059  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
8060 
8061  GPUStaticInst*
8063  {
8064  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
8065  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
8066 
8067  GPUStaticInst*
8069  {
8070  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
8071  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
8072 
8073  GPUStaticInst*
8075  {
8077  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
8078 
8079  GPUStaticInst*
8081  {
8083  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
8084 
8085  GPUStaticInst*
8087  {
8088  return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
8089  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
8090 
8091  GPUStaticInst*
8093  {
8095  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
8096 
8097  GPUStaticInst*
8099  {
8101  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
8102 
8103  GPUStaticInst*
8105  {
8107  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
8108 
8109  GPUStaticInst*
8111  {
8113  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
8114 
8115  GPUStaticInst*
8117  {
8119  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
8120 
8121  GPUStaticInst*
8123  {
8125  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
8126 
8127  GPUStaticInst*
8129  {
8131  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
8132 
8133  GPUStaticInst*
8135  {
8137  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
8138 
8139  GPUStaticInst*
8141  {
8143  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
8144 
8145  GPUStaticInst*
8147  {
8149  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
8150 
8151  GPUStaticInst*
8153  {
8155  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
8156 
8157  GPUStaticInst*
8159  {
8160  return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
8161  } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
8162 
8163  GPUStaticInst*
8165  {
8166  return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
8167  } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
8168 
8169  GPUStaticInst*
8171  {
8172  return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
8173  } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
8174 
8175  GPUStaticInst*
8177  {
8178  return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
8179  } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
8180 
8181  GPUStaticInst*
8183  {
8184  return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
8185  } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
8186 
8187  GPUStaticInst*
8189  {
8190  return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
8191  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
8192 
8193  GPUStaticInst*
8195  {
8196  return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
8197  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
8198 
8199  GPUStaticInst*
8201  {
8202  return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
8203  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
8204 
8205  GPUStaticInst*
8207  {
8208  return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
8209  } // decode_OP_MUBUF__BUFFER_STORE_BYTE
8210 
8211  GPUStaticInst*
8213  {
8214  return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
8215  } // decode_OP_MUBUF__BUFFER_STORE_SHORT
8216 
8217  GPUStaticInst*
8219  {
8220  return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
8221  } // decode_OP_MUBUF__BUFFER_STORE_DWORD
8222 
8223  GPUStaticInst*
8225  {
8226  return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
8227  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
8228 
8229  GPUStaticInst*
8231  {
8232  return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
8233  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
8234 
8235  GPUStaticInst*
8237  {
8238  return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
8239  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
8240 
8241  GPUStaticInst*
8243  {
8245  } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
8246 
8247  GPUStaticInst*
8249  {
8250  return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
8251  } // decode_OP_MUBUF__BUFFER_WBINVL1
8252 
8253  GPUStaticInst*
8255  {
8256  return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
8257  } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
8258 
8259  GPUStaticInst*
8261  {
8262  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
8263  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
8264 
8265  GPUStaticInst*
8267  {
8268  return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
8269  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
8270 
8271  GPUStaticInst*
8273  {
8274  return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
8275  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
8276 
8277  GPUStaticInst*
8279  {
8280  return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
8281  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
8282 
8283  GPUStaticInst*
8285  {
8286  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
8287  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
8288 
8289  GPUStaticInst*
8291  {
8292  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
8293  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
8294 
8295  GPUStaticInst*
8297  {
8298  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
8299  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
8300 
8301  GPUStaticInst*
8303  {
8304  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
8305  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
8306 
8307  GPUStaticInst*
8309  {
8310  return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
8311  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
8312 
8313  GPUStaticInst*
8315  {
8316  return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
8317  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
8318 
8319  GPUStaticInst*
8321  {
8322  return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
8323  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
8324 
8325  GPUStaticInst*
8327  {
8328  return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
8329  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
8330 
8331  GPUStaticInst*
8333  {
8334  return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
8335  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
8336 
8337  GPUStaticInst*
8339  {
8340  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
8341  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
8342 
8343  GPUStaticInst*
8345  {
8347  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
8348 
8349  GPUStaticInst*
8351  {
8352  return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
8353  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
8354 
8355  GPUStaticInst*
8357  {
8358  return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
8359  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
8360 
8361  GPUStaticInst*
8363  {
8364  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
8365  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
8366 
8367  GPUStaticInst*
8369  {
8370  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
8371  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
8372 
8373  GPUStaticInst*
8375  {
8376  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
8377  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
8378 
8379  GPUStaticInst*
8381  {
8382  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
8383  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
8384 
8385  GPUStaticInst*
8387  {
8388  return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
8389  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
8390 
8391  GPUStaticInst*
8393  {
8394  return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
8395  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
8396 
8397  GPUStaticInst*
8399  {
8400  return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
8401  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
8402 
8403  GPUStaticInst*
8405  {
8406  return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
8407  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
8408 
8409  GPUStaticInst*
8411  {
8412  return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
8413  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
8414 
8415  GPUStaticInst*
8417  {
8418  return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
8419  } // decode_OP_SMEM__S_LOAD_DWORD
8420 
8421  GPUStaticInst*
8423  {
8424  return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
8425  } // decode_OP_SMEM__S_LOAD_DWORDX2
8426 
8427  GPUStaticInst*
8429  {
8430  return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
8431  } // decode_OP_SMEM__S_LOAD_DWORDX4
8432 
8433  GPUStaticInst*
8435  {
8436  return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
8437  } // decode_OP_SMEM__S_LOAD_DWORDX8
8438 
8439  GPUStaticInst*
8441  {
8442  return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
8443  } // decode_OP_SMEM__S_LOAD_DWORDX16
8444 
8445  GPUStaticInst*
8447  {
8448  return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
8449  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
8450 
8451  GPUStaticInst*
8453  {
8454  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
8455  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
8456 
8457  GPUStaticInst*
8459  {
8460  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
8461  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
8462 
8463  GPUStaticInst*
8465  {
8466  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
8467  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
8468 
8469  GPUStaticInst*
8471  {
8472  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
8473  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
8474 
8475  GPUStaticInst*
8477  {
8478  return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
8479  } // decode_OP_SMEM__S_STORE_DWORD
8480 
8481  GPUStaticInst*
8483  {
8484  return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
8485  } // decode_OP_SMEM__S_STORE_DWORDX2
8486 
8487  GPUStaticInst*
8489  {
8490  return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
8491  } // decode_OP_SMEM__S_STORE_DWORDX4
8492 
8493  GPUStaticInst*
8495  {
8496  return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
8497  } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
8498 
8499  GPUStaticInst*
8501  {
8502  return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
8503  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
8504 
8505  GPUStaticInst*
8507  {
8508  return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
8509  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
8510 
8511  GPUStaticInst*
8513  {
8514  return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
8515  } // decode_OP_SMEM__S_DCACHE_INV
8516 
8517  GPUStaticInst*
8519  {
8520  return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
8521  } // decode_OP_SMEM__S_DCACHE_WB
8522 
8523  GPUStaticInst*
8525  {
8526  return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
8527  } // decode_OP_SMEM__S_DCACHE_INV_VOL
8528 
8529  GPUStaticInst*
8531  {
8532  return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
8533  } // decode_OP_SMEM__S_DCACHE_WB_VOL
8534 
8535  GPUStaticInst*
8537  {
8538  return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
8539  } // decode_OP_SMEM__S_MEMTIME
8540 
8541  GPUStaticInst*
8543  {
8544  return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
8545  } // decode_OP_SMEM__S_MEMREALTIME
8546 
8547  GPUStaticInst*
8549  {
8550  return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
8551  } // decode_OP_SMEM__S_ATC_PROBE
8552 
8553  GPUStaticInst*
8555  {
8556  return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
8557  } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
8558 
8559  GPUStaticInst*
8561  {
8562  return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
8563  } // decode_OP_SOP1__S_MOV_B32
8564 
8565  GPUStaticInst*
8567  {
8568  return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
8569  } // decode_OP_SOP1__S_MOV_B64
8570 
8571  GPUStaticInst*
8573  {
8574  return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
8575  } // decode_OP_SOP1__S_CMOV_B32
8576 
8577  GPUStaticInst*
8579  {
8580  return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
8581  } // decode_OP_SOP1__S_CMOV_B64
8582 
8583  GPUStaticInst*
8585  {
8586  return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
8587  } // decode_OP_SOP1__S_NOT_B32
8588 
8589  GPUStaticInst*
8591  {
8592  return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
8593  } // decode_OP_SOP1__S_NOT_B64
8594 
8595  GPUStaticInst*
8597  {
8598  return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
8599  } // decode_OP_SOP1__S_WQM_B32
8600 
8601  GPUStaticInst*
8603  {
8604  return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
8605  } // decode_OP_SOP1__S_WQM_B64
8606 
8607  GPUStaticInst*
8609  {
8610  return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
8611  } // decode_OP_SOP1__S_BREV_B32
8612 
8613  GPUStaticInst*
8615  {
8616  return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
8617  } // decode_OP_SOP1__S_BREV_B64
8618 
8619  GPUStaticInst*
8621  {
8622  return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
8623  } // decode_OP_SOP1__S_BCNT0_I32_B32
8624 
8625  GPUStaticInst*
8627  {
8628  return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
8629  } // decode_OP_SOP1__S_BCNT0_I32_B64
8630 
8631  GPUStaticInst*
8633  {
8634  return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
8635  } // decode_OP_SOP1__S_BCNT1_I32_B32
8636 
8637  GPUStaticInst*
8639  {
8640  return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
8641  } // decode_OP_SOP1__S_BCNT1_I32_B64
8642 
8643  GPUStaticInst*
8645  {
8646  return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
8647  } // decode_OP_SOP1__S_FF0_I32_B32
8648 
8649  GPUStaticInst*
8651  {
8652  return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
8653  } // decode_OP_SOP1__S_FF0_I32_B64
8654 
8655  GPUStaticInst*
8657  {
8658  return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
8659  } // decode_OP_SOP1__S_FF1_I32_B32
8660 
8661  GPUStaticInst*
8663  {
8664  return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
8665  } // decode_OP_SOP1__S_FF1_I32_B64
8666 
8667  GPUStaticInst*
8669  {
8670  return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
8671  } // decode_OP_SOP1__S_FLBIT_I32_B32
8672 
8673  GPUStaticInst*
8675  {
8676  return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
8677  } // decode_OP_SOP1__S_FLBIT_I32_B64
8678 
8679  GPUStaticInst*
8681  {
8682  return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
8683  } // decode_OP_SOP1__S_FLBIT_I32
8684 
8685  GPUStaticInst*
8687  {
8688  return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
8689  } // decode_OP_SOP1__S_FLBIT_I32_I64
8690 
8691  GPUStaticInst*
8693  {
8694  return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
8695  } // decode_OP_SOP1__S_SEXT_I32_I8
8696 
8697  GPUStaticInst*
8699  {
8700  return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
8701  } // decode_OP_SOP1__S_SEXT_I32_I16
8702 
8703  GPUStaticInst*
8705  {
8706  return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
8707  } // decode_OP_SOP1__S_BITSET0_B32
8708 
8709  GPUStaticInst*
8711  {
8712  return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
8713  } // decode_OP_SOP1__S_BITSET0_B64
8714 
8715  GPUStaticInst*
8717  {
8718  return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
8719  } // decode_OP_SOP1__S_BITSET1_B32
8720 
8721  GPUStaticInst*
8723  {
8724  return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
8725  } // decode_OP_SOP1__S_BITSET1_B64
8726 
8727  GPUStaticInst*
8729  {
8730  return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
8731  } // decode_OP_SOP1__S_GETPC_B64
8732 
8733  GPUStaticInst*
8735  {
8736  return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
8737  } // decode_OP_SOP1__S_SETPC_B64
8738 
8739  GPUStaticInst*
8741  {
8742  return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
8743  } // decode_OP_SOP1__S_SWAPPC_B64
8744 
8745  GPUStaticInst*
8747  {
8748  return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
8749  } // decode_OP_SOP1__S_RFE_B64
8750 
8751  GPUStaticInst*
8753  {
8754  return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8755  } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
8756 
8757  GPUStaticInst*
8759  {
8760  return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8761  } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
8762 
8763  GPUStaticInst*
8765  {
8766  return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8767  } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
8768 
8769  GPUStaticInst*
8771  {
8772  return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8773  } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
8774 
8775  GPUStaticInst*
8777  {
8778  return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8779  } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
8780 
8781  GPUStaticInst*
8783  {
8784  return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8785  } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
8786 
8787  GPUStaticInst*
8789  {
8790  return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8791  } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
8792 
8793  GPUStaticInst*
8795  {
8796  return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
8797  } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
8798 
8799  GPUStaticInst*
8801  {
8802  return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
8803  } // decode_OP_SOP1__S_QUADMASK_B32
8804 
8805  GPUStaticInst*
8807  {
8808  return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
8809  } // decode_OP_SOP1__S_QUADMASK_B64
8810 
8811  GPUStaticInst*
8813  {
8814  return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
8815  } // decode_OP_SOP1__S_MOVRELS_B32
8816 
8817  GPUStaticInst*
8819  {
8820  return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
8821  } // decode_OP_SOP1__S_MOVRELS_B64
8822 
8823  GPUStaticInst*
8825  {
8826  return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
8827  } // decode_OP_SOP1__S_MOVRELD_B32
8828 
8829  GPUStaticInst*
8831  {
8832  return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
8833  } // decode_OP_SOP1__S_MOVRELD_B64
8834 
8835  GPUStaticInst*
8837  {
8838  return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
8839  } // decode_OP_SOP1__S_CBRANCH_JOIN
8840 
8841  GPUStaticInst*
8843  {
8844  return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
8845  } // decode_OP_SOP1__S_ABS_I32
8846 
8847  GPUStaticInst*
8849  {
8850  return new Inst_SOP1__S_MOV_FED_B32(&iFmt->iFmt_SOP1);
8851  } // decode_OP_SOP1__S_MOV_FED_B32
8852 
8853  GPUStaticInst*
8855  {
8856  return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
8857  } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
8858 
8859  GPUStaticInst*
8861  {
8862  return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
8863  } // decode_OP_SOPC__S_CMP_EQ_I32
8864 
8865  GPUStaticInst*
8867  {
8868  return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
8869  } // decode_OP_SOPC__S_CMP_LG_I32
8870 
8871  GPUStaticInst*
8873  {
8874  return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
8875  } // decode_OP_SOPC__S_CMP_GT_I32
8876 
8877  GPUStaticInst*
8879  {
8880  return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
8881  } // decode_OP_SOPC__S_CMP_GE_I32
8882 
8883  GPUStaticInst*
8885  {
8886  return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
8887  } // decode_OP_SOPC__S_CMP_LT_I32
8888 
8889  GPUStaticInst*
8891  {
8892  return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
8893  } // decode_OP_SOPC__S_CMP_LE_I32
8894 
8895  GPUStaticInst*
8897  {
8898  return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
8899  } // decode_OP_SOPC__S_CMP_EQ_U32
8900 
8901  GPUStaticInst*
8903  {
8904  return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
8905  } // decode_OP_SOPC__S_CMP_LG_U32
8906 
8907  GPUStaticInst*
8909  {
8910  return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
8911  } // decode_OP_SOPC__S_CMP_GT_U32
8912 
8913  GPUStaticInst*
8915  {
8916  return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
8917  } // decode_OP_SOPC__S_CMP_GE_U32
8918 
8919  GPUStaticInst*
8921  {
8922  return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
8923  } // decode_OP_SOPC__S_CMP_LT_U32
8924 
8925  GPUStaticInst*
8927  {
8928  return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
8929  } // decode_OP_SOPC__S_CMP_LE_U32
8930 
8931  GPUStaticInst*
8933  {
8934  return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
8935  } // decode_OP_SOPC__S_BITCMP0_B32
8936 
8937  GPUStaticInst*
8939  {
8940  return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
8941  } // decode_OP_SOPC__S_BITCMP1_B32
8942 
8943  GPUStaticInst*
8945  {
8946  return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
8947  } // decode_OP_SOPC__S_BITCMP0_B64
8948 
8949  GPUStaticInst*
8951  {
8952  return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
8953  } // decode_OP_SOPC__S_BITCMP1_B64
8954 
8955  GPUStaticInst*
8957  {
8958  return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
8959  } // decode_OP_SOPC__S_SETVSKIP
8960 
8961  GPUStaticInst*
8963  {
8964  return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
8965  } // decode_OP_SOPC__S_SET_GPR_IDX_ON
8966 
8967  GPUStaticInst*
8969  {
8970  return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
8971  } // decode_OP_SOPC__S_CMP_EQ_U64
8972 
8973  GPUStaticInst*
8975  {
8976  return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
8977  } // decode_OP_SOPC__S_CMP_LG_U64
8978 
8979  GPUStaticInst*
8981  {
8982  return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
8983  } // decode_OP_SOPP__S_NOP
8984 
8985  GPUStaticInst*
8987  {
8988  return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
8989  } // decode_OP_SOPP__S_ENDPGM
8990 
8991  GPUStaticInst*
8993  {
8994  return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
8995  } // decode_OP_SOPP__S_BRANCH
8996 
8997  GPUStaticInst*
8999  {
9000  return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
9001  } // decode_OP_SOPP__S_WAKEUP
9002 
9003  GPUStaticInst*
9005  {
9006  return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
9007  } // decode_OP_SOPP__S_CBRANCH_SCC0
9008 
9009  GPUStaticInst*
9011  {
9012  return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
9013  } // decode_OP_SOPP__S_CBRANCH_SCC1
9014 
9015  GPUStaticInst*
9017  {
9018  return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
9019  } // decode_OP_SOPP__S_CBRANCH_VCCZ
9020 
9021  GPUStaticInst*
9023  {
9024  return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
9025  } // decode_OP_SOPP__S_CBRANCH_VCCNZ
9026 
9027  GPUStaticInst*
9029  {
9030  return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
9031  } // decode_OP_SOPP__S_CBRANCH_EXECZ
9032 
9033  GPUStaticInst*
9035  {
9036  return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
9037  } // decode_OP_SOPP__S_CBRANCH_EXECNZ
9038 
9039  GPUStaticInst*
9041  {
9042  return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
9043  } // decode_OP_SOPP__S_BARRIER
9044 
9045  GPUStaticInst*
9047  {
9048  return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
9049  } // decode_OP_SOPP__S_SETKILL
9050 
9051  GPUStaticInst*
9053  {
9054  return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
9055  } // decode_OP_SOPP__S_WAITCNT
9056 
9057  GPUStaticInst*
9059  {
9060  return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
9061  } // decode_OP_SOPP__S_SETHALT
9062 
9063  GPUStaticInst*
9065  {
9066  return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
9067  } // decode_OP_SOPP__S_SLEEP
9068 
9069  GPUStaticInst*
9071  {
9072  return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
9073  } // decode_OP_SOPP__S_SETPRIO
9074 
9075  GPUStaticInst*
9077  {
9078  return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
9079  } // decode_OP_SOPP__S_SENDMSG
9080 
9081  GPUStaticInst*
9083  {
9084  return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
9085  } // decode_OP_SOPP__S_SENDMSGHALT
9086 
9087  GPUStaticInst*
9089  {
9090  return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
9091  } // decode_OP_SOPP__S_TRAP
9092 
9093  GPUStaticInst*
9095  {
9096  return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
9097  } // decode_OP_SOPP__S_ICACHE_INV
9098 
9099  GPUStaticInst*
9101  {
9102  return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
9103  } // decode_OP_SOPP__S_INCPERFLEVEL
9104 
9105  GPUStaticInst*
9107  {
9108  return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
9109  } // decode_OP_SOPP__S_DECPERFLEVEL
9110 
9111  GPUStaticInst*
9113  {
9114  return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
9115  } // decode_OP_SOPP__S_TTRACEDATA
9116 
9117  GPUStaticInst*
9119  {
9120  return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
9121  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
9122 
9123  GPUStaticInst*
9125  {
9126  return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
9127  } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
9128 
9129  GPUStaticInst*
9131  {
9133  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
9134 
9135  GPUStaticInst*
9137  {
9139  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
9140 
9141  GPUStaticInst*
9143  {
9144  return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
9145  } // decode_OP_SOPP__S_ENDPGM_SAVED
9146 
9147  GPUStaticInst*
9149  {
9150  return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
9151  } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
9152 
9153  GPUStaticInst*
9155  {
9156  return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
9157  } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
9158 
9159  GPUStaticInst*
9161  {
9162  return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
9163  } // decode_OP_VINTRP__V_INTERP_P1_F32
9164 
9165  GPUStaticInst*
9167  {
9168  return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
9169  } // decode_OP_VINTRP__V_INTERP_P2_F32
9170 
9171  GPUStaticInst*
9173  {
9174  return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
9175  } // decode_OP_VINTRP__V_INTERP_MOV_F32
9176 
9177  GPUStaticInst*
9179  {
9180  return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
9181  } // decode_OP_VOP1__V_NOP
9182 
9183  GPUStaticInst*
9185  {
9186  return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
9187  } // decode_OP_VOP1__V_MOV_B32
9188 
9189  GPUStaticInst*
9191  {
9192  return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
9193  } // decode_OP_VOP1__V_READFIRSTLANE_B32
9194 
9195  GPUStaticInst*
9197  {
9198  return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
9199  } // decode_OP_VOP1__V_CVT_I32_F64
9200 
9201  GPUStaticInst*
9203  {
9204  return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
9205  } // decode_OP_VOP1__V_CVT_F64_I32
9206 
9207  GPUStaticInst*
9209  {
9210  return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
9211  } // decode_OP_VOP1__V_CVT_F32_I32
9212 
9213  GPUStaticInst*
9215  {
9216  return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
9217  } // decode_OP_VOP1__V_CVT_F32_U32
9218 
9219  GPUStaticInst*
9221  {
9222  return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
9223  } // decode_OP_VOP1__V_CVT_U32_F32
9224 
9225  GPUStaticInst*
9227  {
9228  return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
9229  } // decode_OP_VOP1__V_CVT_I32_F32
9230 
9231  GPUStaticInst*
9233  {
9234  return new Inst_VOP1__V_MOV_FED_B32(&iFmt->iFmt_VOP1);
9235  } // decode_OP_VOP1__V_MOV_FED_B32
9236 
9237  GPUStaticInst*
9239  {
9240  return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
9241  } // decode_OP_VOP1__V_CVT_F16_F32
9242 
9243  GPUStaticInst*
9245  {
9246  return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
9247  } // decode_OP_VOP1__V_CVT_F32_F16
9248 
9249  GPUStaticInst*
9251  {
9252  return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
9253  } // decode_OP_VOP1__V_CVT_RPI_I32_F32
9254 
9255  GPUStaticInst*
9257  {
9258  return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
9259  } // decode_OP_VOP1__V_CVT_FLR_I32_F32
9260 
9261  GPUStaticInst*
9263  {
9264  return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
9265  } // decode_OP_VOP1__V_CVT_OFF_F32_I4
9266 
9267  GPUStaticInst*
9269  {
9270  return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
9271  } // decode_OP_VOP1__V_CVT_F32_F64
9272 
9273  GPUStaticInst*
9275  {
9276  return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
9277  } // decode_OP_VOP1__V_CVT_F64_F32
9278 
9279  GPUStaticInst*
9281  {
9282  return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
9283  } // decode_OP_VOP1__V_CVT_F32_UBYTE0
9284 
9285  GPUStaticInst*
9287  {
9288  return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
9289  } // decode_OP_VOP1__V_CVT_F32_UBYTE1
9290 
9291  GPUStaticInst*
9293  {
9294  return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
9295  } // decode_OP_VOP1__V_CVT_F32_UBYTE2
9296 
9297  GPUStaticInst*
9299  {
9300  return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
9301  } // decode_OP_VOP1__V_CVT_F32_UBYTE3
9302 
9303  GPUStaticInst*
9305  {
9306  return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
9307  } // decode_OP_VOP1__V_CVT_U32_F64
9308 
9309  GPUStaticInst*
9311  {
9312  return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
9313  } // decode_OP_VOP1__V_CVT_F64_U32
9314 
9315  GPUStaticInst*
9317  {
9318  return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
9319  } // decode_OP_VOP1__V_TRUNC_F64
9320 
9321  GPUStaticInst*
9323  {
9324  return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
9325  } // decode_OP_VOP1__V_CEIL_F64
9326 
9327  GPUStaticInst*
9329  {
9330  return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
9331  } // decode_OP_VOP1__V_RNDNE_F64
9332 
9333  GPUStaticInst*
9335  {
9336  return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
9337  } // decode_OP_VOP1__V_FLOOR_F64
9338 
9339  GPUStaticInst*
9341  {
9342  return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
9343  } // decode_OP_VOP1__V_FRACT_F32
9344 
9345  GPUStaticInst*
9347  {
9348  return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
9349  } // decode_OP_VOP1__V_TRUNC_F32
9350 
9351  GPUStaticInst*
9353  {
9354  return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
9355  } // decode_OP_VOP1__V_CEIL_F32
9356 
9357  GPUStaticInst*
9359  {
9360  return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
9361  } // decode_OP_VOP1__V_RNDNE_F32
9362 
9363  GPUStaticInst*
9365  {
9366  return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
9367  } // decode_OP_VOP1__V_FLOOR_F32
9368 
9369  GPUStaticInst*
9371  {
9372  return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
9373  } // decode_OP_VOP1__V_EXP_F32
9374 
9375  GPUStaticInst*
9377  {
9378  return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
9379  } // decode_OP_VOP1__V_LOG_F32
9380 
9381  GPUStaticInst*
9383  {
9384  return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
9385  } // decode_OP_VOP1__V_RCP_F32
9386 
9387  GPUStaticInst*
9389  {
9390  return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
9391  } // decode_OP_VOP1__V_RCP_IFLAG_F32
9392 
9393  GPUStaticInst*
9395  {
9396  return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
9397  } // decode_OP_VOP1__V_RSQ_F32
9398 
9399  GPUStaticInst*
9401  {
9402  return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
9403  } // decode_OP_VOP1__V_RCP_F64
9404 
9405  GPUStaticInst*
9407  {
9408  return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
9409  } // decode_OP_VOP1__V_RSQ_F64
9410 
9411  GPUStaticInst*
9413  {
9414  return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
9415  } // decode_OP_VOP1__V_SQRT_F32
9416 
9417  GPUStaticInst*
9419  {
9420  return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
9421  } // decode_OP_VOP1__V_SQRT_F64
9422 
9423  GPUStaticInst*
9425  {
9426  return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
9427  } // decode_OP_VOP1__V_SIN_F32
9428 
9429  GPUStaticInst*
9431  {
9432  return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
9433  } // decode_OP_VOP1__V_COS_F32
9434 
9435  GPUStaticInst*
9437  {
9438  return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
9439  } // decode_OP_VOP1__V_NOT_B32
9440 
9441  GPUStaticInst*
9443  {
9444  return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
9445  } // decode_OP_VOP1__V_BFREV_B32
9446 
9447  GPUStaticInst*
9449  {
9450  return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
9451  } // decode_OP_VOP1__V_FFBH_U32
9452 
9453  GPUStaticInst*
9455  {
9456  return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
9457  } // decode_OP_VOP1__V_FFBL_B32
9458 
9459  GPUStaticInst*
9461  {
9462  return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
9463  } // decode_OP_VOP1__V_FFBH_I32
9464 
9465  GPUStaticInst*
9467  {
9468  return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
9469  } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
9470 
9471  GPUStaticInst*
9473  {
9474  return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
9475  } // decode_OP_VOP1__V_FREXP_MANT_F64
9476 
9477  GPUStaticInst*
9479  {
9480  return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
9481  } // decode_OP_VOP1__V_FRACT_F64
9482 
9483  GPUStaticInst*
9485  {
9486  return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
9487  } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
9488 
9489  GPUStaticInst*
9491  {
9492  return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
9493  } // decode_OP_VOP1__V_FREXP_MANT_F32
9494 
9495  GPUStaticInst*
9497  {
9498  return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
9499  } // decode_OP_VOP1__V_CLREXCP
9500 
9501  GPUStaticInst*
9503  {
9504  return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
9505  } // decode_OP_VOP1__V_CVT_F16_U16
9506 
9507  GPUStaticInst*
9509  {
9510  return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
9511  } // decode_OP_VOP1__V_CVT_F16_I16
9512 
9513  GPUStaticInst*
9515  {
9516  return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
9517  } // decode_OP_VOP1__V_CVT_U16_F16
9518 
9519  GPUStaticInst*
9521  {
9522  return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
9523  } // decode_OP_VOP1__V_CVT_I16_F16
9524 
9525  GPUStaticInst*
9527  {
9528  return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
9529  } // decode_OP_VOP1__V_RCP_F16
9530 
9531  GPUStaticInst*
9533  {
9534  return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
9535  } // decode_OP_VOP1__V_SQRT_F16
9536 
9537  GPUStaticInst*
9539  {
9540  return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
9541  } // decode_OP_VOP1__V_RSQ_F16
9542 
9543  GPUStaticInst*
9545  {
9546  return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
9547  } // decode_OP_VOP1__V_LOG_F16
9548 
9549  GPUStaticInst*
9551  {
9552  return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
9553  } // decode_OP_VOP1__V_EXP_F16
9554 
9555  GPUStaticInst*
9557  {
9558  return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
9559  } // decode_OP_VOP1__V_FREXP_MANT_F16
9560 
9561  GPUStaticInst*
9563  {
9564  return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
9565  } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
9566 
9567  GPUStaticInst*
9569  {
9570  return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
9571  } // decode_OP_VOP1__V_FLOOR_F16
9572 
9573  GPUStaticInst*
9575  {
9576  return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
9577  } // decode_OP_VOP1__V_CEIL_F16
9578 
9579  GPUStaticInst*
9581  {
9582  return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
9583  } // decode_OP_VOP1__V_TRUNC_F16
9584 
9585  GPUStaticInst*
9587  {
9588  return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
9589  } // decode_OP_VOP1__V_RNDNE_F16
9590 
9591  GPUStaticInst*
9593  {
9594  return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
9595  } // decode_OP_VOP1__V_FRACT_F16
9596 
9597  GPUStaticInst*
9599  {
9600  return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
9601  } // decode_OP_VOP1__V_SIN_F16
9602 
9603  GPUStaticInst*
9605  {
9606  return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
9607  } // decode_OP_VOP1__V_COS_F16
9608 
9609  GPUStaticInst*
9611  {
9612  return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
9613  } // decode_OP_VOP1__V_EXP_LEGACY_F32
9614 
9615  GPUStaticInst*
9617  {
9618  return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
9619  } // decode_OP_VOP1__V_LOG_LEGACY_F32
9620 
9621  GPUStaticInst*
9623  {
9624  return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
9625  } // decode_OP_VOPC__V_CMP_CLASS_F32
9626 
9627  GPUStaticInst*
9629  {
9630  return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
9631  } // decode_OP_VOPC__V_CMPX_CLASS_F32
9632 
9633  GPUStaticInst*
9635  {
9636  return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
9637  } // decode_OP_VOPC__V_CMP_CLASS_F64
9638 
9639  GPUStaticInst*
9641  {
9642  return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
9643  } // decode_OP_VOPC__V_CMPX_CLASS_F64
9644 
9645  GPUStaticInst*
9647  {
9648  return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
9649  } // decode_OP_VOPC__V_CMP_CLASS_F16
9650 
9651  GPUStaticInst*
9653  {
9654  return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
9655  } // decode_OP_VOPC__V_CMPX_CLASS_F16
9656 
9657  GPUStaticInst*
9659  {
9660  return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
9661  } // decode_OP_VOPC__V_CMP_F_F16
9662 
9663  GPUStaticInst*
9665  {
9666  return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
9667  } // decode_OP_VOPC__V_CMP_LT_F16
9668 
9669  GPUStaticInst*
9671  {
9672  return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
9673  } // decode_OP_VOPC__V_CMP_EQ_F16
9674 
9675  GPUStaticInst*
9677  {
9678  return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
9679  } // decode_OP_VOPC__V_CMP_LE_F16
9680 
9681  GPUStaticInst*
9683  {
9684  return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
9685  } // decode_OP_VOPC__V_CMP_GT_F16
9686 
9687  GPUStaticInst*
9689  {
9690  return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
9691  } // decode_OP_VOPC__V_CMP_LG_F16
9692 
9693  GPUStaticInst*
9695  {
9696  return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
9697  } // decode_OP_VOPC__V_CMP_GE_F16
9698 
9699  GPUStaticInst*
9701  {
9702  return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
9703  } // decode_OP_VOPC__V_CMP_O_F16
9704 
9705  GPUStaticInst*
9707  {
9708  return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
9709  } // decode_OP_VOPC__V_CMP_U_F16
9710 
9711  GPUStaticInst*
9713  {
9714  return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
9715  } // decode_OP_VOPC__V_CMP_NGE_F16
9716 
9717  GPUStaticInst*
9719  {
9720  return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
9721  } // decode_OP_VOPC__V_CMP_NLG_F16
9722 
9723  GPUStaticInst*
9725  {
9726  return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
9727  } // decode_OP_VOPC__V_CMP_NGT_F16
9728 
9729  GPUStaticInst*
9731  {
9732  return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
9733  } // decode_OP_VOPC__V_CMP_NLE_F16
9734 
9735  GPUStaticInst*
9737  {
9738  return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
9739  } // decode_OP_VOPC__V_CMP_NEQ_F16
9740 
9741  GPUStaticInst*
9743  {
9744  return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
9745  } // decode_OP_VOPC__V_CMP_NLT_F16
9746 
9747  GPUStaticInst*
9749  {
9750  return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
9751  } // decode_OP_VOPC__V_CMP_TRU_F16
9752 
9753  GPUStaticInst*
9755  {
9756  return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
9757  } // decode_OP_VOPC__V_CMPX_F_F16
9758 
9759  GPUStaticInst*
9761  {
9762  return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
9763  } // decode_OP_VOPC__V_CMPX_LT_F16
9764 
9765  GPUStaticInst*
9767  {
9768  return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
9769  } // decode_OP_VOPC__V_CMPX_EQ_F16
9770 
9771  GPUStaticInst*
9773  {
9774  return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
9775  } // decode_OP_VOPC__V_CMPX_LE_F16
9776 
9777  GPUStaticInst*
9779  {
9780  return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
9781  } // decode_OP_VOPC__V_CMPX_GT_F16
9782 
9783  GPUStaticInst*
9785  {
9786  return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
9787  } // decode_OP_VOPC__V_CMPX_LG_F16
9788 
9789  GPUStaticInst*
9791  {
9792  return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
9793  } // decode_OP_VOPC__V_CMPX_GE_F16
9794 
9795  GPUStaticInst*
9797  {
9798  return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
9799  } // decode_OP_VOPC__V_CMPX_O_F16
9800 
9801  GPUStaticInst*
9803  {
9804  return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
9805  } // decode_OP_VOPC__V_CMPX_U_F16
9806 
9807  GPUStaticInst*
9809  {
9810  return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
9811  } // decode_OP_VOPC__V_CMPX_NGE_F16
9812 
9813  GPUStaticInst*
9815  {
9816  return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
9817  } // decode_OP_VOPC__V_CMPX_NLG_F16
9818 
9819  GPUStaticInst*
9821  {
9822  return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
9823  } // decode_OP_VOPC__V_CMPX_NGT_F16
9824 
9825  GPUStaticInst*
9827  {
9828  return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
9829  } // decode_OP_VOPC__V_CMPX_NLE_F16
9830 
9831  GPUStaticInst*
9833  {
9834  return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
9835  } // decode_OP_VOPC__V_CMPX_NEQ_F16
9836 
9837  GPUStaticInst*
9839  {
9840  return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
9841  } // decode_OP_VOPC__V_CMPX_NLT_F16
9842 
9843  GPUStaticInst*
9845  {
9846  return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
9847  } // decode_OP_VOPC__V_CMPX_TRU_F16
9848 
9849  GPUStaticInst*
9851  {
9852  return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
9853  } // decode_OP_VOPC__V_CMP_F_F32
9854 
9855  GPUStaticInst*
9857  {
9858  return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
9859  } // decode_OP_VOPC__V_CMP_LT_F32
9860 
9861  GPUStaticInst*
9863  {
9864  return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
9865  } // decode_OP_VOPC__V_CMP_EQ_F32
9866 
9867  GPUStaticInst*
9869  {
9870  return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
9871  } // decode_OP_VOPC__V_CMP_LE_F32
9872 
9873  GPUStaticInst*
9875  {
9876  return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
9877  } // decode_OP_VOPC__V_CMP_GT_F32
9878 
9879  GPUStaticInst*
9881  {
9882  return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
9883  } // decode_OP_VOPC__V_CMP_LG_F32
9884 
9885  GPUStaticInst*
9887  {
9888  return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
9889  } // decode_OP_VOPC__V_CMP_GE_F32
9890 
9891  GPUStaticInst*
9893  {
9894  return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
9895  } // decode_OP_VOPC__V_CMP_O_F32
9896 
9897  GPUStaticInst*
9899  {
9900  return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
9901  } // decode_OP_VOPC__V_CMP_U_F32
9902 
9903  GPUStaticInst*
9905  {
9906  return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
9907  } // decode_OP_VOPC__V_CMP_NGE_F32
9908 
9909  GPUStaticInst*
9911  {
9912  return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
9913  } // decode_OP_VOPC__V_CMP_NLG_F32
9914 
9915  GPUStaticInst*
9917  {
9918  return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
9919  } // decode_OP_VOPC__V_CMP_NGT_F32
9920 
9921  GPUStaticInst*
9923  {
9924  return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
9925  } // decode_OP_VOPC__V_CMP_NLE_F32
9926 
9927  GPUStaticInst*
9929  {
9930  return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
9931  } // decode_OP_VOPC__V_CMP_NEQ_F32
9932 
9933  GPUStaticInst*
9935  {
9936  return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
9937  } // decode_OP_VOPC__V_CMP_NLT_F32
9938 
9939  GPUStaticInst*
9941  {
9942  return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
9943  } // decode_OP_VOPC__V_CMP_TRU_F32
9944 
9945  GPUStaticInst*
9947  {
9948  return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
9949  } // decode_OP_VOPC__V_CMPX_F_F32
9950 
9951  GPUStaticInst*
9953  {
9954  return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
9955  } // decode_OP_VOPC__V_CMPX_LT_F32
9956 
9957  GPUStaticInst*
9959  {
9960  return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
9961  } // decode_OP_VOPC__V_CMPX_EQ_F32
9962 
9963  GPUStaticInst*
9965  {
9966  return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
9967  } // decode_OP_VOPC__V_CMPX_LE_F32
9968 
9969  GPUStaticInst*
9971  {
9972  return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
9973  } // decode_OP_VOPC__V_CMPX_GT_F32
9974 
9975  GPUStaticInst*
9977  {
9978  return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
9979  } // decode_OP_VOPC__V_CMPX_LG_F32
9980 
9981  GPUStaticInst*
9983  {
9984  return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
9985  } // decode_OP_VOPC__V_CMPX_GE_F32
9986 
9987  GPUStaticInst*
9989  {
9990  return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
9991  } // decode_OP_VOPC__V_CMPX_O_F32
9992 
9993  GPUStaticInst*
9995  {
9996  return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
9997  } // decode_OP_VOPC__V_CMPX_U_F32
9998 
9999  GPUStaticInst*
10001  {
10002  return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
10003  } // decode_OP_VOPC__V_CMPX_NGE_F32
10004 
10005  GPUStaticInst*
10007  {
10008  return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
10009  } // decode_OP_VOPC__V_CMPX_NLG_F32
10010 
10011  GPUStaticInst*
10013  {
10014  return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
10015  } // decode_OP_VOPC__V_CMPX_NGT_F32
10016 
10017  GPUStaticInst*
10019  {
10020  return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
10021  } // decode_OP_VOPC__V_CMPX_NLE_F32
10022 
10023  GPUStaticInst*
10025  {
10026  return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
10027  } // decode_OP_VOPC__V_CMPX_NEQ_F32
10028 
10029  GPUStaticInst*
10031  {
10032  return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
10033  } // decode_OP_VOPC__V_CMPX_NLT_F32
10034 
10035  GPUStaticInst*
10037  {
10038  return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
10039  } // decode_OP_VOPC__V_CMPX_TRU_F32
10040 
10041  GPUStaticInst*
10043  {
10044  return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
10045  } // decode_OP_VOPC__V_CMP_F_F64
10046 
10047  GPUStaticInst*
10049  {
10050  return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
10051  } // decode_OP_VOPC__V_CMP_LT_F64
10052 
10053  GPUStaticInst*
10055  {
10056  return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
10057  } // decode_OP_VOPC__V_CMP_EQ_F64
10058 
10059  GPUStaticInst*
10061  {
10062  return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
10063  } // decode_OP_VOPC__V_CMP_LE_F64
10064 
10065  GPUStaticInst*
10067  {
10068  return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
10069  } // decode_OP_VOPC__V_CMP_GT_F64
10070 
10071  GPUStaticInst*
10073  {
10074  return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
10075  } // decode_OP_VOPC__V_CMP_LG_F64
10076 
10077  GPUStaticInst*
10079  {
10080  return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
10081  } // decode_OP_VOPC__V_CMP_GE_F64
10082 
10083  GPUStaticInst*
10085  {
10086  return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
10087  } // decode_OP_VOPC__V_CMP_O_F64
10088 
10089  GPUStaticInst*
10091  {
10092  return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
10093  } // decode_OP_VOPC__V_CMP_U_F64
10094 
10095  GPUStaticInst*
10097  {
10098  return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
10099  } // decode_OP_VOPC__V_CMP_NGE_F64
10100 
10101  GPUStaticInst*
10103  {
10104  return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
10105  } // decode_OP_VOPC__V_CMP_NLG_F64
10106 
10107  GPUStaticInst*
10109  {
10110  return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
10111  } // decode_OP_VOPC__V_CMP_NGT_F64
10112 
10113  GPUStaticInst*
10115  {
10116  return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
10117  } // decode_OP_VOPC__V_CMP_NLE_F64
10118 
10119  GPUStaticInst*
10121  {
10122  return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
10123  } // decode_OP_VOPC__V_CMP_NEQ_F64
10124 
10125  GPUStaticInst*
10127  {
10128  return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
10129  } // decode_OP_VOPC__V_CMP_NLT_F64
10130 
10131  GPUStaticInst*
10133  {
10134  return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
10135  } // decode_OP_VOPC__V_CMP_TRU_F64
10136 
10137  GPUStaticInst*
10139  {
10140  return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
10141  } // decode_OP_VOPC__V_CMPX_F_F64
10142 
10143  GPUStaticInst*
10145  {
10146  return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
10147  } // decode_OP_VOPC__V_CMPX_LT_F64
10148 
10149  GPUStaticInst*
10151  {
10152  return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
10153  } // decode_OP_VOPC__V_CMPX_EQ_F64
10154 
10155  GPUStaticInst*
10157  {
10158  return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
10159  } // decode_OP_VOPC__V_CMPX_LE_F64
10160 
10161  GPUStaticInst*
10163  {
10164  return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
10165  } // decode_OP_VOPC__V_CMPX_GT_F64
10166 
10167  GPUStaticInst*
10169  {
10170  return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
10171  } // decode_OP_VOPC__V_CMPX_LG_F64
10172 
10173  GPUStaticInst*
10175  {
10176  return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
10177  } // decode_OP_VOPC__V_CMPX_GE_F64
10178 
10179  GPUStaticInst*
10181  {
10182  return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
10183  } // decode_OP_VOPC__V_CMPX_O_F64
10184 
10185  GPUStaticInst*
10187  {
10188  return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
10189  } // decode_OP_VOPC__V_CMPX_U_F64
10190 
10191  GPUStaticInst*
10193  {
10194  return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
10195  } // decode_OP_VOPC__V_CMPX_NGE_F64
10196 
10197  GPUStaticInst*
10199  {
10200  return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
10201  } // decode_OP_VOPC__V_CMPX_NLG_F64
10202 
10203  GPUStaticInst*
10205  {
10206  return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
10207  } // decode_OP_VOPC__V_CMPX_NGT_F64
10208 
10209  GPUStaticInst*
10211  {
10212  return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
10213  } // decode_OP_VOPC__V_CMPX_NLE_F64
10214 
10215  GPUStaticInst*
10217  {
10218  return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
10219  } // decode_OP_VOPC__V_CMPX_NEQ_F64
10220 
10221  GPUStaticInst*
10223  {
10224  return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
10225  } // decode_OP_VOPC__V_CMPX_NLT_F64
10226 
10227  GPUStaticInst*
10229  {
10230  return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
10231  } // decode_OP_VOPC__V_CMPX_TRU_F64
10232 
10233  GPUStaticInst*
10235  {
10236  return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
10237  } // decode_OP_VOPC__V_CMP_F_I16
10238 
10239  GPUStaticInst*
10241  {
10242  return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
10243  } // decode_OP_VOPC__V_CMP_LT_I16
10244 
10245  GPUStaticInst*
10247  {
10248  return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
10249  } // decode_OP_VOPC__V_CMP_EQ_I16
10250 
10251  GPUStaticInst*
10253  {
10254  return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
10255  } // decode_OP_VOPC__V_CMP_LE_I16
10256 
10257  GPUStaticInst*
10259  {
10260  return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
10261  } // decode_OP_VOPC__V_CMP_GT_I16
10262 
10263  GPUStaticInst*
10265  {
10266  return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
10267  } // decode_OP_VOPC__V_CMP_NE_I16
10268 
10269  GPUStaticInst*
10271  {
10272  return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
10273  } // decode_OP_VOPC__V_CMP_GE_I16
10274 
10275  GPUStaticInst*
10277  {
10278  return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
10279  } // decode_OP_VOPC__V_CMP_T_I16
10280 
10281  GPUStaticInst*
10283  {
10284  return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
10285  } // decode_OP_VOPC__V_CMP_F_U16
10286 
10287  GPUStaticInst*
10289  {
10290  return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
10291  } // decode_OP_VOPC__V_CMP_LT_U16
10292 
10293  GPUStaticInst*
10295  {
10296  return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
10297  } // decode_OP_VOPC__V_CMP_EQ_U16
10298 
10299  GPUStaticInst*
10301  {
10302  return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
10303  } // decode_OP_VOPC__V_CMP_LE_U16
10304 
10305  GPUStaticInst*
10307  {
10308  return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
10309  } // decode_OP_VOPC__V_CMP_GT_U16
10310 
10311  GPUStaticInst*
10313  {
10314  return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
10315  } // decode_OP_VOPC__V_CMP_NE_U16
10316 
10317  GPUStaticInst*
10319  {
10320  return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
10321  } // decode_OP_VOPC__V_CMP_GE_U16
10322 
10323  GPUStaticInst*
10325  {
10326  return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
10327  } // decode_OP_VOPC__V_CMP_T_U16
10328 
10329  GPUStaticInst*
10331  {
10332  return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
10333  } // decode_OP_VOPC__V_CMPX_F_I16
10334 
10335  GPUStaticInst*
10337  {
10338  return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
10339  } // decode_OP_VOPC__V_CMPX_LT_I16
10340 
10341  GPUStaticInst*
10343  {
10344  return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
10345  } // decode_OP_VOPC__V_CMPX_EQ_I16
10346 
10347  GPUStaticInst*
10349  {
10350  return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
10351  } // decode_OP_VOPC__V_CMPX_LE_I16
10352 
10353  GPUStaticInst*
10355  {
10356  return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
10357  } // decode_OP_VOPC__V_CMPX_GT_I16
10358 
10359  GPUStaticInst*
10361  {
10362  return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
10363  } // decode_OP_VOPC__V_CMPX_NE_I16
10364 
10365  GPUStaticInst*
10367  {
10368  return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
10369  } // decode_OP_VOPC__V_CMPX_GE_I16
10370 
10371  GPUStaticInst*
10373  {
10374  return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
10375  } // decode_OP_VOPC__V_CMPX_T_I16
10376 
10377  GPUStaticInst*
10379  {
10380  return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
10381  } // decode_OP_VOPC__V_CMPX_F_U16
10382 
10383  GPUStaticInst*
10385  {
10386  return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
10387  } // decode_OP_VOPC__V_CMPX_LT_U16
10388 
10389  GPUStaticInst*
10391  {
10392  return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
10393  } // decode_OP_VOPC__V_CMPX_EQ_U16
10394 
10395  GPUStaticInst*
10397  {
10398  return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
10399  } // decode_OP_VOPC__V_CMPX_LE_U16
10400 
10401  GPUStaticInst*
10403  {
10404  return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
10405  } // decode_OP_VOPC__V_CMPX_GT_U16
10406 
10407  GPUStaticInst*
10409  {
10410  return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
10411  } // decode_OP_VOPC__V_CMPX_NE_U16
10412 
10413  GPUStaticInst*
10415  {
10416  return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
10417  } // decode_OP_VOPC__V_CMPX_GE_U16
10418 
10419  GPUStaticInst*
10421  {
10422  return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
10423  } // decode_OP_VOPC__V_CMPX_T_U16
10424 
10425  GPUStaticInst*
10427  {
10428  return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
10429  } // decode_OP_VOPC__V_CMP_F_I32
10430 
10431  GPUStaticInst*
10433  {
10434  return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
10435  } // decode_OP_VOPC__V_CMP_LT_I32
10436 
10437  GPUStaticInst*
10439  {
10440  return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
10441  } // decode_OP_VOPC__V_CMP_EQ_I32
10442 
10443  GPUStaticInst*
10445  {
10446  return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
10447  } // decode_OP_VOPC__V_CMP_LE_I32
10448 
10449  GPUStaticInst*
10451  {
10452  return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
10453  } // decode_OP_VOPC__V_CMP_GT_I32
10454 
10455  GPUStaticInst*
10457  {
10458  return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
10459  } // decode_OP_VOPC__V_CMP_NE_I32
10460 
10461  GPUStaticInst*
10463  {
10464  return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
10465  } // decode_OP_VOPC__V_CMP_GE_I32
10466 
10467  GPUStaticInst*
10469  {
10470  return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
10471  } // decode_OP_VOPC__V_CMP_T_I32
10472 
10473  GPUStaticInst*
10475  {
10476  return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
10477  } // decode_OP_VOPC__V_CMP_F_U32
10478 
10479  GPUStaticInst*
10481  {
10482  return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
10483  } // decode_OP_VOPC__V_CMP_LT_U32
10484 
10485  GPUStaticInst*
10487  {
10488  return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
10489  } // decode_OP_VOPC__V_CMP_EQ_U32
10490 
10491  GPUStaticInst*
10493  {
10494  return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
10495  } // decode_OP_VOPC__V_CMP_LE_U32
10496 
10497  GPUStaticInst*
10499  {
10500  return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
10501  } // decode_OP_VOPC__V_CMP_GT_U32
10502 
10503  GPUStaticInst*
10505  {
10506  return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
10507  } // decode_OP_VOPC__V_CMP_NE_U32
10508 
10509  GPUStaticInst*
10511  {
10512  return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
10513  } // decode_OP_VOPC__V_CMP_GE_U32
10514 
10515  GPUStaticInst*
10517  {
10518  return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
10519  } // decode_OP_VOPC__V_CMP_T_U32
10520 
10521  GPUStaticInst*
10523  {
10524  return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
10525  } // decode_OP_VOPC__V_CMPX_F_I32
10526 
10527  GPUStaticInst*
10529  {
10530  return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
10531  } // decode_OP_VOPC__V_CMPX_LT_I32
10532 
10533  GPUStaticInst*
10535  {
10536  return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
10537  } // decode_OP_VOPC__V_CMPX_EQ_I32
10538 
10539  GPUStaticInst*
10541  {
10542  return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
10543  } // decode_OP_VOPC__V_CMPX_LE_I32
10544 
10545  GPUStaticInst*
10547  {
10548  return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
10549  } // decode_OP_VOPC__V_CMPX_GT_I32
10550 
10551  GPUStaticInst*
10553  {
10554  return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
10555  } // decode_OP_VOPC__V_CMPX_NE_I32
10556 
10557  GPUStaticInst*
10559  {
10560  return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
10561  } // decode_OP_VOPC__V_CMPX_GE_I32
10562 
10563  GPUStaticInst*
10565  {
10566  return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
10567  } // decode_OP_VOPC__V_CMPX_T_I32
10568 
10569  GPUStaticInst*
10571  {
10572  return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
10573  } // decode_OP_VOPC__V_CMPX_F_U32
10574 
10575  GPUStaticInst*
10577  {
10578  return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
10579  } // decode_OP_VOPC__V_CMPX_LT_U32
10580 
10581  GPUStaticInst*
10583  {
10584  return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
10585  } // decode_OP_VOPC__V_CMPX_EQ_U32
10586 
10587  GPUStaticInst*
10589  {
10590  return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
10591  } // decode_OP_VOPC__V_CMPX_LE_U32
10592 
10593  GPUStaticInst*
10595  {
10596  return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
10597  } // decode_OP_VOPC__V_CMPX_GT_U32
10598 
10599  GPUStaticInst*
10601  {
10602  return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
10603  } // decode_OP_VOPC__V_CMPX_NE_U32
10604 
10605  GPUStaticInst*
10607  {
10608  return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
10609  } // decode_OP_VOPC__V_CMPX_GE_U32
10610 
10611  GPUStaticInst*
10613  {
10614  return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
10615  } // decode_OP_VOPC__V_CMPX_T_U32
10616 
10617  GPUStaticInst*
10619  {
10620  return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
10621  } // decode_OP_VOPC__V_CMP_F_I64
10622 
10623  GPUStaticInst*
10625  {
10626  return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
10627  } // decode_OP_VOPC__V_CMP_LT_I64
10628 
10629  GPUStaticInst*
10631  {
10632  return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
10633  } // decode_OP_VOPC__V_CMP_EQ_I64
10634 
10635  GPUStaticInst*
10637  {
10638  return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
10639  } // decode_OP_VOPC__V_CMP_LE_I64
10640 
10641  GPUStaticInst*
10643  {
10644  return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
10645  } // decode_OP_VOPC__V_CMP_GT_I64
10646 
10647  GPUStaticInst*
10649  {
10650  return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
10651  } // decode_OP_VOPC__V_CMP_NE_I64
10652 
10653  GPUStaticInst*
10655  {
10656  return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
10657  } // decode_OP_VOPC__V_CMP_GE_I64
10658 
10659  GPUStaticInst*
10661  {
10662  return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
10663  } // decode_OP_VOPC__V_CMP_T_I64
10664 
10665  GPUStaticInst*
10667  {
10668  return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
10669  } // decode_OP_VOPC__V_CMP_F_U64
10670 
10671  GPUStaticInst*
10673  {
10674  return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
10675  } // decode_OP_VOPC__V_CMP_LT_U64
10676 
10677  GPUStaticInst*
10679  {
10680  return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
10681  } // decode_OP_VOPC__V_CMP_EQ_U64
10682 
10683  GPUStaticInst*
10685  {
10686  return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
10687  } // decode_OP_VOPC__V_CMP_LE_U64
10688 
10689  GPUStaticInst*
10691  {
10692  return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
10693  } // decode_OP_VOPC__V_CMP_GT_U64
10694 
10695  GPUStaticInst*
10697  {
10698  return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
10699  } // decode_OP_VOPC__V_CMP_NE_U64
10700 
10701  GPUStaticInst*
10703  {
10704  return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
10705  } // decode_OP_VOPC__V_CMP_GE_U64
10706 
10707  GPUStaticInst*
10709  {
10710  return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
10711  } // decode_OP_VOPC__V_CMP_T_U64
10712 
10713  GPUStaticInst*
10715  {
10716  return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
10717  } // decode_OP_VOPC__V_CMPX_F_I64
10718 
10719  GPUStaticInst*
10721  {
10722  return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
10723  } // decode_OP_VOPC__V_CMPX_LT_I64
10724 
10725  GPUStaticInst*
10727  {
10728  return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
10729  } // decode_OP_VOPC__V_CMPX_EQ_I64
10730 
10731  GPUStaticInst*
10733  {
10734  return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
10735  } // decode_OP_VOPC__V_CMPX_LE_I64
10736 
10737  GPUStaticInst*
10739  {
10740  return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
10741  } // decode_OP_VOPC__V_CMPX_GT_I64
10742 
10743  GPUStaticInst*
10745  {
10746  return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
10747  } // decode_OP_VOPC__V_CMPX_NE_I64
10748 
10749  GPUStaticInst*
10751  {
10752  return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
10753  } // decode_OP_VOPC__V_CMPX_GE_I64
10754 
10755  GPUStaticInst*
10757  {
10758  return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
10759  } // decode_OP_VOPC__V_CMPX_T_I64
10760 
10761  GPUStaticInst*
10763  {
10764  return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
10765  } // decode_OP_VOPC__V_CMPX_F_U64
10766 
10767  GPUStaticInst*
10769  {
10770  return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
10771  } // decode_OP_VOPC__V_CMPX_LT_U64
10772 
10773  GPUStaticInst*
10775  {
10776  return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
10777  } // decode_OP_VOPC__V_CMPX_EQ_U64
10778 
10779  GPUStaticInst*
10781  {
10782  return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
10783  } // decode_OP_VOPC__V_CMPX_LE_U64
10784 
10785  GPUStaticInst*
10787  {
10788  return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
10789  } // decode_OP_VOPC__V_CMPX_GT_U64
10790 
10791  GPUStaticInst*
10793  {
10794  return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
10795  } // decode_OP_VOPC__V_CMPX_NE_U64
10796 
10797  GPUStaticInst*
10799  {
10800  return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
10801  } // decode_OP_VOPC__V_CMPX_GE_U64
10802 
10803  GPUStaticInst*
10805  {
10806  return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
10807  } // decode_OP_VOPC__V_CMPX_T_U64
10808 
10809  GPUStaticInst*
10811  {
10812  fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
10813 
10814  return nullptr;
10815  }
10816 } // namespace Gcn3ISA
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:10120
Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:9562
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst)
Definition: decoder.cc:6039
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:7995
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CL_O
Definition: instructions.hh:76098
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_U32(MachInst)
Definition: decoder.cc:8914
Gcn3ISA::Inst_VOP1__V_FRACT_F64
Definition: instructions.hh:17988
Gcn3ISA::Inst_SOPP__S_WAITCNT
Definition: instructions.hh:9004
Gcn3ISA::Inst_VOP1__V_CVT_F16_U16
Definition: instructions.hh:18216
Gcn3ISA::Inst_VOP3__V_RCP_IFLAG_F32
Definition: instructions.hh:50594
Gcn3ISA::Inst_VOP3__V_CVT_PKRTZ_F16_F32
Definition: instructions.hh:58296
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D
Definition: instructions.hh:75018
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CL_O
Definition: instructions.hh:75522
Gcn3ISA::Decoder::decode_OP_VOP1__V_FLOOR_F32
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F32(MachInst)
Definition: decoder.cc:9364
Gcn3ISA::Inst_SOP1__S_CBRANCH_JOIN
Definition: instructions.hh:6904
Gcn3ISA::Decoder::decode_OP_SOP1__S_NOT_B64
GPUStaticInst * decode_OP_SOP1__S_NOT_B64(MachInst)
Definition: decoder.cc:8590
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:9826
Gcn3ISA::InstFormat::iFmt_SMEM
InFmt_SMEM iFmt_SMEM
Definition: gpu_decoder.hh:1626
Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8422
Gcn3ISA::Inst_DS__DS_MAX_SRC2_I64
Definition: instructions.hh:66516
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:10762
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:183
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8398
Gcn3ISA::Inst_SOP1__S_WQM_B32
Definition: instructions.hh:4510
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:7365
Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP
Definition: instructions.hh:72762
Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_U16
GPUStaticInst * decode_OP_VOP2__V_MIN_U16(MachInst)
Definition: decoder.cc:3531
Gcn3ISA::Inst_VOP3__V_CMP_NGT_F16
Definition: instructions.hh:33392
Gcn3ISA::Inst_VOP3__V_MAX_I16
Definition: instructions.hh:48302
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U16(MachInst)
Definition: decoder.cc:6111
Gcn3ISA::Inst_VOP3__V_CMP_NLG_F32
Definition: instructions.hh:35438
Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F32
Definition: instructions.hh:35636
Gcn3ISA::Inst_SOP1__S_BREV_B32
Definition: instructions.hh:4630
Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F32
Definition: instructions.hh:19482
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst)
Definition: decoder.cc:7287
Gcn3ISA::Inst_VOP1__V_RSQ_F16
Definition: instructions.hh:18576
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL
Definition: instructions.hh:75090
Gcn3ISA::Inst_EXP__EXP
Definition: instructions.hh:78978
Gcn3ISA::Inst_VOP3__V_CMP_NLT_F64
Definition: instructions.hh:37814
Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFREV_B32
GPUStaticInst * decode_OPU_VOP3__V_BFREV_B32(MachInst)
Definition: decoder.cc:5673
Gcn3ISA::Inst_VOP1__V_RCP_F16
Definition: instructions.hh:18456
Gcn3ISA::Decoder::decode_OP_SOPP__S_SETKILL
GPUStaticInst * decode_OP_SOPP__S_SETKILL(MachInst)
Definition: decoder.cc:9046
Gcn3ISA::Inst_DS__DS_MAX_SRC2_F64
Definition: instructions.hh:66948
Gcn3ISA::Inst_VOP3__V_CLREXCP
Definition: instructions.hh:51674
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD
Definition: instructions.hh:78546
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:4905
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U64(MachInst)
Definition: decoder.cc:6831
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst)
Definition: decoder.cc:7755
Gcn3ISA::Inst_DS__DS_GWS_BARRIER
Definition: instructions.hh:65952
Gcn3ISA::Inst_VOPC__V_CMPX_F_U16
Definition: instructions.hh:27480
Gcn3ISA::Inst_SOP1__S_ABS_I32
Definition: instructions.hh:6964
Gcn3ISA::Inst_VOP2__V_LDEXP_F16
Definition: instructions.hh:14934
Gcn3ISA::Inst_MIMG__IMAGE_STORE_MIP
Definition: instructions.hh:73170
Gcn3ISA::Inst_VOPC__V_CMP_NLE_F64
Definition: instructions.hh:24676
Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F32
Definition: instructions.hh:23512
Gcn3ISA::Inst_VOP2__V_LSHLREV_B16
Definition: instructions.hh:14340
Gcn3ISA::Inst_VOP3__V_MAX_F16
Definition: instructions.hh:48104
Gcn3ISA::Inst_VOPC__V_CMP_GT_U32
Definition: instructions.hh:28768
Gcn3ISA::Inst_VOPC__V_CMPX_NE_U32
Definition: instructions.hh:29838
Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F64
Definition: instructions.hh:38606
Gcn3ISA::Inst_VOP3__V_CMPX_F_U16
Definition: instructions.hh:40586
Gcn3ISA::Inst_VOP3__V_CVT_PKACCUM_U8_F32
Definition: instructions.hh:56436
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FMA_F64
GPUStaticInst * decode_OPU_VOP3__V_FMA_F64(MachInst)
Definition: decoder.cc:5925
Gcn3ISA::Inst_VOPC__V_CMP_U_F32
Definition: instructions.hh:22368
Gcn3ISA::InstFormat::iFmt_SOP1
InFmt_SOP1 iFmt_SOP1
Definition: gpu_decoder.hh:1628
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_PCK(MachInst)
Definition: decoder.cc:7479
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst)
Definition: decoder.cc:5937
Gcn3ISA::Inst_DS__DS_INC_U32
Definition: instructions.hh:58674
Gcn3ISA::Inst_VOP3__V_COS_F32
Definition: instructions.hh:51014
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:4125
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U32(MachInst)
Definition: decoder.cc:6513
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:10732
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:10330
Gcn3ISA::Decoder::decode_OP_DS__DS_PERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_PERMUTE_B32(MachInst)
Definition: decoder.cc:6651
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:5079
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst)
Definition: decoder.cc:7863
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:4929
Gcn3ISA::InstFormat::iFmt_MUBUF
InFmt_MUBUF iFmt_MUBUF
Definition: gpu_decoder.hh:1624
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:4989
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst)
Definition: decoder.cc:7593
Gcn3ISA::Inst_VOP2__V_LSHRREV_B16
Definition: instructions.hh:14406
Gcn3ISA::Decoder::decode_OPU_VOP3__V_COS_F32
GPUStaticInst * decode_OPU_VOP3__V_COS_F32(MachInst)
Definition: decoder.cc:5661
Gcn3ISA::Inst_VOP3__V_CMP_GT_U32
Definition: instructions.hh:41906
Gcn3ISA::Decoder::decode_OP_SOP1__S_FF0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B32(MachInst)
Definition: decoder.cc:8644
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:7371
Gcn3ISA::Inst_VOP3__V_EXP_F32
Definition: instructions.hh:50414
Gcn3ISA::Inst_VOP1__V_CLREXCP
Definition: instructions.hh:18168
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I64
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I64(MachInst)
Definition: decoder.cc:6279
Gcn3ISA::Decoder::decode_OP_VOP2__V_AND_B32
GPUStaticInst * decode_OP_VOP2__V_AND_B32(MachInst)
Definition: decoder.cc:3351
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
Definition: instructions.hh:76242
Gcn3ISA::Inst_VOP1__V_SIN_F16
Definition: instructions.hh:19176
Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET1_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B32(MachInst)
Definition: decoder.cc:8716
Gcn3ISA::Decoder::decode_OP_SOP2__S_MAX_U32
GPUStaticInst * decode_OP_SOP2__S_MAX_U32(MachInst)
Definition: decoder.cc:3603
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAC_F16
GPUStaticInst * decode_OPU_VOP3__V_MAC_F16(MachInst)
Definition: decoder.cc:5325
Gcn3ISA::Decoder::decode_OP_SOP2__S_XOR_B32
GPUStaticInst * decode_OP_SOP2__S_XOR_B32(MachInst)
Definition: decoder.cc:3645
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RSQ_F32
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F32(MachInst)
Definition: decoder.cc:5625
Gcn3ISA::Decoder::decode_OP_SOPK__S_MULK_I32
GPUStaticInst * decode_OP_SOPK__S_MULK_I32(MachInst)
Definition: decoder.cc:3903
Gcn3ISA::InFmt_SOP1::ENCODING
unsigned int ENCODING
Definition: gpu_decoder.hh:1495
Gcn3ISA::Inst_VOPC__V_CMPX_F_I16
Definition: instructions.hh:26984
Gcn3ISA::Inst_VOP3__V_MIN_U32
Definition: instructions.hh:46268
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:10072
Gcn3ISA::Inst_VOP3__V_QSAD_PK_U16_U8
Definition: instructions.hh:55604
Gcn3ISA::Inst_SOP1__S_MOV_B64
Definition: instructions.hh:4210
Gcn3ISA::Inst_VINTRP__V_INTERP_P1_F32
Definition: instructions.hh:32072
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP
Definition: instructions.hh:79924
Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F32
Definition: instructions.hh:23574
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP
Definition: instructions.hh:79992
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:10624
Gcn3ISA::Decoder::decode_OP_SOP2__S_MAX_I32
GPUStaticInst * decode_OP_SOP2__S_MAX_I32(MachInst)
Definition: decoder.cc:3597
Gcn3ISA::Decoder::decode_OP_DS__DS_INC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U64(MachInst)
Definition: decoder.cc:6801
Gcn3ISA::Inst_VOP3__V_CMP_TRU_F64
Definition: instructions.hh:37880
Gcn3ISA::Inst_VOP3__V_CMPX_F_I16
Definition: instructions.hh:40058
Gcn3ISA::Inst_SOP1__S_BITSET1_B64
Definition: instructions.hh:5770
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:10636
Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F16
Definition: instructions.hh:21654
Gcn3ISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8482
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C(MachInst)
Definition: decoder.cc:7803
Gcn3ISA::Inst_VOPC__V_CMP_EQ_F16
Definition: instructions.hh:19928
Gcn3ISA::Inst_VOPC__V_CMPX_F_F16
Definition: instructions.hh:20848
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FRACT_F64
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F64(MachInst)
Definition: decoder.cc:5709
Gcn3ISA::Inst_DS__DS_DEC_SRC2_U64
Definition: instructions.hh:66408
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst)
Definition: decoder.cc:7203
Gcn3ISA::Inst_VOPC__V_CMPX_GT_U32
Definition: instructions.hh:29776
Gcn3ISA::Inst_VOP3__V_CMPX_F_F16
Definition: instructions.hh:33722
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:9904
Gcn3ISA::Inst_DS__DS_ADD_U64
Definition: instructions.hh:62024
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:5151
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:4653
Gcn3ISA::Inst_VOP3__V_CMPX_NE_U32
Definition: instructions.hh:43028
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN_I16(MachInst)
Definition: decoder.cc:5403
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:10768
Gcn3ISA::Inst_VOP1__V_CEIL_F16
Definition: instructions.hh:18936
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:71658
Gcn3ISA::Inst_SMEM__S_MEMTIME
Definition: instructions.hh:11256
Gcn3ISA::Inst_VOPC__V_CMP_EQ_I16
Definition: instructions.hh:26060
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst)
Definition: decoder.cc:7959
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:4479
Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I16_F16
Definition: instructions.hh:52322
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:10438
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_INC_X2
Definition: instructions.hh:71366
Gcn3ISA::Inst_VOP3__V_CMP_EQ_F16
Definition: instructions.hh:32798
Gcn3ISA::Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8782
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:4269
Gcn3ISA::Decoder::decode_OP_DS__DS_NOP
GPUStaticInst * decode_OP_DS__DS_NOP(MachInst)
Definition: decoder.cc:6447
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_CL
Definition: instructions.hh:76674
Gcn3ISA::Inst_DS__DS_WRXCHG2ST64_RTN_B32
Definition: instructions.hh:60940
Gcn3ISA::Decoder::decode_OP_VOP1__V_SIN_F16
GPUStaticInst * decode_OP_VOP1__V_SIN_F16(MachInst)
Definition: decoder.cc:9598
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst)
Definition: decoder.cc:7581
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:9664
Gcn3ISA::Inst_VOPC__V_CMP_U_F64
Definition: instructions.hh:24412
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:68352
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst)
Definition: decoder.cc:6135
Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_U64
GPUStaticInst * decode_OP_SOP2__S_BFE_U64(MachInst)
Definition: decoder.cc:3783
Gcn3ISA::Inst_VOPC__V_CMPX_F_U32
Definition: instructions.hh:29528
Gcn3ISA::Inst_VOP3__V_MAD_I64_I32
Definition: instructions.hh:55898
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:4701
Gcn3ISA::Inst_DS__DS_MSKOR_B32
Definition: instructions.hh:59214
Gcn3ISA::Inst_VOP3__V_CMP_EQ_I16
Definition: instructions.hh:39134
Gcn3ISA::Inst_VOP3__V_LSHLREV_B32
Definition: instructions.hh:46532
Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F32
Definition: instructions.hh:55082
Gcn3ISA::Inst_DS__DS_MIN_U64
Definition: instructions.hh:62444
Gcn3ISA::Inst_VOPC__V_CMP_T_I16
Definition: instructions.hh:26390
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBETC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBETC_F32(MachInst)
Definition: decoder.cc:5889
Gcn3ISA::Inst_SOPP__S_WAKEUP
Definition: instructions.hh:8506
Gcn3ISA::Inst_VOPC__V_CMP_GT_U16
Definition: instructions.hh:26720
Gcn3ISA::Inst_VOP3__V_CMPX_F_U32
Definition: instructions.hh:42698
Gcn3ISA::Inst_VOP3__V_FFBH_I32
Definition: instructions.hh:51314
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:4545
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8037
Gcn3ISA::Inst_VOP3__V_MUL_LO_U16
Definition: instructions.hh:47840
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B_CL
Definition: instructions.hh:74730
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:72324
Gcn3ISA::Inst_DS__DS_DEC_SRC2_U32
Definition: instructions.hh:65022
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:10378
Gcn3ISA::Inst_DS__DS_READ_B64
Definition: instructions.hh:64554
Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst)
Definition: decoder.cc:6171
Gcn3ISA::Inst_VOP2__V_MUL_LEGACY_F32
Definition: instructions.hh:11766
Gcn3ISA::Decoder::decode_OP_SOP2__S_AND_B32
GPUStaticInst * decode_OP_SOP2__S_AND_B32(MachInst)
Definition: decoder.cc:3621
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F16_U16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:9502
Gcn3ISA::Inst_DS__DS_MAX_RTN_F32
Definition: instructions.hh:61204
Gcn3ISA::Inst_VOP3__V_CVT_U32_F64
Definition: instructions.hh:49754
Gcn3ISA::Decoder::decode_OP_DS__DS_OR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B64(MachInst)
Definition: decoder.cc:6843
Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst)
Definition: decoder.cc:6561
Gcn3ISA::Inst_VOP3__V_LSHRREV_B32
Definition: instructions.hh:46400
Gcn3ISA::Inst_VOP3__V_CMP_GT_U16
Definition: instructions.hh:39794
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8013
Gcn3ISA::Inst_VOP3__V_CMPX_GT_U32
Definition: instructions.hh:42962
Gcn3ISA::Inst_VOP2__V_MIN_U16
Definition: instructions.hh:14802
Gcn3ISA::Inst_VOP3__V_CVT_F32_F16
Definition: instructions.hh:49154
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:4221
Gcn3ISA::Inst_VOP1__V_FFBH_U32
Definition: instructions.hh:17688
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:5073
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:4371
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:4617
Gcn3ISA::Inst_DS__DS_MAX_RTN_I32
Definition: instructions.hh:60346
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:10300
Gcn3ISA::Inst_DS__DS_XOR_RTN_B64
Definition: instructions.hh:63960
Gcn3ISA::Decoder::decode_OP_VOP1__V_FRACT_F32
GPUStaticInst * decode_OP_VOP1__V_FRACT_F32(MachInst)
Definition: decoder.cc:9340
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_AND
Definition: instructions.hh:80460
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:9760
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:8464
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:9946
Gcn3ISA::Inst_SOP1__S_CMOV_B64
Definition: instructions.hh:4330
Gcn3ISA::Decoder::decode_OP_SOP2__S_MIN_U32
GPUStaticInst * decode_OP_SOP2__S_MIN_U32(MachInst)
Definition: decoder.cc:3591
Gcn3ISA::Inst_SOP2__S_MUL_I32
Definition: instructions.hh:2422
Gcn3ISA::InstFormat::iFmt_VOPC
InFmt_VOPC iFmt_VOPC
Definition: gpu_decoder.hh:1639
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:7275
Gcn3ISA::Inst_VOPC__V_CMPX_LE_U64
Definition: instructions.hh:31762
Gcn3ISA::Inst_SOP2__S_MIN_U32
Definition: instructions.hh:508
Gcn3ISA::Inst_VOPC__V_CMPX_F_I32
Definition: instructions.hh:29032
Gcn3ISA::Inst_VOP3__V_MUL_HI_U32_U24
Definition: instructions.hh:45938
Gcn3ISA::Inst_VOP3__V_SUB_U32
Definition: instructions.hh:46934
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:9262
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:68278
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_I8
GPUStaticInst * decode_OP_DS__DS_READ_I8(MachInst)
Definition: decoder.cc:6621
Gcn3ISA::Inst_SOP1__S_SEXT_I32_I16
Definition: instructions.hh:5530
Gcn3ISA::Inst_DS__DS_SWIZZLE_B32
Definition: instructions.hh:61832
Gcn3ISA::Inst_VOPC__V_CMP_LE_F16
Definition: instructions.hh:19994
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F64_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:5541
Gcn3ISA::Inst_VOP3__V_CMPX_F_I32
Definition: instructions.hh:42170
Gcn3ISA::Inst_VOP1__V_CVT_F32_F16
Definition: instructions.hh:15648
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:4509
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:4389
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_U32(MachInst)
Definition: decoder.cc:3879
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_F32
GPUStaticInst * decode_OPU_VOP3__V_ADD_F32(MachInst)
Definition: decoder.cc:5133
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:9916
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_L
Definition: instructions.hh:77178
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:9976
Gcn3ISA::Inst_SMEM__S_LOAD_DWORD
Definition: instructions.hh:9976
Gcn3ISA::Inst_DS__DS_ADD_F32
Definition: instructions.hh:59766
Gcn3ISA::Inst_VOP1__V_CVT_U32_F64
Definition: instructions.hh:16248
Gcn3ISA::Inst_VOPC__V_CMPX_F_F32
Definition: instructions.hh:22892
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:4689
Gcn3ISA::Inst_VOP3__V_CMPX_F_F32
Definition: instructions.hh:35834
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:5745
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_I64
GPUStaticInst * decode_OP_DS__DS_MAX_I64(MachInst)
Definition: decoder.cc:6699
Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F64
Definition: instructions.hh:25618
Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGSYS
Definition: instructions.hh:9598
Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F64
Definition: instructions.hh:25680
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_F16
GPUStaticInst * decode_OP_VOP2__V_SUB_F16(MachInst)
Definition: decoder.cc:3429
Gcn3ISA::Inst_VOP3__V_MAD_LEGACY_F32
Definition: instructions.hh:52922
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_F32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F32(MachInst)
Definition: decoder.cc:5145
Gcn3ISA::Inst_DS__DS_MAX_SRC2_U64
Definition: instructions.hh:66624
Gcn3ISA::Inst_VOPC__V_CMP_LE_I16
Definition: instructions.hh:26126
Gcn3ISA::Inst_SOP2__S_BFE_U64
Definition: instructions.hh:2620
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_F16(MachInst)
Definition: decoder.cc:6105
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:10228
Gcn3ISA::Inst_DS__DS_OR_SRC2_B32
Definition: instructions.hh:65346
Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B64(MachInst)
Definition: decoder.cc:6855
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:4767
Gcn3ISA::Inst_DS__DS_READ2ST64_B32
Definition: instructions.hh:61526
Gcn3ISA::Inst_VOP3__V_CMP_U_F32
Definition: instructions.hh:35306
Gcn3ISA::Inst_VOP2__V_MIN_I16
Definition: instructions.hh:14868
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
Definition: instructions.hh:71510
Gcn3ISA::Inst_VOP3__V_RSQ_F32
Definition: instructions.hh:50654
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U64(MachInst)
Definition: decoder.cc:8968
Gcn3ISA::Inst_VOP3__V_ASHRREV_I64
Definition: instructions.hh:57966
Gcn3ISA::Inst_VOP3__V_RCP_F32
Definition: instructions.hh:50534
Gcn3ISA::Inst_VOP3__V_CMP_LE_F16
Definition: instructions.hh:32864
Gcn3ISA::Inst_VOP3__V_MAX_F64
Definition: instructions.hh:57108
Gcn3ISA::Inst_VOPC__V_CMP_NGT_F32
Definition: instructions.hh:22566
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst)
Definition: decoder.cc:7509
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B8
GPUStaticInst * decode_OP_DS__DS_WRITE_B8(MachInst)
Definition: decoder.cc:6459
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:4185
Gcn3ISA::Inst_SOP2__S_MIN_I32
Definition: instructions.hh:442
Gcn3ISA::Inst_SOP2__S_NAND_B64
Definition: instructions.hh:1564
Gcn3ISA::Inst_DS__DS_AND_RTN_B32
Definition: instructions.hh:60544
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:4605
Gcn3ISA::Inst_VOP3__V_CMP_LE_I16
Definition: instructions.hh:39200
Gcn3ISA::Decoder::decode_OP_DS__DS_OR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B64(MachInst)
Definition: decoder.cc:7137
Gcn3ISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN
Definition: instructions.hh:72898
Gcn3ISA::Inst_VOP3__V_FRACT_F64
Definition: instructions.hh:51494
Gcn3ISA::Inst_SOPC__S_BITCMP1_B64
Definition: instructions.hh:8044
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B64
GPUStaticInst * decode_OP_DS__DS_READ_B64(MachInst)
Definition: decoder.cc:6903
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:8007
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_B64(MachInst)
Definition: decoder.cc:6759
Gcn3ISA::Inst_VOP2__V_MIN_F16
Definition: instructions.hh:14604
Gcn3ISA::Decoder::decode_OP_SOP2__S_AND_B64
GPUStaticInst * decode_OP_SOP2__S_AND_B64(MachInst)
Definition: decoder.cc:3627
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_LZ_O
Definition: instructions.hh:77826
Gcn3ISA::Decoder::decode_OP_VOP1__V_SQRT_F32
GPUStaticInst * decode_OP_VOP1__V_SQRT_F32(MachInst)
Definition: decoder.cc:9412
Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F16
Definition: instructions.hh:32600
Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE2
Definition: instructions.hh:49634
Gcn3ISA::Inst_VOP3__V_CMPX_LE_U64
Definition: instructions.hh:45008
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:7983
Gcn3ISA::Inst_VOPC__V_CMPX_GE_U16
Definition: instructions.hh:27852
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBBREV_U32(MachInst)
Definition: decoder.cc:3417
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:9256
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CEIL_F32
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F32(MachInst)
Definition: decoder.cc:5583
Gcn3ISA::Inst_VOP3__V_MUL_LO_U32
Definition: instructions.hh:57240
Gcn3ISA::Inst_SOPC__S_CMP_LG_I32
Definition: instructions.hh:7204
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_INC
Definition: instructions.hh:70430
Gcn3ISA::Inst_VOP3__V_LERP_U8
Definition: instructions.hh:53858
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:10546
Gcn3ISA::Inst_VOPC__V_CMP_GE_U64
Definition: instructions.hh:30948
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_ADD
Definition: instructions.hh:73572
Gcn3ISA::Inst_VOP1__V_TRUNC_F16
Definition: instructions.hh:18996
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:9880
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_F16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F16(MachInst)
Definition: decoder.cc:3435
Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_U32
GPUStaticInst * decode_OP_VOP2__V_MIN_U32(MachInst)
Definition: decoder.cc:3321
Gcn3ISA::InFmt_SOPP
Definition: gpu_decoder.hh:1520
Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE3
Definition: instructions.hh:49694
Gcn3ISA::Inst_SOP2__S_BFE_I64
Definition: instructions.hh:2686
Gcn3ISA::Decoder::decode_OP_SOP1__S_QUADMASK_B32
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B32(MachInst)
Definition: decoder.cc:8800
Gcn3ISA::Inst_FLAT__FLAT_STORE_BYTE
Definition: instructions.hh:79552
Gcn3ISA::Inst_SOP2__S_LSHL_B32
Definition: instructions.hh:1894
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_I32(MachInst)
Definition: decoder.cc:3849
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B_O
Definition: instructions.hh:76386
Gcn3ISA::Inst_DS__DS_READ2ST64_B64
Definition: instructions.hh:64678
Gcn3ISA::Decoder::decode_OPU_VOP3__V_XOR_B32
GPUStaticInst * decode_OPU_VOP3__V_XOR_B32(MachInst)
Definition: decoder.cc:5253
Gcn3ISA::Inst_VOP3__V_SIN_F32
Definition: instructions.hh:50954
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:5751
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I64(MachInst)
Definition: decoder.cc:6813
Gcn3ISA::Inst_VOP3__V_RNDNE_F32
Definition: instructions.hh:50294
Gcn3ISA::Decoder::decode_OP_SOPP__S_BARRIER
GPUStaticInst * decode_OP_SOPP__S_BARRIER(MachInst)
Definition: decoder.cc:9040
Gcn3ISA::Inst_VOP2__V_MIN_U32
Definition: instructions.hh:12426
Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U32(MachInst)
Definition: decoder.cc:6495
Gcn3ISA::Inst_SOPK__S_MULK_I32
Definition: instructions.hh:3850
Gcn3ISA::Inst_VOP3__V_CMP_GE_U64
Definition: instructions.hh:44150
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8116
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_F16
GPUStaticInst * decode_OPU_VOP3__V_ADD_F16(MachInst)
Definition: decoder.cc:5301
Gcn3ISA::Inst_SOP2__S_ADDC_U32
Definition: instructions.hh:310
Gcn3ISA::Inst_DS__DS_GWS_SEMA_V
Definition: instructions.hh:65784
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FFBL_B32
GPUStaticInst * decode_OPU_VOP3__V_FFBL_B32(MachInst)
Definition: decoder.cc:5685
Gcn3ISA::Decoder::decode_OP_DS__DS_OR_B64
GPUStaticInst * decode_OP_DS__DS_OR_B64(MachInst)
Definition: decoder.cc:6723
Gcn3ISA::Inst_VOPC__V_CMP_NLG_F64
Definition: instructions.hh:24544
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:3285
Gcn3ISA::Inst_VOP1__V_EXP_LEGACY_F32
Definition: instructions.hh:19296
Gcn3ISA::Inst_VOP3__V_CMPX_NE_I32
Definition: instructions.hh:42500
Gcn3ISA::Inst_VOP2__V_MADAK_F16
Definition: instructions.hh:14004
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FFBH_I32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_I32(MachInst)
Definition: decoder.cc:5691
Gcn3ISA::Inst_VOP3__V_SUBREV_F16
Definition: instructions.hh:47444
Gcn3ISA::Inst_VOP3__V_CVT_F64_I32
Definition: instructions.hh:48734
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:67982
Gcn3ISA::Inst_DS__DS_OR_RTN_B64
Definition: instructions.hh:63894
Gcn3ISA::Inst_VOPC__V_CMP_LE_F32
Definition: instructions.hh:22038
Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I32_F64
Definition: instructions.hh:17868
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:5445
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:4413
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F64(MachInst)
Definition: decoder.cc:6891
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:72250
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_I32(MachInst)
Definition: decoder.cc:8884
Gcn3ISA::InstFormat::iFmt_FLAT
InFmt_FLAT iFmt_FLAT
Definition: gpu_decoder.hh:1617
Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP0_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B64(MachInst)
Definition: decoder.cc:8944
Gcn3ISA::Inst_VOP1__V_MOV_FED_B32
Definition: instructions.hh:15528
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F64_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:5433
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F64(MachInst)
Definition: decoder.cc:7155
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst)
Definition: decoder.cc:9136
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
Definition: instructions.hh:76458
Gcn3ISA::Inst_VOP2__V_MUL_HI_I32_I24
Definition: instructions.hh:11964
Gcn3ISA::Inst_VOP3__V_CMPX_GE_U16
Definition: instructions.hh:40982
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst)
Definition: decoder.cc:5853
Gcn3ISA::Inst_VOP3__V_CVT_F64_F32
Definition: instructions.hh:49454
Gcn3ISA::Inst_VOPC__V_CMP_LE_I32
Definition: instructions.hh:28174
Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U32(MachInst)
Definition: decoder.cc:6933
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LOG_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_F32(MachInst)
Definition: decoder.cc:5607
Gcn3ISA::Inst_VOP1__V_CVT_F64_I32
Definition: instructions.hh:15228
Gcn3ISA::Inst_SOP2__S_BFM_B32
Definition: instructions.hh:2290
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:4881
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:10018
Gcn3ISA::Inst_VOP2__V_MIN_I32
Definition: instructions.hh:12294
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:4383
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX3_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U32(MachInst)
Definition: decoder.cc:5979
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L(MachInst)
Definition: decoder.cc:7779
Gcn3ISA::Decoder::decode_OP_SOPK__S_ADDK_I32
GPUStaticInst * decode_OP_SOPK__S_ADDK_I32(MachInst)
Definition: decoder.cc:3897
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8230
Gcn3ISA::Inst_VOP3__V_CMP_LE_F32
Definition: instructions.hh:34976
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F32(MachInst)
Definition: decoder.cc:9850
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:10186
Gcn3ISA::Inst_VOP3__V_DIV_SCALE_F64
Definition: instructions.hh:55304
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:10486
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Definition: instructions.hh:81064
Gcn3ISA::Decoder::subDecode_OP_VINTRP
GPUStaticInst * subDecode_OP_VINTRP(MachInst)
Definition: decoder.cc:3189
Gcn3ISA::Inst_FLAT__FLAT_LOAD_UBYTE
Definition: instructions.hh:79056
Gcn3ISA::Inst_VOP3__V_ADD_U16
Definition: instructions.hh:47642
Gcn3ISA::Inst_VOP2__V_MAC_F16
Definition: instructions.hh:13866
Gcn3ISA::Inst_VOP3__V_CMP_LE_I32
Definition: instructions.hh:41312
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I32(MachInst)
Definition: decoder.cc:4785
Gcn3ISA::Inst_VOP1__V_CVT_F64_F32
Definition: instructions.hh:15948
Gcn3ISA::Inst_DS__DS_WRITE2_B64
Definition: instructions.hh:62866
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_OR
Definition: instructions.hh:80526
Gcn3ISA::Inst_VOPC__V_CMP_GE_F32
Definition: instructions.hh:22236
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
Definition: instructions.hh:69710
Gcn3ISA::Decoder::decode_OP_SOP2__S_ADDC_U32
GPUStaticInst * decode_OP_SOP2__S_ADDC_U32(MachInst)
Definition: decoder.cc:3573
Gcn3ISA::Inst_VOP2__V_MIN_F32
Definition: instructions.hh:12162
Gcn3ISA::Decoder::decode_OP_VOP1__V_MOV_FED_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:9232
Gcn3ISA::Inst_VOP3__V_CNDMASK_B32
Definition: instructions.hh:45338
Gcn3ISA::Inst_SOPP__S_ICACHE_INV
Definition: instructions.hh:9382
Gcn3ISA::Inst_DS__DS_SUB_RTN_U64
Definition: instructions.hh:63300
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:5361
Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4
Definition: instructions.hh:10452
Gcn3ISA::Inst_DS__DS_READ_B96
Definition: instructions.hh:67122
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F16_U16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:5733
Gcn3ISA::Inst_VOP3__V_MOV_FED_B32
Definition: instructions.hh:49034
Gcn3ISA::Inst_VOPC__V_CMPX_NE_I32
Definition: instructions.hh:29342
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:3945
Gcn3ISA::Inst_VOPC__V_CMP_O_F16
Definition: instructions.hh:20258
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:3987
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst)
Definition: decoder.cc:7737
Gcn3ISA::Inst_VOPC__V_CMPX_GE_U32
Definition: instructions.hh:29900
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:4527
Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F64
Definition: instructions.hh:25494
Gcn3ISA::Inst_DS__DS_WRITE_B64
Definition: instructions.hh:62804
Gcn3ISA::Inst_SOP2__S_ANDN2_B64
Definition: instructions.hh:1300
Gcn3ISA::Inst_VOPC__V_CMP_GE_I32
Definition: instructions.hh:28372
Gcn3ISA::Inst_VOP3__V_CVT_F16_F32
Definition: instructions.hh:49094
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:4869
Gcn3ISA::Inst_VOP3__V_CMPX_GT_F32
Definition: instructions.hh:36098
Gcn3ISA::Decoder::decode_OPU_VOP3__V_BCNT_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_BCNT_U32_B32(MachInst)
Definition: decoder.cc:6249
Gcn3ISA::Inst_VOP3__V_CMP_GE_F32
Definition: instructions.hh:35174
Gcn3ISA::Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8776
Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX4
Definition: instructions.hh:79490
Gcn3ISA::Inst_VOPC__V_CMP_NGE_F16
Definition: instructions.hh:20390
Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B64(MachInst)
Definition: decoder.cc:8638
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN3_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F32(MachInst)
Definition: decoder.cc:5949
Gcn3ISA::Inst_VOPC__V_CMPX_T_U16
Definition: instructions.hh:27914
Gcn3ISA::Inst_VOP3__V_CMPX_GT_I32
Definition: instructions.hh:42434
Gcn3ISA::Inst_VOP3__V_INTERP_P2_F32
Definition: instructions.hh:56568
Gcn3ISA::Inst_VOP2__V_SUB_U32
Definition: instructions.hh:13224
Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F16
Definition: instructions.hh:18756
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_U8(MachInst)
Definition: decoder.cc:6003
Gcn3ISA::Decoder::subDecode_OP_VOPC
GPUStaticInst * subDecode_OP_VOPC(MachInst)
Definition: decoder.cc:3133
Gcn3ISA::Inst_VOP3__V_CMP_GE_I32
Definition: instructions.hh:41510
Gcn3ISA::Inst_VOP1__V_FFBH_I32
Definition: instructions.hh:17808
Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst)
Definition: decoder.cc:6873
Gcn3ISA::Inst_DS__DS_WRITE_SRC2_B64
Definition: instructions.hh:66840
Gcn3ISA::Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:9610
Gcn3ISA::Inst_DS__DS_INC_SRC2_U64
Definition: instructions.hh:66354
Gcn3ISA::Inst_VOP1__V_CVT_F16_F32
Definition: instructions.hh:15588
Gcn3ISA::Inst_VOP3__V_CMPX_T_U16
Definition: instructions.hh:41048
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_UMAX
Definition: instructions.hh:73902
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst)
Definition: decoder.cc:7773
Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE0
Definition: instructions.hh:16008
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B_CL_O
Definition: instructions.hh:77754
Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:6159
Gcn3ISA::Decoder::subDecode_OP_MIMG
GPUStaticInst * subDecode_OP_MIMG(MachInst)
Definition: decoder.cc:3229
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:4233
Gcn3ISA::Inst_VOPC__V_CMP_LG_F64
Definition: instructions.hh:24214
Gcn3ISA::Inst_SOP2__S_XOR_B64
Definition: instructions.hh:1168
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I64(MachInst)
Definition: decoder.cc:7107
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:9790
Gcn3ISA::Inst_DS__DS_ADD_SRC2_U64
Definition: instructions.hh:66192
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:10126
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SQRT_F32
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F32(MachInst)
Definition: decoder.cc:5643
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B_O
Definition: instructions.hh:77682
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CL
Definition: instructions.hh:74370
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX2
Definition: instructions.hh:69256
Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F64
Definition: instructions.hh:25804
Gcn3ISA::Inst_VOP3__V_MIN_I16
Definition: instructions.hh:48434
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:5427
Gcn3ISA::Inst_DS__DS_GWS_INIT
Definition: instructions.hh:65724
Gcn3ISA::Decoder::decode_OP_SOP1__S_FF1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B32(MachInst)
Definition: decoder.cc:8656
Gcn3ISA::Inst_VOP3__V_CMPX_GE_U32
Definition: instructions.hh:43094
Gcn3ISA::Inst_VOP3__V_CMP_NGE_F64
Definition: instructions.hh:37484
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_F32(MachInst)
Definition: decoder.cc:5613
Gcn3ISA::Decoder::decode_OP_SOPP__S_SETHALT
GPUStaticInst * decode_OP_SOPP__S_SETHALT(MachInst)
Definition: decoder.cc:9058
Gcn3ISA::Inst_VOP1__V_FRACT_F16
Definition: instructions.hh:19116
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_U64(MachInst)
Definition: decoder.cc:6705
Gcn3ISA::Inst_VOP3__V_CMPX_LE_I64
Definition: instructions.hh:44480
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_U16
GPUStaticInst * decode_OP_DS__DS_READ_U16(MachInst)
Definition: decoder.cc:6639
Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F32
Definition: instructions.hh:19416
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX
Definition: instructions.hh:70142
Gcn3ISA::Inst_VOPC__V_CMPX_T_I16
Definition: instructions.hh:27418
Gcn3ISA::Inst_VOP3__V_CMP_LG_F64
Definition: instructions.hh:37220
Gcn3ISA::Inst_VOPC__V_CMPX_GT_F32
Definition: instructions.hh:23140
Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U32(MachInst)
Definition: decoder.cc:6477
Gcn3ISA::Inst_VOP3__V_MIN_F16
Definition: instructions.hh:48170
Gcn3ISA::Decoder::decode_OP_VOP1__V_MOV_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_B32(MachInst)
Definition: decoder.cc:9184
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst)
Definition: decoder.cc:7899
Gcn3ISA::Inst_VOP3__V_CMPX_LE_F64
Definition: instructions.hh:38144
Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX2
Definition: instructions.hh:79738
Gcn3ISA::Inst_VOP1__V_COS_F32
Definition: instructions.hh:17508
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F64_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:9310
Gcn3ISA::Inst_VOP3__V_CMPX_T_I16
Definition: instructions.hh:40520
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_F32(MachInst)
Definition: decoder.cc:3267
Gcn3ISA::Decoder::decode_OP_SOP1__S_ABS_I32
GPUStaticInst * decode_OP_SOP1__S_ABS_I32(MachInst)
Definition: decoder.cc:8842
Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F64
Definition: instructions.hh:32468
Gcn3ISA::Inst_VOP3__V_ADD_U32
Definition: instructions.hh:46862
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B64(MachInst)
Definition: decoder.cc:6273
Gcn3ISA::Inst_VOPC__V_CMPX_GT_I32
Definition: instructions.hh:29280
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst)
Definition: decoder.cc:7905
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_EQ_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_I32(MachInst)
Definition: decoder.cc:8860
Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFE_I32
GPUStaticInst * decode_OPU_VOP3__V_BFE_I32(MachInst)
Definition: decoder.cc:5907
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:10222
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:67908
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U64(MachInst)
Definition: decoder.cc:10708
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:10210
Gcn3ISA::Inst_DS__DS_WRXCHG2_RTN_B32
Definition: instructions.hh:60874
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_O
Definition: instructions.hh:75450
Gcn3ISA::Inst_DS__DS_MIN_I64
Definition: instructions.hh:62324
Gcn3ISA::Inst_VOP2__V_SUB_F32
Definition: instructions.hh:11634
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:9958
Gcn3ISA::Inst_VOP1__V_EXP_F32
Definition: instructions.hh:16908
Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U64(MachInst)
Definition: decoder.cc:6789
Gcn3ISA::Decoder::decode_OP_VOP1__V_CLREXCP
GPUStaticInst * decode_OP_VOP1__V_CLREXCP(MachInst)
Definition: decoder.cc:9496
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:10612
Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET1_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B64(MachInst)
Definition: decoder.cc:8722
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:7977
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst)
Definition: decoder.cc:7725
Gcn3ISA::Inst_VOP3__V_CMP_NLT_F16
Definition: instructions.hh:33590
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:4863
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC1
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC1(MachInst)
Definition: decoder.cc:9010
Gcn3ISA::Inst_VOP3__V_CVT_OFF_F32_I4
Definition: instructions.hh:49334
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:9820
Gcn3ISA::Inst_VOP3__V_MQSAD_U32_U8
Definition: instructions.hh:55748
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX4
Definition: instructions.hh:69404
Gcn3ISA::Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:9616
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:4443
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B_O
Definition: instructions.hh:78114
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:10078
Gcn3ISA::Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX
GPUStaticInst * decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst)
Definition: decoder.cc:8854
Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC0
Definition: instructions.hh:8560
Gcn3ISA::Inst_DS__DS_MIN_F64
Definition: instructions.hh:63114
Gcn3ISA::Inst_VOP1__V_CVT_FLR_I32_F32
Definition: instructions.hh:15768
Gcn3ISA::Inst_VOPC__V_CMP_NLE_F16
Definition: instructions.hh:20588
Gcn3ISA::Decoder::subDecode_OP_VOP1
GPUStaticInst * subDecode_OP_VOP1(MachInst)
Definition: decoder.cc:3141
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I16(MachInst)
Definition: decoder.cc:6117
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:5517
Gcn3ISA::Decoder::tableSubDecode_OP_FLAT
static IsaDecodeMethod tableSubDecode_OP_FLAT[128]
Definition: gpu_decoder.hh:66
Gcn3ISA::Inst_VOPC__V_CMP_NGE_F32
Definition: instructions.hh:22434
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
Definition: instructions.hh:71294
Gcn3ISA::Inst_SOPP__S_BARRIER
Definition: instructions.hh:8896
Gcn3ISA::Inst_MUBUF__BUFFER_WBINVL1_VOL
Definition: instructions.hh:69588
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
Definition: instructions.hh:70574
Gcn3ISA::Inst_VOP3__V_INTERP_P2_F16
Definition: instructions.hh:56838
Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_U32
GPUStaticInst * decode_OP_SOP2__S_BFE_U32(MachInst)
Definition: decoder.cc:3771
Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst)
Definition: decoder.cc:8524
Gcn3ISA::Inst_VOP2__V_ASHRREV_I16
Definition: instructions.hh:14472
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:10780
Gcn3ISA::Inst_VOPC__V_CMPX_LE_I64
Definition: instructions.hh:31266
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:4797
Gcn3ISA::Inst_VOPC__V_CMP_GT_F32
Definition: instructions.hh:22104
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:7407
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:8086
Gcn3ISA::Inst_DS__DS_INC_RTN_U64
Definition: instructions.hh:63432
Gcn3ISA::Inst_VOP1__V_FLOOR_F64
Definition: instructions.hh:16548
Gcn3ISA::Inst_DS__DS_SUB_U32
Definition: instructions.hh:58554
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I64(MachInst)
Definition: decoder.cc:10660
Gcn3ISA::Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON
GPUStaticInst * decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst)
Definition: decoder.cc:8962
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:4779
Gcn3ISA::Inst_SOP1__S_AND_SAVEEXEC_B64
Definition: instructions.hh:6064
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_INC
Definition: instructions.hh:74166
Gcn3ISA::Inst_VOPC__V_CMPX_LE_F64
Definition: instructions.hh:25122
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8266
Gcn3ISA::Inst_VOP3__V_TRUNC_F16
Definition: instructions.hh:52502
Gcn3ISA::Inst_VOP3__V_CVT_F64_U32
Definition: instructions.hh:49814
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:4707
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_RTN_U32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U32(MachInst)
Definition: decoder.cc:6471
Gcn3ISA::Inst_SOP2__S_OR_B32
Definition: instructions.hh:970
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_F32(MachInst)
Definition: decoder.cc:6429
Gcn3ISA::Inst_VOPC__V_CMP_GT_I32
Definition: instructions.hh:28240
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD_O
Definition: instructions.hh:78690
Gcn3ISA::Inst_VOP3__V_CMPX_GE_F16
Definition: instructions.hh:34118
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:10564
Gcn3ISA::Decoder::tableDecodePrimary
static IsaDecodeMethod tableDecodePrimary[512]
Definition: gpu_decoder.hh:63
Gcn3ISA::Inst_DS__DS_MIN_SRC2_I32
Definition: instructions.hh:65076
Gcn3ISA::Inst_SOP2__S_LSHR_B32
Definition: instructions.hh:2026
Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U32(MachInst)
Definition: decoder.cc:6939
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOV_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_B32(MachInst)
Definition: decoder.cc:8560
Gcn3ISA::Inst_VOP3__V_MIN_I32
Definition: instructions.hh:46136
Gcn3ISA::Decoder::decode_OP_SOP1__S_SETPC_B64
GPUStaticInst * decode_OP_SOP1__S_SETPC_B64(MachInst)
Definition: decoder.cc:8734
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:4521
Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst)
Definition: decoder.cc:6861
Gcn3ISA::Inst_VOP3__V_CMP_GT_F32
Definition: instructions.hh:35042
Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_F32
GPUStaticInst * decode_OP_VOP2__V_ADD_F32(MachInst)
Definition: decoder.cc:3243
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst)
Definition: decoder.cc:8242
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst)
Definition: decoder.cc:8170
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:10312
Gcn3ISA::Inst_VOP3__V_CMPX_GE_I16
Definition: instructions.hh:40454
Gcn3ISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8488
Gcn3ISA::Inst_SOP2__S_LSHL_B64
Definition: instructions.hh:1960
Gcn3ISA::Inst_SOP1__S_NAND_SAVEEXEC_B64
Definition: instructions.hh:6364
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst)
Definition: decoder.cc:7665
Gcn3ISA::Inst_VOP1__V_CVT_F64_U32
Definition: instructions.hh:16308
Gcn3ISA::Inst_VOP3__V_CMP_GT_I32
Definition: instructions.hh:41378
Gcn3ISA::Inst_VOP3__V_EXP_LEGACY_F32
Definition: instructions.hh:52802
Gcn3ISA::Inst_VOP2__V_ADD_U16
Definition: instructions.hh:14076
Gcn3ISA::Inst_VOP3__V_MAC_F16
Definition: instructions.hh:47576
Gcn3ISA::Inst_DS__DS_XOR_SRC2_B64
Definition: instructions.hh:66786
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_U32
GPUStaticInst * decode_OP_VOP2__V_MAX_U32(MachInst)
Definition: decoder.cc:3327
Gcn3ISA::Inst_DS__DS_MIN_SRC2_F32
Definition: instructions.hh:65508
Gcn3ISA::Inst_VOP3__V_CUBEMA_F32
Definition: instructions.hh:53426
Gcn3ISA::Inst_VOP3__V_MIN_F32
Definition: instructions.hh:46004
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:4119
Gcn3ISA::Inst_VOPC__V_CMPX_LT_U32
Definition: instructions.hh:29590
Gcn3ISA::Inst_VOP3__V_LOG_F32
Definition: instructions.hh:50474
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst)
Definition: decoder.cc:6045
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:7359
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:4053
Gcn3ISA::Decoder::decode_OP_SOP1__S_CMOV_B64
GPUStaticInst * decode_OP_SOP1__S_CMOV_B64(MachInst)
Definition: decoder.cc:8578
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:9802
Gcn3ISA::Inst_SMEM__S_DCACHE_INV_VOL
Definition: instructions.hh:11160
Gcn3ISA::Inst_SOPP__S_SETHALT
Definition: instructions.hh:9058
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst)
Definition: decoder.cc:7557
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_F32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F32(MachInst)
Definition: decoder.cc:3255
Gcn3ISA::Inst_VOP3__V_SAD_HI_U8
Definition: instructions.hh:54794
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:7317
Gcn3ISA::Decoder::decode_OP_SOP2__S_MUL_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_I32(MachInst)
Definition: decoder.cc:3765
Gcn3ISA::Inst_DS__DS_ADD_RTN_U32
Definition: instructions.hh:59950
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:10594
Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:9466
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RNDNE_F16
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F16(MachInst)
Definition: decoder.cc:5817
Gcn3ISA::Inst_SMEM__S_ATC_PROBE
Definition: instructions.hh:11364
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8140
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I64(MachInst)
Definition: decoder.cc:4977
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX
Definition: instructions.hh:70070
Gcn3ISA::Decoder::decode_OP_SOP2__S_OR_B64
GPUStaticInst * decode_OP_SOP2__S_OR_B64(MachInst)
Definition: decoder.cc:3639
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_LZ
Definition: instructions.hh:76962
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst)
Definition: decoder.cc:7485
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:10396
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:5355
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst)
Definition: decoder.cc:7341
Gcn3ISA::Decoder::decode_OP_SOP2__S_ANDN2_B64
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B64(MachInst)
Definition: decoder.cc:3663
Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP1_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B64(MachInst)
Definition: decoder.cc:8950
Gcn3ISA::Decoder::decode_OP_VOP1__V_CEIL_F32
GPUStaticInst * decode_OP_VOP1__V_CEIL_F32(MachInst)
Definition: decoder.cc:9352
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:4155
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:9856
Gcn3ISA::Inst_VOP3__V_MED3_U32
Definition: instructions.hh:54650
Gcn3ISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I8
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I8(MachInst)
Definition: decoder.cc:8692
Gcn3ISA::Inst_VOP3__V_CUBETC_F32
Definition: instructions.hh:53354
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_AND_X2
Definition: instructions.hh:81328
Gcn3ISA::Inst_VOPC__V_CMPX_GE_F16
Definition: instructions.hh:21220
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Definition: instructions.hh:81130
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8176
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:4449
Gcn3ISA::Inst_MIMG__IMAGE_GET_RESINFO
Definition: instructions.hh:73374
Gcn3ISA::InFmt_SOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1509
Gcn3ISA::Inst_VOP1__V_FLOOR_F32
Definition: instructions.hh:16848
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LDEXP_F16
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F16(MachInst)
Definition: decoder.cc:5409
Gcn3ISA::Inst_DS__DS_MIN_RTN_U64
Definition: instructions.hh:63696
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:9970
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CNDMASK_B32
GPUStaticInst * decode_OPU_VOP3__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:5127
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LDEXP_F64
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F64(MachInst)
Definition: decoder.cc:6207
Gcn3ISA::Inst_SOP2__S_RFE_RESTORE_B64
Definition: instructions.hh:2884
Gcn3ISA::Decoder::subDecode_OP_SOP1
GPUStaticInst * subDecode_OP_SOP1(MachInst)
Definition: decoder.cc:3149
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I16
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:5367
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst)
Definition: decoder.cc:7683
Gcn3ISA::Decoder::decode_OP_SOP1__S_FF0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B64(MachInst)
Definition: decoder.cc:8650
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMIN
Definition: instructions.hh:80196
Gcn3ISA::Inst_DS__DS_OR_B64
Definition: instructions.hh:62624
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:5439
Gcn3ISA::Inst_VOPC__V_CMPX_GE_I16
Definition: instructions.hh:27356
Gcn3ISA::Inst_VOP3__V_ASHRREV_I32
Definition: instructions.hh:46466
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:4995
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:7305
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B32(MachInst)
Definition: decoder.cc:6567
Gcn3ISA::Inst_VOP2__V_ADD_F16
Definition: instructions.hh:13602
Gcn3ISA::Inst_VOPC__V_CMP_GT_F16
Definition: instructions.hh:20060
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:5787
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:7281
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:4875
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:10684
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8055
Gcn3ISA::Inst_DS__DS_MIN_SRC2_I64
Definition: instructions.hh:66462
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:9622
Gcn3ISA::Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK
GPUStaticInst * decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst)
Definition: decoder.cc:3909
Gcn3ISA::Decoder::decode_OP_VOP2__V_MADAK_F32
GPUStaticInst * decode_OP_VOP2__V_MADAK_F32(MachInst)
Definition: decoder.cc:3381
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:4143
Gcn3ISA::Inst_VOP3__V_CMPX_LT_U32
Definition: instructions.hh:42764
Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_I32
GPUStaticInst * decode_OP_SOP2__S_BFE_I32(MachInst)
Definition: decoder.cc:3777
Gcn3ISA::Inst_SOP2__S_ASHR_I32
Definition: instructions.hh:2158
Gcn3ISA::Decoder::decode_OP_VOP1__V_CEIL_F16
GPUStaticInst * decode_OP_VOP1__V_CEIL_F16(MachInst)
Definition: decoder.cc:9574
Gcn3ISA::Inst_SOPC__S_CMP_EQ_U32
Definition: instructions.hh:7504
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8296
Gcn3ISA::Inst_MUBUF__BUFFER_WBINVL1
Definition: instructions.hh:69538
Gcn3ISA::Inst_DS__DS_AND_SRC2_B32
Definition: instructions.hh:65292
Gcn3ISA::Inst_VOP1__V_RSQ_F32
Definition: instructions.hh:17148
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D_CL
Definition: instructions.hh:74514
Gcn3ISA::Inst_VOP1__V_RCP_F32
Definition: instructions.hh:17028
Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F32
Definition: instructions.hh:36494
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8110
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:10336
Gcn3ISA::Inst_VOPC__V_CMP_GT_I16
Definition: instructions.hh:26192
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAC_F32
GPUStaticInst * decode_OP_VOP2__V_MAC_F32(MachInst)
Definition: decoder.cc:3369
Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET0_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B32(MachInst)
Definition: decoder.cc:8704
Gcn3ISA::Inst_VOP3__V_CMPX_GE_F32
Definition: instructions.hh:36230
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_I32(MachInst)
Definition: decoder.cc:3837
Gcn3ISA::Inst_VOP3__V_CMP_NLE_F64
Definition: instructions.hh:37682
Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U64(MachInst)
Definition: decoder.cc:7089
Gcn3ISA::Inst_VOP3__V_PERM_B32
Definition: instructions.hh:56192
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst)
Definition: decoder.cc:7707
Gcn3ISA::Inst_DS__DS_MIN_SRC2_F64
Definition: instructions.hh:66894
Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I32_F32
Definition: instructions.hh:51554
Gcn3ISA::Inst_VOP3__V_CMP_T_U16
Definition: instructions.hh:39992
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN_U32(MachInst)
Definition: decoder.cc:5211
Gcn3ISA::Inst_VOP3__V_CMP_GT_F16
Definition: instructions.hh:32930
Gcn3ISA::Inst_DS__DS_AND_SRC2_B64
Definition: instructions.hh:66678
Gcn3ISA::Inst_VOP3__V_MIN_F64
Definition: instructions.hh:57042
Gcn3ISA::Inst_VOP3__V_CMPX_GE_I32
Definition: instructions.hh:42566
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_F64
GPUStaticInst * decode_OPU_VOP3__V_ADD_F64(MachInst)
Definition: decoder.cc:6183
Gcn3ISA::Decoder::decode_OP_VOP1__V_FFBH_U32
GPUStaticInst * decode_OP_VOP1__V_FFBH_U32(MachInst)
Definition: decoder.cc:9448
Gcn3ISA::Inst_VOP3__V_CMP_GT_I16
Definition: instructions.hh:39266
Gcn3ISA::Inst_VOP2__V_MADMK_F16
Definition: instructions.hh:13932
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_U64
GPUStaticInst * decode_OP_DS__DS_MAX_U64(MachInst)
Definition: decoder.cc:6711
Gcn3ISA::Inst_VOP2__V_ADD_U32
Definition: instructions.hh:13152
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:5115
Gcn3ISA::Inst_VOP3__V_MED3_F32
Definition: instructions.hh:54506
Gcn3ISA::Inst_VOP3__V_COS_F16
Definition: instructions.hh:52742
Gcn3ISA::Inst_VOP3__V_MUL_U32_U24
Definition: instructions.hh:45872
Gcn3ISA::Decoder::tableSubDecode_OP_VOP1
static IsaDecodeMethod tableSubDecode_OP_VOP1[256]
Definition: gpu_decoder.hh:75
Gcn3ISA::Inst_VOP3__V_SUB_F32
Definition: instructions.hh:45476
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:10270
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B_CL_O
Definition: instructions.hh:75882
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U64(MachInst)
Definition: decoder.cc:10666
Gcn3ISA::Inst_VOP2__V_MUL_U32_U24
Definition: instructions.hh:12030
Gcn3ISA::Inst_VOPC__V_CMP_NE_U64
Definition: instructions.hh:30882
Gcn3ISA::Inst_DS__DS_ORDERED_COUNT
Definition: instructions.hh:66132
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_L
Definition: instructions.hh:74586
Gcn3ISA::Inst_SOP2__S_NOR_B64
Definition: instructions.hh:1696
Gcn3ISA::Decoder::decode_OP_SOP2__S_OR_B32
GPUStaticInst * decode_OP_SOP2__S_OR_B32(MachInst)
Definition: decoder.cc:3633
Gcn3ISA::Inst_VOP3__V_MED3_I32
Definition: instructions.hh:54578
Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_B32(MachInst)
Definition: decoder.cc:6399
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_F64
GPUStaticInst * decode_OPU_VOP3__V_MAX_F64(MachInst)
Definition: decoder.cc:6201
Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F64
Definition: instructions.hh:51434
Gcn3ISA::Inst_VOP3__V_MBCNT_LO_U32_B32
Definition: instructions.hh:57702
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:5847
Gcn3ISA::Inst_VOP1__V_SIN_F32
Definition: instructions.hh:17448
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F64_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:5505
Gcn3ISA::Inst_SOP1__S_FLBIT_I32_B32
Definition: instructions.hh:5230
Gcn3ISA::Decoder::decode_OP_VINTRP__V_INTERP_P1_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:9160
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_F16
GPUStaticInst * decode_OPU_VOP3__V_RCP_F16(MachInst)
Definition: decoder.cc:5757
Gcn3ISA::Inst_DS__DS_WRITE_B128
Definition: instructions.hh:67062
Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F32
Definition: instructions.hh:36560
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:4161
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst)
Definition: decoder.cc:7821
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8164
Gcn3ISA::Inst_VOP3__V_CMP_NE_U64
Definition: instructions.hh:44084
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I24(MachInst)
Definition: decoder.cc:5865
Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F16
Definition: instructions.hh:34580
Gcn3ISA::Inst_VOP3__V_FRACT_F16
Definition: instructions.hh:52622
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:10102
Gcn3ISA::Decoder::decode_OP_SOPK__S_SETREG_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_B32(MachInst)
Definition: decoder.cc:3921
Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK
Definition: instructions.hh:72966
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I16(MachInst)
Definition: decoder.cc:4593
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst)
Definition: decoder.cc:7545
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SWAP
Definition: instructions.hh:73440
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMAX
Definition: instructions.hh:80328
Gcn3ISA::Inst_VOP3__V_BFREV_B32
Definition: instructions.hh:51134
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:4437
Gcn3ISA::Inst_VOP3__V_SUBBREV_U32
Definition: instructions.hh:47234
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SQRT_F16
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F16(MachInst)
Definition: decoder.cc:5763
Gcn3ISA::Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK
GPUStaticInst * decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst)
Definition: decoder.cc:3795
Gcn3ISA::Inst_VOPC__V_CMPX_GE_F32
Definition: instructions.hh:23264
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:10504
Gcn3ISA::Decoder::decode_OP_VOP2__V_OR_B32
GPUStaticInst * decode_OP_VOP2__V_OR_B32(MachInst)
Definition: decoder.cc:3357
Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F32
Definition: instructions.hh:23698
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst)
Definition: decoder.cc:6063
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL
Definition: instructions.hh:77322
Gcn3ISA::Inst_VOP1__V_FLOOR_F16
Definition: instructions.hh:18876
Gcn3ISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64
Definition: instructions.hh:6304
Gcn3ISA::Inst_DS__DS_SUB_SRC2_U64
Definition: instructions.hh:66246
Gcn3ISA::Inst_VOP3__V_CMPX_LG_F64
Definition: instructions.hh:38276
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:10204
Gcn3ISA::Decoder::decode_OP_VOP1__V_FLOOR_F64
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F64(MachInst)
Definition: decoder.cc:9334
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:5529
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FLOOR_F32
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F32(MachInst)
Definition: decoder.cc:5595
instructions.hh
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC
Definition: instructions.hh:80658
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN_F32(MachInst)
Definition: decoder.cc:5187
Gcn3ISA::Inst_VOPC__V_CMP_GE_U16
Definition: instructions.hh:26852
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:5085
Gcn3ISA::Inst_VOP1__V_TRUNC_F64
Definition: instructions.hh:16368
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_U32(MachInst)
Definition: decoder.cc:6369
Gcn3ISA::Inst_VOPC__V_CMPX_GE_I32
Definition: instructions.hh:29404
Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:8440
Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8
Definition: instructions.hh:10520
Gcn3ISA::Inst_SOPP__S_SET_GPR_IDX_MODE
Definition: instructions.hh:9922
Gcn3ISA::Decoder::Decoder
Decoder()
Definition: decoder.cc:46
Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_F64
GPUStaticInst * decode_OP_VOP1__V_RCP_F64(MachInst)
Definition: decoder.cc:9400
Gcn3ISA::Inst_DS__DS_CMPST_RTN_F32
Definition: instructions.hh:61072
Gcn3ISA::Inst_VOP2__V_ADD_F32
Definition: instructions.hh:11568
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:9844
Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP1_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B32(MachInst)
Definition: decoder.cc:8938
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:9994
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:5031
Gcn3ISA::Inst_VOPC__V_CMP_GE_F64
Definition: instructions.hh:24280
Gcn3ISA::Inst_VOP3__V_WRITELANE_B32
Definition: instructions.hh:57570
Gcn3ISA::Inst_SMEM__S_DCACHE_INV
Definition: instructions.hh:11064
Gcn3ISA::Inst_VOP3__V_CMP_GE_U16
Definition: instructions.hh:39926
Gcn3ISA::Inst_DS__DS_CMPST_RTN_B32
Definition: instructions.hh:61006
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C
Definition: instructions.hh:77034
Gcn3ISA::Decoder::decode_OP_VOP1__V_COS_F16
GPUStaticInst * decode_OP_VOP1__V_COS_F16(MachInst)
Definition: decoder.cc:9604
Gcn3ISA::Decoder::decode_OP_VOP1__V_TRUNC_F16
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F16(MachInst)
Definition: decoder.cc:9580
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMIN
Definition: instructions.hh:80262
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN_I32(MachInst)
Definition: decoder.cc:5199
Gcn3ISA::Inst_VOPC__V_CMP_NLG_F16
Definition: instructions.hh:20456
Gcn3ISA::Inst_VOP2__V_ADDC_U32
Definition: instructions.hh:13368
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F16_I16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:5739
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:5175
Gcn3ISA::Inst_VOPC__V_CMP_GE_I64
Definition: instructions.hh:30420
Gcn3ISA::Inst_DS__DS_MIN_SRC2_U32
Definition: instructions.hh:65184
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:10006
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:4347
Gcn3ISA::Inst_DS__DS_WRXCHG_RTN_B32
Definition: instructions.hh:60808
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:4095
Gcn3ISA::Inst_VOP2__V_MUL_HI_U32_U24
Definition: instructions.hh:12096
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U32(MachInst)
Definition: decoder.cc:6213
Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORD
Definition: instructions.hh:79676
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:4695
Gcn3ISA::Decoder::decode_OP_VOP2__V_MADMK_F32
GPUStaticInst * decode_OP_VOP2__V_MADMK_F32(MachInst)
Definition: decoder.cc:3375
Gcn3ISA::Inst_VOP3__V_CMP_GE_F64
Definition: instructions.hh:37286
Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B32(MachInst)
Definition: decoder.cc:8632
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:10582
Gcn3ISA::InFmt_VOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1537
gpu_static_inst.hh
Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F32
Definition: instructions.hh:23822
Gcn3ISA::Inst_DS__DS_SUB_SRC2_U32
Definition: instructions.hh:64860
Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHR_B64
GPUStaticInst * decode_OP_SOP2__S_LSHR_B64(MachInst)
Definition: decoder.cc:3735
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst)
Definition: decoder.cc:7623
Gcn3ISA::Decoder::tableSubDecode_OP_DS
static IsaDecodeMethod tableSubDecode_OP_DS[256]
Definition: gpu_decoder.hh:65
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Definition: instructions.hh:80794
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:80860
Gcn3ISA::Inst_VOP3__V_CVT_F32_I32
Definition: instructions.hh:48794
Gcn3ISA::Inst_DS__DS_RSUB_SRC2_U32
Definition: instructions.hh:64914
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:10552
Gcn3ISA::Decoder::tableSubDecode_OP_SOP1
static IsaDecodeMethod tableSubDecode_OP_SOP1[256]
Definition: gpu_decoder.hh:71
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP(MachInst)
Definition: decoder.cc:7473
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:5619
Gcn3ISA::Inst_VOP3__V_CMP_GE_I64
Definition: instructions.hh:43622
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:4071
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:10162
Gcn3ISA::Inst_VOPC__V_CMPX_LG_F64
Definition: instructions.hh:25246
Gcn3ISA::Inst_SMEM__S_MEMREALTIME
Definition: instructions.hh:11310
Gcn3ISA::Inst_SOP1__S_SEXT_I32_I8
Definition: instructions.hh:5470
Gcn3ISA::Decoder::decode_OP_SOPP__S_ENDPGM
GPUStaticInst * decode_OP_SOPP__S_ENDPGM(MachInst)
Definition: decoder.cc:8986
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst)
Definition: decoder.cc:7515
Gcn3ISA::Inst_DS__DS_GWS_SEMA_BR
Definition: instructions.hh:65838
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAC_F32
GPUStaticInst * decode_OPU_VOP3__V_MAC_F32(MachInst)
Definition: decoder.cc:5259
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:5475
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:10360
Gcn3ISA::Inst_DS__DS_RSUB_U64
Definition: instructions.hh:62144
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:10414
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I16(MachInst)
Definition: decoder.cc:10234
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:9694
Gcn3ISA::Inst_VOP1__V_CVT_F32_I32
Definition: instructions.hh:15288
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SUB
Definition: instructions.hh:73638
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:9712
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I32(MachInst)
Definition: decoder.cc:10426
Gcn3ISA::Inst_VOPC__V_CMP_TRU_F32
Definition: instructions.hh:22830
Gcn3ISA::Decoder::tableSubDecode_OP_MTBUF
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16]
Definition: gpu_decoder.hh:68
Gcn3ISA::Inst_VOP3__V_SUB_U16
Definition: instructions.hh:47708
Gcn3ISA::Inst_SOPP__S_SENDMSGHALT
Definition: instructions.hh:9274
Gcn3ISA::Inst_SOP2__S_LSHR_B64
Definition: instructions.hh:2092
Gcn3ISA::Decoder::decode_OP_DS__DS_INC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U32(MachInst)
Definition: decoder.cc:6489
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_F64
GPUStaticInst * decode_OPU_VOP3__V_MIN_F64(MachInst)
Definition: decoder.cc:6195
Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F32
Definition: instructions.hh:23636
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:10156
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SMAX
Definition: instructions.hh:73836
Gcn3ISA::Inst_VOP3__V_CMPX_LT_I32
Definition: instructions.hh:42236
Gcn3ISA::Inst_DS__DS_MIN_U32
Definition: instructions.hh:58914
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst)
Definition: decoder.cc:7881
Gcn3ISA::Inst_SOP1__S_MOVRELD_B64
Definition: instructions.hh:6844
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELD_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B32(MachInst)
Definition: decoder.cc:8824
Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F64
Definition: instructions.hh:38672
Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F64
Definition: instructions.hh:38738
Gcn3ISA::Inst_VOP3__V_ADD_F16
Definition: instructions.hh:47312
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:9772
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4
Definition: instructions.hh:76602
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8356
Gcn3ISA::InFmt_MTBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1439
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:4077
Gcn3ISA::Inst_SOP2__S_XNOR_B32
Definition: instructions.hh:1762
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8362
Gcn3ISA::Inst_VOP3__V_CMPX_LT_F32
Definition: instructions.hh:35900
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX_F16(MachInst)
Definition: decoder.cc:5373
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_LO_U16
GPUStaticInst * decode_OP_VOP2__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:3483
Gcn3ISA::Inst_VOP3__V_CMP_T_I16
Definition: instructions.hh:39464
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_LZ
Definition: instructions.hh:74802
Gcn3ISA::Decoder::decode_OP_SOP2__S_ORN2_B32
GPUStaticInst * decode_OP_SOP2__S_ORN2_B32(MachInst)
Definition: decoder.cc:3669
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U16(MachInst)
Definition: decoder.cc:10324
Gcn3ISA::Inst_DS__DS_DEC_RTN_U32
Definition: instructions.hh:60214
Gcn3ISA::Decoder::decode_OP_SOP1__S_BREV_B32
GPUStaticInst * decode_OP_SOP1__S_BREV_B32(MachInst)
Definition: decoder.cc:8608
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
Definition: instructions.hh:78186
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMAX
Definition: instructions.hh:80394
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:4035
Gcn3ISA::Inst_VOP2__V_SUBREV_U32
Definition: instructions.hh:13296
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst)
Definition: decoder.cc:7263
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst)
Definition: decoder.cc:7635
Gcn3ISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I16
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I16(MachInst)
Definition: decoder.cc:8698
Gcn3ISA::Inst_DS__DS_WRITE2_B32
Definition: instructions.hh:59336
Gcn3ISA::Decoder::decode_invalid
GPUStaticInst * decode_invalid(MachInst)
Definition: decoder.cc:10810
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_UBYTE
Definition: instructions.hh:68426
Gcn3ISA::Inst_DS__DS_MIN_SRC2_U64
Definition: instructions.hh:66570
Gcn3ISA::Inst_VOP3__V_MQSAD_PK_U16_U8
Definition: instructions.hh:55676
Gcn3ISA::Inst_VOP3__V_CMP_NGT_F32
Definition: instructions.hh:35504
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst)
Definition: decoder.cc:7647
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:9988
Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B64(MachInst)
Definition: decoder.cc:8626
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst)
Definition: decoder.cc:7269
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:9838
Gcn3ISA::Inst_DS__DS_CMPST_RTN_F64
Definition: instructions.hh:64356
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:10408
Gcn3ISA::Decoder::decode_OP_SOPP__S_TTRACEDATA
GPUStaticInst * decode_OP_SOPP__S_TTRACEDATA(MachInst)
Definition: decoder.cc:9112
Gcn3ISA::Decoder::decode_OP_DS__DS_INC_U64
GPUStaticInst * decode_OP_DS__DS_INC_U64(MachInst)
Definition: decoder.cc:6681
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst)
Definition: decoder.cc:7857
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:4683
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:5523
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:5091
Gcn3ISA::Inst_SOP1__S_BCNT1_I32_B64
Definition: instructions.hh:4930
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U64(MachInst)
Definition: decoder.cc:4983
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:8308
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:10180
Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F16
Definition: instructions.hh:21468
Gcn3ISA::Inst_DS__DS_CMPST_RTN_B64
Definition: instructions.hh:64290
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32(MachInst)
Definition: decoder.cc:6219
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:9832
Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX4
Definition: instructions.hh:79862
Gcn3ISA::Inst_VOPC__V_CMP_NE_U16
Definition: instructions.hh:26786
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:8314
Gcn3ISA::Inst_VOPC__V_CMPX_NE_U16
Definition: instructions.hh:27790
Gcn3ISA::Inst_VOP3__V_NOP
Definition: instructions.hh:48566
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:10348
Gcn3ISA::Decoder::decode_OP_VOP1__V_NOT_B32
GPUStaticInst * decode_OP_VOP1__V_NOT_B32(MachInst)
Definition: decoder.cc:9436
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:9886
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst)
Definition: decoder.cc:7845
Gcn3ISA::Decoder::tableSubDecode_OP_SOPC
static IsaDecodeMethod tableSubDecode_OP_SOPC[128]
Definition: gpu_decoder.hh:72
Gcn3ISA::Inst_VOPC__V_CMPX_LT_I32
Definition: instructions.hh:29094
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_XOR
Definition: instructions.hh:74100
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_L_O
Definition: instructions.hh:75738
Gcn3ISA::Inst_VOP3__V_SAD_U32
Definition: instructions.hh:54938
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:10372
Gcn3ISA::Inst_VOP3__V_CMP_NE_U16
Definition: instructions.hh:39860
Gcn3ISA::Inst_VOPC__V_CMPX_LT_F32
Definition: instructions.hh:22954
Gcn3ISA::Inst_DS__DS_SUB_U64
Definition: instructions.hh:62084
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SUB
Definition: instructions.hh:69854
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:10702
Gcn3ISA::Inst_SOP2__S_ASHR_I64
Definition: instructions.hh:2224
Gcn3ISA::InFmt_SOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1493
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:72028
Gcn3ISA::Inst_VOP3__V_CMP_NLG_F64
Definition: instructions.hh:37550
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U32(MachInst)
Definition: decoder.cc:6975
Gcn3ISA::Decoder::decode_OP_DS__DS_INC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U64(MachInst)
Definition: decoder.cc:7095
Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
Definition: instructions.hh:9706
Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_U64
GPUStaticInst * decode_OP_DS__DS_SUB_U64(MachInst)
Definition: decoder.cc:6669
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst)
Definition: decoder.cc:6057
Gcn3ISA::Inst_SOP2__S_OR_B64
Definition: instructions.hh:1036
Gcn3ISA::Decoder::decode_OP_SMEM__S_MEMREALTIME
GPUStaticInst * decode_OP_SMEM__S_MEMREALTIME(MachInst)
Definition: decoder.cc:8542
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst)
Definition: decoder.cc:7329
Gcn3ISA::Inst_VOPC__V_CMP_TRU_F16
Definition: instructions.hh:20786
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LG_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_I32(MachInst)
Definition: decoder.cc:8866
Gcn3ISA::Inst_DS__DS_ADD_RTN_F32
Definition: instructions.hh:61336
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORD(MachInst)
Definition: decoder.cc:7251
Gcn3ISA::InstFormat::iFmt_MIMG
InFmt_MIMG iFmt_MIMG
Definition: gpu_decoder.hh:1620
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_I32(MachInst)
Definition: decoder.cc:6357
Gcn3ISA::Inst_SOP1__S_QUADMASK_B32
Definition: instructions.hh:6544
Gcn3ISA::Inst_SOP1__S_RFE_B64
Definition: instructions.hh:6004
Gcn3ISA::Decoder::decode_OP_SOP1__S_FF1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B64(MachInst)
Definition: decoder.cc:8662
Gcn3ISA::Inst_VOP3__V_CVT_U16_F16
Definition: instructions.hh:51842
Gcn3ISA::Inst_DS__DS_INC_RTN_U32
Definition: instructions.hh:60148
Gcn3ISA::Inst_VOP3__V_ADD_F32
Definition: instructions.hh:45410
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst)
Definition: decoder.cc:5943
Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F64
Definition: instructions.hh:25866
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBB_U32
GPUStaticInst * decode_OP_VOP2__V_SUBB_U32(MachInst)
Definition: decoder.cc:3411
Gcn3ISA::InFmt_FLAT
Definition: gpu_decoder.hh:1390
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:10342
Gcn3ISA::Inst_SOPP__S_INCPERFLEVEL
Definition: instructions.hh:9436
Gcn3ISA::Inst_SOPC__S_SET_GPR_IDX_ON
Definition: instructions.hh:8164
Gcn3ISA::Inst_SOP1__S_MOV_FED_B32
Definition: instructions.hh:7024
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F64(MachInst)
Definition: decoder.cc:10042
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:4173
Gcn3ISA::Inst_SOP1__S_QUADMASK_B64
Definition: instructions.hh:6604
Gcn3ISA::Decoder::decode_OP_SOP2__S_BFM_B32
GPUStaticInst * decode_OP_SOP2__S_BFM_B32(MachInst)
Definition: decoder.cc:3753
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:10420
Gcn3ISA::Inst_VOP3__V_CMPX_NE_U16
Definition: instructions.hh:40916
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_DEC
Definition: instructions.hh:70502
Gcn3ISA::Inst_SOP1__S_FF1_I32_B32
Definition: instructions.hh:5110
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B16
GPUStaticInst * decode_OP_DS__DS_WRITE_B16(MachInst)
Definition: decoder.cc:6465
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8260
Gcn3ISA::Inst_DS__DS_MIN_RTN_F64
Definition: instructions.hh:64422
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst)
Definition: decoder.cc:6033
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE(MachInst)
Definition: decoder.cc:7239
Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F32
Definition: instructions.hh:32336
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst)
Definition: decoder.cc:7551
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8404
Gcn3ISA::Decoder::decode_OP_VOP2__V_MADMK_F16
GPUStaticInst * decode_OP_VOP2__V_MADMK_F16(MachInst)
Definition: decoder.cc:3453
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8236
Gcn3ISA::Decoder::decode_OP_SOPP__S_WAKEUP
GPUStaticInst * decode_OP_SOPP__S_WAKEUP(MachInst)
Definition: decoder.cc:8998
Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_F32
GPUStaticInst * decode_OP_VOP2__V_MIN_F32(MachInst)
Definition: decoder.cc:3297
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC_X2
Definition: instructions.hh:81526
Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX3
Definition: instructions.hh:79428
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_I32(MachInst)
Definition: decoder.cc:8890
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U64(MachInst)
Definition: decoder.cc:7077
Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F32
Definition: instructions.hh:51614
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:5511
Gcn3ISA::InFmt_DS
Definition: gpu_decoder.hh:1357
Gcn3ISA::Inst_DS__DS_MIN_RTN_I64
Definition: instructions.hh:63564
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:10258
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:9766
Gcn3ISA::Inst_VOP3__V_DIV_FMAS_F32
Definition: instructions.hh:55382
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_AND_X2
Definition: instructions.hh:71150
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:4773
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U32(MachInst)
Definition: decoder.cc:5277
Gcn3ISA::Inst_VOP3__V_LDEXP_F16
Definition: instructions.hh:48500
Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_B64
GPUStaticInst * decode_OP_DS__DS_XOR_B64(MachInst)
Definition: decoder.cc:6729
Gcn3ISA::Inst_VOP1__V_LOG_F32
Definition: instructions.hh:16968
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:4491
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:10288
Gcn3ISA::Inst_VOP1__V_CVT_U16_F16
Definition: instructions.hh:18336
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:4059
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:4251
Gcn3ISA::Inst_DS__DS_MAX_U32
Definition: instructions.hh:58974
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst)
Definition: decoder.cc:7293
Gcn3ISA::Inst_VOP2__V_MUL_I32_I24
Definition: instructions.hh:11898
Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F64
Definition: instructions.hh:38540
Gcn3ISA::Inst_VOP3__V_LSHLREV_B16
Definition: instructions.hh:47906
Gcn3ISA::Inst_VOP3__V_MUL_I32_I24
Definition: instructions.hh:45740
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:5223
Gcn3ISA::Inst_VOPC__V_CMP_LG_F16
Definition: instructions.hh:20126
Gcn3ISA::Inst_VOP3__V_TRUNC_F64
Definition: instructions.hh:49874
Gcn3ISA::Inst_VOPC__V_CMP_O_F32
Definition: instructions.hh:22302
Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE1
Definition: instructions.hh:16068
Gcn3ISA::Inst_VOPC__V_CMP_NE_U32
Definition: instructions.hh:28834
Gcn3ISA::Inst_VOP3__V_FMA_F64
Definition: instructions.hh:53786
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U32(MachInst)
Definition: decoder.cc:3399
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:10726
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:10066
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst)
Definition: decoder.cc:7677
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:10558
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELS_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B64(MachInst)
Definition: decoder.cc:8818
Gcn3ISA::Decoder::subDecode_OP_MUBUF
GPUStaticInst * subDecode_OP_MUBUF(MachInst)
Definition: decoder.cc:3213
Gcn3ISA::Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8788
Gcn3ISA::Inst_VOP3__V_CVT_F32_U32
Definition: instructions.hh:48854
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:4821
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_U32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:9220
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_F32(MachInst)
Definition: decoder.cc:5859
Gcn3ISA::Decoder::decode_OP_SOP2__S_XOR_B64
GPUStaticInst * decode_OP_SOP2__S_XOR_B64(MachInst)
Definition: decoder.cc:3651
Gcn3ISA::Inst_VOP3__V_CMP_NGE_F16
Definition: instructions.hh:33260
Gcn3ISA::Decoder::decode_OP_SOP2__S_SUB_U32
GPUStaticInst * decode_OP_SOP2__S_SUB_U32(MachInst)
Definition: decoder.cc:3555
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U64
Definition: instructions.hh:31700
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:10534
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst)
Definition: decoder.cc:7569
Gcn3ISA::Inst_VOP3__V_READLANE_B32
Definition: instructions.hh:57504
Gcn3ISA::Inst_DS__DS_INC_SRC2_U32
Definition: instructions.hh:64968
Gcn3ISA::Inst_VOP3__V_SAD_U16
Definition: instructions.hh:54866
Gcn3ISA::Inst_VOP3__V_LSHRREV_B16
Definition: instructions.hh:47972
Gcn3ISA::Inst_VOP3__V_CMP_NE_U32
Definition: instructions.hh:41972
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LOG_F16
GPUStaticInst * decode_OPU_VOP3__V_LOG_F16(MachInst)
Definition: decoder.cc:5775
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:67686
Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B64(MachInst)
Definition: decoder.cc:7143
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:10294
Gcn3ISA::Inst_VOP3__V_CMP_LG_F16
Definition: instructions.hh:32996
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst)
Definition: decoder.cc:7833
Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_F16
GPUStaticInst * decode_OP_VOP2__V_MIN_F16(MachInst)
Definition: decoder.cc:3513
Gcn3ISA::Inst_SOPC__S_CMP_EQ_U64
Definition: instructions.hh:8224
Gcn3ISA::Inst_VOP2__V_SUB_U16
Definition: instructions.hh:14142
Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECNZ
Definition: instructions.hh:8842
Gcn3ISA::Decoder::decode_OPU_VOP3__V_NOT_B32
GPUStaticInst * decode_OPU_VOP3__V_NOT_B32(MachInst)
Definition: decoder.cc:5667
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I32(MachInst)
Definition: decoder.cc:6957
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3
Definition: instructions.hh:68878
Gcn3ISA::Inst_VOP1__V_CVT_F32_U32
Definition: instructions.hh:15348
Gcn3ISA::Decoder::decode_OP_SOP1__S_BITSET0_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B64(MachInst)
Definition: decoder.cc:8710
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOV_FED_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_FED_B32(MachInst)
Definition: decoder.cc:8848
Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F32
Definition: instructions.hh:23760
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X
Definition: instructions.hh:67242
Gcn3ISA::Inst_VOP3__V_INTERP_P1LL_F16
Definition: instructions.hh:56700
Gcn3ISA::Inst_VOP2__V_MUL_F32
Definition: instructions.hh:11832
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:7353
Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F64
Definition: instructions.hh:38870
Gcn3ISA::Decoder::decode_OP_DS__DS_AND_RTN_B64
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B64(MachInst)
Definition: decoder.cc:6837
Gcn3ISA::Inst_DS__DS_ADD_SRC2_F32
Definition: instructions.hh:65616
Gcn3ISA::Decoder::decode_OP_SOP1__S_WQM_B32
GPUStaticInst * decode_OP_SOP1__S_WQM_B32(MachInst)
Definition: decoder.cc:8596
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:10696
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:4671
Gcn3ISA::Decoder::decode_OP_SOP1__S_CBRANCH_JOIN
GPUStaticInst * decode_OP_SOP1__S_CBRANCH_JOIN(MachInst)
Definition: decoder.cc:8836
Gcn3ISA::Inst_SOP1__S_FLBIT_I32_I64
Definition: instructions.hh:5410
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GET_LOD
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_LOD(MachInst)
Definition: decoder.cc:7911
Gcn3ISA::Inst_SOPK__S_SETREG_B32
Definition: instructions.hh:4030
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:10678
Gcn3ISA::Decoder::decode_OP_SMEM__S_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORD(MachInst)
Definition: decoder.cc:8476
Gcn3ISA::Inst_SMEM__S_DCACHE_WB
Definition: instructions.hh:11112
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:5487
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:9244
Gcn3ISA::Decoder::decode_OPU_VOP3__V_EXP_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_F32(MachInst)
Definition: decoder.cc:5601
Gcn3ISA::Inst_SOPP__S_ENDPGM_SAVED
Definition: instructions.hh:9814
Gcn3ISA::Inst_VOPC__V_CMP_F_U16
Definition: instructions.hh:26456
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6081
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:4941
Gcn3ISA::Inst_VOP3__V_CMP_O_F16
Definition: instructions.hh:33128
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst)
Definition: decoder.cc:9022
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:4515
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:4257
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:9796
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:7533
Gcn3ISA::Inst_VOP1__V_FRACT_F32
Definition: instructions.hh:16608
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_AND
Definition: instructions.hh:73968
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:8182
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst)
Definition: decoder.cc:6321
Gcn3ISA::Inst_SOPC__S_BITCMP1_B32
Definition: instructions.hh:7924
Gcn3ISA::Inst_SOPP__S_ENDPGM
Definition: instructions.hh:8398
Gcn3ISA::Inst_VOP3__V_SUBB_U32
Definition: instructions.hh:47156
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:4227
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U64
Definition: instructions.hh:44942
Gcn3ISA::Inst_MIMG__IMAGE_LOAD_PCK
Definition: instructions.hh:72830
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_F16
GPUStaticInst * decode_OPU_VOP3__V_MUL_F16(MachInst)
Definition: decoder.cc:5319
Gcn3ISA::Inst_DS__DS_GWS_SEMA_P
Definition: instructions.hh:65898
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst)
Definition: decoder.cc:7875
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F32(MachInst)
Definition: decoder.cc:6579
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:5457
Gcn3ISA::Inst_SOP1__S_FLBIT_I32_B64
Definition: instructions.hh:5290
Gcn3ISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
Definition: instructions.hh:73034
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst)
Definition: decoder.cc:8212
Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I16_F16
Definition: instructions.hh:18816
Gcn3ISA::Inst_SMEM__S_DCACHE_WB_VOL
Definition: instructions.hh:11208
Gcn3ISA::InstFormat::iFmt_EXP
InFmt_EXP iFmt_EXP
Definition: gpu_decoder.hh:1615
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U32(MachInst)
Definition: decoder.cc:10474
Gcn3ISA::Inst_VOP1__V_COS_F16
Definition: instructions.hh:19236
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:8062
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:4533
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX_I16(MachInst)
Definition: decoder.cc:5391
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:10048
Gcn3ISA::Inst_DS__DS_WRITE_B32
Definition: instructions.hh:59274
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8368
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:5061
Gcn3ISA::Inst_SOP2__S_CSELECT_B64
Definition: instructions.hh:772
Gcn3ISA::Inst_VOP2__V_SUB_F16
Definition: instructions.hh:13668
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst)
Definition: decoder.cc:7629
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:4623
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:4851
Gcn3ISA::Inst_SOPC__S_CMP_EQ_I32
Definition: instructions.hh:7144
Gcn3ISA::Inst_VOPC__V_CMP_LG_F32
Definition: instructions.hh:22170
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B
Definition: instructions.hh:74658
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CEIL_F64
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F64(MachInst)
Definition: decoder.cc:5553
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8019
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:7311
Gcn3ISA::Inst_VOP3__V_MUL_LEGACY_F32
Definition: instructions.hh:45608
Gcn3ISA::Inst_VOP3__V_CMP_NLE_F16
Definition: instructions.hh:33458
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst)
Definition: decoder.cc:7335
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:5019
Gcn3ISA::Inst_VOP1__V_READFIRSTLANE_B32
Definition: instructions.hh:15108
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:10462
Gcn3ISA::Inst_SOPC__S_CMP_LT_U32
Definition: instructions.hh:7744
Gcn3ISA::Decoder::decode_OP_SOPP__S_SLEEP
GPUStaticInst * decode_OP_SOPP__S_SLEEP(MachInst)
Definition: decoder.cc:9064
Gcn3ISA::Inst_VOP3__V_CMP_NGE_F32
Definition: instructions.hh:35372
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_O
Definition: instructions.hh:77466
Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F64
Definition: instructions.hh:55154
Gcn3ISA::Decoder::decode_OP_VOP1__V_FRACT_F16
GPUStaticInst * decode_OP_VOP1__V_FRACT_F16(MachInst)
Definition: decoder.cc:9592
Gcn3ISA::Inst_DS__DS_MAX_SRC2_I32
Definition: instructions.hh:65130
Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F16
Definition: instructions.hh:32534
Gcn3ISA::Inst_VOP1__V_RNDNE_F32
Definition: instructions.hh:16788
Gcn3ISA::Decoder::decode_OP_SOP2__S_XNOR_B64
GPUStaticInst * decode_OP_SOP2__S_XNOR_B64(MachInst)
Definition: decoder.cc:3711
Gcn3ISA::Inst_SOPK__S_CMOVK_I32
Definition: instructions.hh:3010
Gcn3ISA::Inst_VOP3__V_CUBESC_F32
Definition: instructions.hh:53282
Gcn3ISA::Inst_VOP3__V_RNDNE_F16
Definition: instructions.hh:52562
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD(MachInst)
Definition: decoder.cc:7431
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:4725
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8224
Gcn3ISA::Inst_VOP3__V_CMP_LG_F32
Definition: instructions.hh:35108
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F32(MachInst)
Definition: decoder.cc:9898
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_I16
GPUStaticInst * decode_OP_DS__DS_READ_I16(MachInst)
Definition: decoder.cc:6633
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBBREV_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBBREV_U32(MachInst)
Definition: decoder.cc:5295
Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4
Definition: instructions.hh:10996
Gcn3ISA::Inst_SOP2__S_SUBB_U32
Definition: instructions.hh:376
Gcn3ISA::Decoder::decode_OP_VOP1__V_SIN_F32
GPUStaticInst * decode_OP_VOP1__V_SIN_F32(MachInst)
Definition: decoder.cc:9424
Gcn3ISA::Inst_VOP1__V_NOP
Definition: instructions.hh:15000
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:4803
Gcn3ISA::Inst_SOP1__S_BITSET1_B32
Definition: instructions.hh:5710
Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32(MachInst)
Definition: decoder.cc:8680
Gcn3ISA::Inst_DS__DS_READ_U8
Definition: instructions.hh:61648
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:4581
Gcn3ISA::Inst_VOP3__V_CMPX_NE_I16
Definition: instructions.hh:40388
Gcn3ISA::Decoder::decode_OP_VOP1__V_SQRT_F64
GPUStaticInst * decode_OP_VOP1__V_SQRT_F64(MachInst)
Definition: decoder.cc:9418
Gcn3ISA::Inst_DS__DS_MAX_SRC2_F32
Definition: instructions.hh:65562
Gcn3ISA::Inst_VOP2__V_MUL_F16
Definition: instructions.hh:13800
Gcn3ISA::InFmt_VOPC
Definition: gpu_decoder.hh:1575
Gcn3ISA::Inst_DS__DS_MIN_I32
Definition: instructions.hh:58794
Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst)
Definition: decoder.cc:6555
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:7395
Gcn3ISA::InstFormat::iFmt_VOP2
InFmt_VOP2 iFmt_VOP2
Definition: gpu_decoder.hh:1635
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F64(MachInst)
Definition: decoder.cc:6897
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F64(MachInst)
Definition: decoder.cc:6885
Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORD
Definition: instructions.hh:10860
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:9730
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:4197
Gcn3ISA::Inst_SOP1__S_FF1_I32_B64
Definition: instructions.hh:5170
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX_F32(MachInst)
Definition: decoder.cc:5193
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst)
Definition: decoder.cc:7653
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_UMIN
Definition: instructions.hh:73770
Gcn3ISA::Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8758
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:4293
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:4011
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8320
Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:9388
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F64(MachInst)
Definition: decoder.cc:10090
Gcn3ISA::Inst_FLAT__FLAT_LOAD_USHORT
Definition: instructions.hh:79180
Gcn3ISA::Inst_DS__DS_MIN_F32
Definition: instructions.hh:59592
Gcn3ISA::Inst_VOP3__V_CMP_O_F32
Definition: instructions.hh:35240
Gcn3ISA::Decoder::decode_OP_SOPP__S_WAITCNT
GPUStaticInst * decode_OP_SOPP__S_WAITCNT(MachInst)
Definition: decoder.cc:9052
Gcn3ISA::Decoder::tableSubDecode_OP_SMEM
static IsaDecodeMethod tableSubDecode_OP_SMEM[64]
Definition: gpu_decoder.hh:70
Gcn3ISA
classes that represnt vector/scalar operands in GCN3 ISA.
Definition: decoder.cc:44
Gcn3ISA::Inst_VOPC__V_CMP_NE_I64
Definition: instructions.hh:30354
Gcn3ISA::Inst_SOPK__S_CMPK_GT_U32
Definition: instructions.hh:3550
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst)
Definition: decoder.cc:7191
Gcn3ISA::Inst_SOPK__S_CMPK_GE_U32
Definition: instructions.hh:3610
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_DEC
Definition: instructions.hh:74232
Gcn3ISA::Decoder::decode_OP_VOP1__V_RNDNE_F16
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F16(MachInst)
Definition: decoder.cc:9586
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:4419
Gcn3ISA::Inst_VOPC__V_CMP_NLT_F32
Definition: instructions.hh:22764
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2
Definition: instructions.hh:68804
Gcn3ISA::Inst_DS__DS_AND_B64
Definition: instructions.hh:62564
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_CL_O
Definition: instructions.hh:77538
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I64(MachInst)
Definition: decoder.cc:10618
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:68056
Gcn3ISA::Inst_DS__DS_SUB_RTN_U32
Definition: instructions.hh:60016
Gcn3ISA::Inst_VOP3__V_MAX3_U32
Definition: instructions.hh:54434
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:9214
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:8218
Gcn3ISA::Decoder::decode_OP_VOP1__V_FFBL_B32
GPUStaticInst * decode_OP_VOP1__V_FFBL_B32(MachInst)
Definition: decoder.cc:9454
Gcn3ISA::Inst_VOP3__V_CEIL_F32
Definition: instructions.hh:50234
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U24(MachInst)
Definition: decoder.cc:5871
Gcn3ISA::Inst_SOP1__S_MOVRELS_B64
Definition: instructions.hh:6724
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:10498
Gcn3ISA::Decoder::decode_OP_VOP1__V_CEIL_F64
GPUStaticInst * decode_OP_VOP1__V_CEIL_F64(MachInst)
Definition: decoder.cc:9322
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst)
Definition: decoder.cc:7713
Gcn3ISA::Inst_VOP2__V_SUBREV_F32
Definition: instructions.hh:11700
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F16(MachInst)
Definition: decoder.cc:4023
Gcn3ISA::Inst_VOPC__V_CMPX_LE_U32
Definition: instructions.hh:29714
Gcn3ISA::Decoder::tableSubDecode_OP_MIMG
static IsaDecodeMethod tableSubDecode_OP_MIMG[128]
Definition: gpu_decoder.hh:67
Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F16
Definition: instructions.hh:21406
Gcn3ISA::Decoder::decode_OP_VOP1__V_LOG_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_F32(MachInst)
Definition: decoder.cc:9376
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:8104
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U32(MachInst)
Definition: decoder.cc:4791
Gcn3ISA::Inst_DS__DS_WRITE_B16
Definition: instructions.hh:59888
Gcn3ISA::Inst_VOP3__V_CMP_NE_I64
Definition: instructions.hh:43556
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:8092
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_U32(MachInst)
Definition: decoder.cc:8920
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CEIL_F16
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F16(MachInst)
Definition: decoder.cc:5805
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:8494
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:9640
Gcn3ISA::Inst_VOPC__V_CMP_GE_F16
Definition: instructions.hh:20192
Gcn3ISA::Decoder::decode_OP_VOP1__V_LOG_F16
GPUStaticInst * decode_OP_VOP1__V_LOG_F16(MachInst)
Definition: decoder.cc:9544
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_I32(MachInst)
Definition: decoder.cc:3855
Gcn3ISA::Inst_VOP3__V_RSQ_F64
Definition: instructions.hh:50774
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:4113
Gcn3ISA::Inst_SOPK__S_MOVK_I32
Definition: instructions.hh:2950
Gcn3ISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1434
Gcn3ISA::Inst_VOP1__V_RCP_IFLAG_F32
Definition: instructions.hh:17088
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC0
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC0(MachInst)
Definition: decoder.cc:9004
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:10216
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:4917
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:10648
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst)
Definition: decoder.cc:7659
Gcn3ISA::Inst_VOPC__V_CMPX_NE_I16
Definition: instructions.hh:27294
Gcn3ISA::Decoder::decode_OP_DS__DS_READ2_B64
GPUStaticInst * decode_OP_DS__DS_READ2_B64(MachInst)
Definition: decoder.cc:6909
Gcn3ISA::Inst_DS__DS_DEC_U32
Definition: instructions.hh:58734
Gcn3ISA::InFmt_FLAT::OP
unsigned int OP
Definition: gpu_decoder.hh:1394
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_U16
GPUStaticInst * decode_OP_VOP2__V_SUB_U16(MachInst)
Definition: decoder.cc:3471
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_F32
GPUStaticInst * decode_OP_DS__DS_ADD_F32(MachInst)
Definition: decoder.cc:6453
Gcn3ISA::InFmt_SOPC
Definition: gpu_decoder.hh:1506
Gcn3ISA::Inst_VOPC__V_CMPX_F_U64
Definition: instructions.hh:31576
Gcn3ISA::Inst_VOPC__V_CMPX_T_U64
Definition: instructions.hh:32010
Gcn3ISA::Inst_VOP3__V_CMP_T_U64
Definition: instructions.hh:44216
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U32(MachInst)
Definition: decoder.cc:6519
Gcn3ISA::Inst_VOPC__V_CMP_GE_I16
Definition: instructions.hh:26324
Gcn3ISA::Decoder::decode_OP_SOP1__S_RFE_B64
GPUStaticInst * decode_OP_SOP1__S_RFE_B64(MachInst)
Definition: decoder.cc:8746
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_U64_U32
GPUStaticInst * decode_OPU_VOP3__V_MAD_U64_U32(MachInst)
Definition: decoder.cc:6093
Gcn3ISA::Inst_VOP3__V_CMPX_F_U64
Definition: instructions.hh:44810
Gcn3ISA::Inst_VOP3__V_CMP_GE_F16
Definition: instructions.hh:33062
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F16(MachInst)
Definition: decoder.cc:9706
Gcn3ISA::Inst_VOP3__V_CMPX_T_U64
Definition: instructions.hh:45272
Gcn3ISA::Decoder::~Decoder
~Decoder()
Definition: decoder.cc:50
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:9910
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_F32
GPUStaticInst * decode_OP_VOP2__V_MAX_F32(MachInst)
Definition: decoder.cc:3303
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:10756
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:5181
Gcn3ISA::Inst_VOPC__V_CMPX_T_U32
Definition: instructions.hh:29962
Gcn3ISA::Inst_VOP1__V_CVT_RPI_I32_F32
Definition: instructions.hh:15708
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_D_O
Definition: instructions.hh:76170
Gcn3ISA::Inst_DS__DS_INC_U64
Definition: instructions.hh:62204
Gcn3ISA::Inst_VOP3__V_MUL_F32
Definition: instructions.hh:45674
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_O
Definition: instructions.hh:76026
Gcn3ISA::Inst_VOP3__V_CMP_GE_I16
Definition: instructions.hh:39398
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:8043
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst)
Definition: decoder.cc:7257
Gcn3ISA::Decoder::decode_OPU_VOP3__V_AND_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_B32(MachInst)
Definition: decoder.cc:5241
Gcn3ISA::Decoder::decode_OP_SOPP__S_INCPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_INCPERFLEVEL(MachInst)
Definition: decoder.cc:9100
Gcn3ISA::Inst_VOPC__V_CMP_F_I16
Definition: instructions.hh:25928
Gcn3ISA::Decoder::decode_OP_SOPP__S_TRAP
GPUStaticInst * decode_OP_SOPP__S_TRAP(MachInst)
Definition: decoder.cc:9088
Gcn3ISA::Decoder::decode_OP_DS__DS_AND_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B32(MachInst)
Definition: decoder.cc:6981
Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U32(MachInst)
Definition: decoder.cc:6951
Gcn3ISA::Inst_DS__DS_ADD_SRC2_U32
Definition: instructions.hh:64806
Gcn3ISA::Inst_VOP3__V_CMPX_T_U32
Definition: instructions.hh:43160
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B64(MachInst)
Definition: decoder.cc:6267
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:4827
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F64(MachInst)
Definition: decoder.cc:4401
Gcn3ISA::Inst_DS__DS_ADD_RTN_U64
Definition: instructions.hh:63234
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:9250
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:4101
Gcn3ISA::Inst_VOP3__V_MAX3_F32
Definition: instructions.hh:54290
Gcn3ISA::Inst_VOPC__V_CMP_F_F16
Definition: instructions.hh:19796
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:9634
Gcn3ISA::Inst_VOP3__V_CMPX_LE_U32
Definition: instructions.hh:42896
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:10384
Gcn3ISA::Inst_DS__DS_WRITE_SRC2_B32
Definition: instructions.hh:65454
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:10690
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst)
Definition: decoder.cc:7671
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LG_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U64(MachInst)
Definition: decoder.cc:8974
Gcn3ISA::Inst_VOP1__V_CVT_OFF_F32_I4
Definition: instructions.hh:15828
Gcn3ISA::Decoder::decode_OP_DS__DS_APPEND
GPUStaticInst * decode_OP_DS__DS_APPEND(MachInst)
Definition: decoder.cc:7065
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:10390
Gcn3ISA::Inst_VOPC__V_CMPX_F_I64
Definition: instructions.hh:31080
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RNDNE_F32
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F32(MachInst)
Definition: decoder.cc:5589
Gcn3ISA::Inst_VOPC__V_CMPX_T_I64
Definition: instructions.hh:31514
Gcn3ISA::Inst_VOP3__V_MAX3_I32
Definition: instructions.hh:54362
Gcn3ISA::Inst_VOP3__V_MOV_B32
Definition: instructions.hh:48614
Gcn3ISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1455
Gcn3ISA::Decoder::decode_OP_SOP1__S_QUADMASK_B64
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B64(MachInst)
Definition: decoder.cc:8806
Gcn3ISA::Inst_VOP3__V_MIN3_U32
Definition: instructions.hh:54218
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
Definition: instructions.hh:78618
Gcn3ISA::Inst_VOP3__V_CMPX_F_I64
Definition: instructions.hh:44282
Gcn3ISA::Inst_VOP3__V_CMPX_T_I64
Definition: instructions.hh:44744
Gcn3ISA::Inst_VOP3__V_FFBL_B32
Definition: instructions.hh:51254
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_F16
GPUStaticInst * decode_OP_VOP2__V_MAX_F16(MachInst)
Definition: decoder.cc:3507
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F64
Definition: instructions.hh:38078
Gcn3ISA::Inst_DS__DS_AND_RTN_B64
Definition: instructions.hh:63828
Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2
Definition: instructions.hh:10724
Gcn3ISA::Inst_VOPC__V_CMPX_F_F64
Definition: instructions.hh:24936
Gcn3ISA::Inst_VOPC__V_CMPX_T_I32
Definition: instructions.hh:29466
Gcn3ISA::Inst_SOP1__S_BCNT1_I32_B32
Definition: instructions.hh:4870
Gcn3ISA::Inst_VOP3__V_CMPX_F_F64
Definition: instructions.hh:37946
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:4485
Gcn3ISA::Decoder::decode_OP_SOP1__S_CMOV_B32
GPUStaticInst * decode_OP_SOP1__S_CMOV_B32(MachInst)
Definition: decoder.cc:8572
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I64
Definition: instructions.hh:44414
Gcn3ISA::Inst_VOP3__V_SUB_F16
Definition: instructions.hh:47378
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SQRT_F64
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F64(MachInst)
Definition: decoder.cc:5649
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
Definition: instructions.hh:76530
Gcn3ISA::Inst_SOP2__S_BFE_U32
Definition: instructions.hh:2488
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst)
Definition: decoder.cc:7917
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX_U32(MachInst)
Definition: decoder.cc:5217
Gcn3ISA::Inst_VOP3__V_CMPX_T_I32
Definition: instructions.hh:42632
Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B32(MachInst)
Definition: decoder.cc:8668
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:10012
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8506
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_U16
GPUStaticInst * decode_OPU_VOP3__V_SAD_U16(MachInst)
Definition: decoder.cc:6015
Gcn3ISA::Inst_DS__DS_MAX_I32
Definition: instructions.hh:58854
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:5055
Gcn3ISA::Inst_DS__DS_RSUB_SRC2_U64
Definition: instructions.hh:66300
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:10798
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U32(MachInst)
Definition: decoder.cc:8896
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:5043
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:4191
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8500
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst)
Definition: decoder.cc:7719
Gcn3ISA::Inst_VOPC__V_CMP_T_U32
Definition: instructions.hh:28966
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F32(MachInst)
Definition: decoder.cc:7011
Gcn3ISA::Inst_SOPP__S_SET_GPR_IDX_OFF
Definition: instructions.hh:9868
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:4587
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F64(MachInst)
Definition: decoder.cc:10084
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:9670
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:71954
Gcn3ISA::InstFormat::iFmt_VOP3
InFmt_VOP3 iFmt_VOP3
Definition: gpu_decoder.hh:1636
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:10264
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F32(MachInst)
Definition: decoder.cc:4167
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LG_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_I32(MachInst)
Definition: decoder.cc:3831
Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F32
Definition: instructions.hh:36692
Gcn3ISA::Inst_VOP3__V_FRACT_F32
Definition: instructions.hh:50114
Gcn3ISA::Inst_VOP3__V_RNDNE_F64
Definition: instructions.hh:49994
Gcn3ISA::Inst_DS__DS_MAX_F32
Definition: instructions.hh:59652
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_U32(MachInst)
Definition: decoder.cc:3891
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F16(MachInst)
Definition: decoder.cc:3975
Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:9490
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:5007
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F64(MachInst)
Definition: decoder.cc:4359
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_F64
GPUStaticInst * decode_OP_DS__DS_MAX_F64(MachInst)
Definition: decoder.cc:6777
Gcn3ISA::Inst_DS__DS_MAX_SRC2_U32
Definition: instructions.hh:65238
Gcn3ISA::Inst_VOPC__V_CMPX_NE_U64
Definition: instructions.hh:31886
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X
Definition: instructions.hh:67538
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:10654
Gcn3ISA::Inst_VOP3__V_MIN3_F32
Definition: instructions.hh:54074
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_I32(MachInst)
Definition: decoder.cc:3825
Gcn3ISA::Inst_VOP3__V_MUL_F16
Definition: instructions.hh:47510
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_U32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:9304
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:3981
Gcn3ISA::Inst_DS__DS_READ_I16
Definition: instructions.hh:61710
Gcn3ISA::Inst_VOP2__V_LSHLREV_B32
Definition: instructions.hh:12690
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F64
Definition: instructions.hh:25060
Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_F16
GPUStaticInst * decode_OP_VOP2__V_ADD_F16(MachInst)
Definition: decoder.cc:3423
Gcn3ISA::Inst_SOP2__S_BFE_I32
Definition: instructions.hh:2554
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:3939
Gcn3ISA::Inst_SOPP__S_NOP
Definition: instructions.hh:8344
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX_U16(MachInst)
Definition: decoder.cc:5385
Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B64(MachInst)
Definition: decoder.cc:6849
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_RTN_F32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_F32(MachInst)
Definition: decoder.cc:6597
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst)
Definition: decoder.cc:9016
Gcn3ISA::Inst_VOP3__V_MIN3_I32
Definition: instructions.hh:54146
Gcn3ISA::Inst_SOP2__S_ORN2_B32
Definition: instructions.hh:1366
Gcn3ISA::Inst_VOP3__V_NOT_B32
Definition: instructions.hh:51074
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst)
Definition: decoder.cc:7437
Gcn3ISA::Inst_VOPC__V_CMP_U_F16
Definition: instructions.hh:20324
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:10522
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MED3_U32
GPUStaticInst * decode_OPU_VOP3__V_MED3_U32(MachInst)
Definition: decoder.cc:5997
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:5103
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I64
Definition: instructions.hh:31204
Gcn3ISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1526
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B_CL
Definition: instructions.hh:76890
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:4455
Gcn3ISA::Inst_SOPP__S_DECPERFLEVEL
Definition: instructions.hh:9490
Gcn3ISA::Inst_VOP3__V_CMP_NLG_F16
Definition: instructions.hh:33326
Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F16
Definition: instructions.hh:19734
Gcn3ISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64
Definition: instructions.hh:6484
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:10318
Gcn3ISA::Inst_VOPC__V_CMP_NE_I16
Definition: instructions.hh:26258
Gcn3ISA::Inst_VOP2__V_LSHRREV_B32
Definition: instructions.hh:12558
Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_WB
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB(MachInst)
Definition: decoder.cc:8518
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_B
Definition: instructions.hh:76818
Gcn3ISA::Inst_VOP3__V_EXP_F16
Definition: instructions.hh:52202
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst)
Definition: decoder.cc:7491
Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F32
Definition: instructions.hh:36824
Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
Definition: instructions.hh:9760
Gcn3ISA::InFmt_MIMG::OP
unsigned int OP
Definition: gpu_decoder.hh:1420
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_F16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F16(MachInst)
Definition: decoder.cc:5313
Gcn3ISA::Decoder::decode_OP_SOP2__S_ANDN2_B32
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B32(MachInst)
Definition: decoder.cc:3657
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:4179
Gcn3ISA::Inst_DS__DS_READ2_B64
Definition: instructions.hh:64616
Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F64
Definition: instructions.hh:24742
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8152
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
Definition: instructions.hh:71078
Gcn3ISA::Decoder::decode_OPU_VOP3__V_COS_F16
GPUStaticInst * decode_OPU_VOP3__V_COS_F16(MachInst)
Definition: decoder.cc:5835
Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F16
Definition: instructions.hh:21778
Gcn3ISA::Inst_SOPK__S_CMPK_GT_I32
Definition: instructions.hh:3190
Gcn3ISA::Inst_SOPK__S_CMPK_GE_I32
Definition: instructions.hh:3250
Gcn3ISA::Inst_VOP3__V_CMP_NE_I16
Definition: instructions.hh:39332
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:4569
Gcn3ISA::Inst_VOPC__V_CMP_T_U64
Definition: instructions.hh:31014
Gcn3ISA::Inst_SOP1__S_SETPC_B64
Definition: instructions.hh:5884
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC
Definition: instructions.hh:80726
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX3_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I32(MachInst)
Definition: decoder.cc:5973
Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F16
Definition: instructions.hh:21530
Gcn3ISA::Inst_VOP3__V_CVT_F32_F64
Definition: instructions.hh:49394
Gcn3ISA::Inst_VOPC__V_CMPX_LT_U16
Definition: instructions.hh:27542
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8200
Gcn3ISA::Inst_VOP3__V_CMP_T_I64
Definition: instructions.hh:43688
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBESC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBESC_F32(MachInst)
Definition: decoder.cc:5883
Gcn3ISA::Inst_VOP3__V_CMPX_NE_U64
Definition: instructions.hh:45140
Gcn3ISA::InFmt_MUBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1463
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8146
Gcn3ISA::Inst_VOP3__V_BFM_B32
Definition: instructions.hh:58098
Gcn3ISA::Inst_VOP3__V_CMP_TRU_F32
Definition: instructions.hh:35768
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:4659
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_U16
GPUStaticInst * decode_OPU_VOP3__V_SUB_U16(MachInst)
Definition: decoder.cc:5337
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_U16
GPUStaticInst * decode_OPU_VOP3__V_ADD_U16(MachInst)
Definition: decoder.cc:5331
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:5703
Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F32
Definition: instructions.hh:36626
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst)
Definition: decoder.cc:7791
Gcn3ISA::Inst_FLAT__FLAT_LOAD_SSHORT
Definition: instructions.hh:79242
Gcn3ISA::Decoder::decode_OP_DS__DS_WRAP_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRAP_RTN_B32(MachInst)
Definition: decoder.cc:6591
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
Definition: instructions.hh:71880
Gcn3ISA::Inst_VOP1__V_CVT_F32_F64
Definition: instructions.hh:15888
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:10450
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:9268
Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRUNC_F64
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F64(MachInst)
Definition: decoder.cc:5547
Gcn3ISA::Inst_SOPP__S_CBRANCH_SCC1
Definition: instructions.hh:8614
Gcn3ISA::Inst_VOP1__V_CEIL_F32
Definition: instructions.hh:16728
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:9874
Gcn3ISA::Inst_SOP2__S_CSELECT_B32
Definition: instructions.hh:706
Gcn3ISA::Inst_DS__DS_WRXCHG2_RTN_B64
Definition: instructions.hh:64158
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_U32
GPUStaticInst * decode_OPU_VOP3__V_SAD_U32(MachInst)
Definition: decoder.cc:6021
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B(MachInst)
Definition: decoder.cc:7785
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY
Definition: instructions.hh:67612
Gcn3ISA::Inst_DS__DS_XOR_B64
Definition: instructions.hh:62684
Gcn3ISA::Inst_SOPK__S_GETREG_B32
Definition: instructions.hh:3970
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:4323
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D_CL_O
Definition: instructions.hh:75666
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst)
Definition: decoder.cc:7197
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D_O
Definition: instructions.hh:75594
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:5697
Gcn3ISA::Inst_VOP3__V_CMPX_LE_I32
Definition: instructions.hh:42368
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U32(MachInst)
Definition: decoder.cc:6969
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:4845
Gcn3ISA::Decoder::subDecode_OP_MTBUF
GPUStaticInst * subDecode_OP_MTBUF(MachInst)
Definition: decoder.cc:3221
Gcn3ISA::Decoder::subDecode_OP_DS
GPUStaticInst * subDecode_OP_DS(MachInst)
Definition: decoder.cc:3197
Gcn3ISA::Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:9172
Gcn3ISA::Inst_VOPC__V_CMP_EQ_U32
Definition: instructions.hh:28636
Gcn3ISA::Decoder::decode_OP_VOP1__V_EXP_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_F32(MachInst)
Definition: decoder.cc:9370
Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX3
Definition: instructions.hh:79800
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:5469
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8122
Gcn3ISA::Inst_VOP3__V_ASHRREV_I16
Definition: instructions.hh:48038
Gcn3ISA::Inst_VOP3__V_RCP_F64
Definition: instructions.hh:50714
Gcn3ISA::Inst_VOP3__V_CMPX_LE_F32
Definition: instructions.hh:36032
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:8001
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:4503
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADDC_U32
GPUStaticInst * decode_OPU_VOP3__V_ADDC_U32(MachInst)
Definition: decoder.cc:5283
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B32
GPUStaticInst * decode_OP_DS__DS_READ_B32(MachInst)
Definition: decoder.cc:6603
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL
Definition: instructions.hh:75306
Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCNZ
Definition: instructions.hh:8728
Gcn3ISA::Inst_VOP3__V_CMPX_LT_U16
Definition: instructions.hh:40652
Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F64
Definition: instructions.hh:17928
Gcn3ISA::Inst_VOP3__V_CMP_EQ_U32
Definition: instructions.hh:41774
Gcn3ISA::Inst_DS__DS_XOR_RTN_B32
Definition: instructions.hh:60676
Gcn3ISA::Inst_VOPC__V_CMPX_GT_U64
Definition: instructions.hh:31824
Gcn3ISA::Inst_VOP3__V_CVT_I16_F16
Definition: instructions.hh:51902
Gcn3ISA::Decoder::decode_OP_SOP2__S_CSELECT_B32
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B32(MachInst)
Definition: decoder.cc:3609
Gcn3ISA::Decoder::decode_OP_DS__DS_READ2ST64_B64
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B64(MachInst)
Definition: decoder.cc:6915
Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F16
Definition: instructions.hh:34382
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:9934
Gcn3ISA::Inst_VOPC__V_CMP_NE_I32
Definition: instructions.hh:28306
Gcn3ISA::Inst_DS__DS_MAX_RTN_U64
Definition: instructions.hh:63762
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MOV_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_B32(MachInst)
Definition: decoder.cc:5421
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_OR_X2
Definition: instructions.hh:81394
Gcn3ISA::Decoder::decode_OP_DS__DS_OR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B32(MachInst)
Definition: decoder.cc:6987
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FMA_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_F16(MachInst)
Definition: decoder.cc:6129
Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_INV
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV(MachInst)
Definition: decoder.cc:8512
Gcn3ISA::Inst_VOP3__V_CMP_T_U32
Definition: instructions.hh:42104
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:4107
Gcn3ISA::Inst_VOP3__V_SQRT_F32
Definition: instructions.hh:50834
Gcn3ISA::Inst_DS__DS_RSUB_RTN_U32
Definition: instructions.hh:60082
Gcn3ISA::Inst_VOPC__V_CMP_T_I32
Definition: instructions.hh:28438
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:5049
Gcn3ISA::Inst_SOP1__S_MOVRELD_B32
Definition: instructions.hh:6784
Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U64(MachInst)
Definition: decoder.cc:7083
Gcn3ISA::InstFormat::iFmt_SOPK
InFmt_SOPK iFmt_SOPK
Definition: gpu_decoder.hh:1631
Gcn3ISA::Decoder::decode_OP_SOP2__S_ASHR_I32
GPUStaticInst * decode_OP_SOP2__S_ASHR_I32(MachInst)
Definition: decoder.cc:3741
Gcn3ISA::Inst_VOP1__V_CVT_I16_F16
Definition: instructions.hh:18396
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LG_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_U32(MachInst)
Definition: decoder.cc:3867
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_U32(MachInst)
Definition: decoder.cc:3873
Gcn3ISA::Inst_VOP3__V_CMP_NE_I32
Definition: instructions.hh:41444
Gcn3ISA::Decoder::decode_OPU_VOP3__V_NOP
GPUStaticInst * decode_OPU_VOP3__V_NOP(MachInst)
Definition: decoder.cc:5415
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst)
Definition: decoder.cc:7599
Gcn3ISA::Decoder::decode_OP_SOP2__S_NOR_B32
GPUStaticInst * decode_OP_SOP2__S_NOR_B32(MachInst)
Definition: decoder.cc:3693
Gcn3ISA::Inst_MIMG__IMAGE_LOAD
Definition: instructions.hh:72694
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst)
Definition: decoder.cc:7455
Gcn3ISA::Decoder::decode_OP_EXP
GPUStaticInst * decode_OP_EXP(MachInst)
Definition: decoder.cc:3933
Gcn3ISA::Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32
GPUStaticInst * decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst)
Definition: decoder.cc:9190
Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHL_B32
GPUStaticInst * decode_OP_SOP2__S_LSHL_B32(MachInst)
Definition: decoder.cc:3717
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:8080
Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2
Definition: instructions.hh:10384
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:10744
Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:9484
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_CL
Definition: instructions.hh:77106
Gcn3ISA::Inst_VOPC__V_CMPX_LE_I32
Definition: instructions.hh:29218
Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U64(MachInst)
Definition: decoder.cc:6795
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:10192
Gcn3ISA::Decoder::tableSubDecode_OP_VOPC
static IsaDecodeMethod tableSubDecode_OP_VOPC[256]
Definition: gpu_decoder.hh:76
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:9628
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:5067
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst)
Definition: decoder.cc:8206
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:9652
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:7425
Gcn3ISA::InFmt_VOP1
Definition: gpu_decoder.hh:1535
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:7389
Gcn3ISA::Inst_SOP1__S_MOV_B32
Definition: instructions.hh:4150
Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U64(MachInst)
Definition: decoder.cc:6807
Gcn3ISA::Inst_VOP1__V_FFBL_B32
Definition: instructions.hh:17748
Gcn3ISA::Inst_VOPC__V_CMPX_LE_F32
Definition: instructions.hh:23078
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:5715
Gcn3ISA::Decoder::decode_OP_DS__DS_CONSUME
GPUStaticInst * decode_OP_DS__DS_CONSUME(MachInst)
Definition: decoder.cc:7059
Gcn3ISA::Inst_VOP3__V_CMP_TRU_F16
Definition: instructions.hh:33656
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:10714
Gcn3ISA::Decoder::decode_OP_DS__DS_INC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U32(MachInst)
Definition: decoder.cc:6945
GPUStaticInst
Definition: gpu_static_inst.hh:58
Gcn3ISA::Inst_SOP2__S_NAND_B32
Definition: instructions.hh:1498
Gcn3ISA::Decoder::decode_OPU_VOP3__V_READLANE_B32
GPUStaticInst * decode_OPU_VOP3__V_READLANE_B32(MachInst)
Definition: decoder.cc:6237
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:10576
Gcn3ISA::Inst_VOP1__V_BFREV_B32
Definition: instructions.hh:17628
Gcn3ISA::Inst_VOP3__V_CMPX_GT_U64
Definition: instructions.hh:45074
Gcn3ISA::Inst_VOP3__V_SAD_U8
Definition: instructions.hh:54722
Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F64
Definition: instructions.hh:38936
Gcn3ISA::Inst_VOP3__V_CVT_PK_I16_I32
Definition: instructions.hh:58428
Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst)
Definition: decoder.cc:6867
Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2
Definition: instructions.hh:10928
Gcn3ISA::Inst_VOP3__V_MUL_F64
Definition: instructions.hh:56976
Gcn3ISA::Decoder::decode_OP_VOP1__V_SQRT_F16
GPUStaticInst * decode_OP_VOP1__V_SQRT_F16(MachInst)
Definition: decoder.cc:9532
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I32(MachInst)
Definition: decoder.cc:4743
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8158
Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_INIT
GPUStaticInst * decode_OP_DS__DS_GWS_INIT(MachInst)
Definition: decoder.cc:7029
Gcn3ISA::Inst_SOP1__S_BITSET0_B64
Definition: instructions.hh:5650
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_ADD
Definition: instructions.hh:69782
Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE2
Definition: instructions.hh:16128
Gcn3ISA::Inst_SOP1__S_NOT_B64
Definition: instructions.hh:4450
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:8068
Gcn3ISA::Inst_VOP2__V_CNDMASK_B32
Definition: instructions.hh:11496
Gcn3ISA::Inst_MIMG__IMAGE_STORE
Definition: instructions.hh:73102
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U64(MachInst)
Definition: decoder.cc:7119
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SMIN
Definition: instructions.hh:73704
Gcn3ISA::Inst_FLAT__FLAT_LOAD_SBYTE
Definition: instructions.hh:79118
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:9736
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RSQ_F64
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F64(MachInst)
Definition: decoder.cc:5637
Gcn3ISA::Inst_SOPP__S_TRAP
Definition: instructions.hh:9328
Gcn3ISA::Inst_SOPC__S_CMP_LT_I32
Definition: instructions.hh:7384
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:4611
Gcn3ISA::InFmt_VOP3
Definition: gpu_decoder.hh:1550
Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE3
Definition: instructions.hh:16188
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE(MachInst)
Definition: decoder.cc:7575
Gcn3ISA::Inst_VOP1__V_TRUNC_F32
Definition: instructions.hh:16668
Gcn3ISA::Inst_VOPC__V_CMP_T_I64
Definition: instructions.hh:30486
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B96
GPUStaticInst * decode_OP_DS__DS_WRITE_B96(MachInst)
Definition: decoder.cc:7167
Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst)
Definition: decoder.cc:6165
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:5097
Gcn3ISA::Inst_VOP3__V_CMPX_NE_I64
Definition: instructions.hh:44612
Gcn3ISA::InFmt_SOP1
Definition: gpu_decoder.hh:1491
Gcn3ISA::Inst_DS__DS_DEC_U64
Definition: instructions.hh:62264
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:10600
Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_U32
GPUStaticInst * decode_OP_DS__DS_DEC_U32(MachInst)
Definition: decoder.cc:6351
Gcn3ISA::Decoder::decode_OP_VOP1__V_RNDNE_F32
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F32(MachInst)
Definition: decoder.cc:9358
Gcn3ISA::Inst_VOP3__V_MAX_U32
Definition: instructions.hh:46334
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4
Definition: instructions.hh:68952
Gcn3ISA::Inst_VOP3__V_SQRT_F16
Definition: instructions.hh:52022
Gcn3ISA::Decoder::decode_OP_VOP1__V_FLOOR_F16
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F16(MachInst)
Definition: decoder.cc:9568
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:9964
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:9754
Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I32_F32
Definition: instructions.hh:18048
Gcn3ISA::Inst_VOP1__V_RSQ_F64
Definition: instructions.hh:17268
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_I32
GPUStaticInst * decode_OP_VOP2__V_MAX_I32(MachInst)
Definition: decoder.cc:3315
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I16(MachInst)
Definition: decoder.cc:4551
Gcn3ISA::Inst_DS__DS_MIN_RTN_U32
Definition: instructions.hh:60412
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_USHORT
Definition: instructions.hh:68582
Gcn3ISA::Inst_VOP2__V_MUL_LO_U16
Definition: instructions.hh:14274
Gcn3ISA::Inst_VOP3__V_ALIGNBYTE_B32
Definition: instructions.hh:54002
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT(MachInst)
Definition: decoder.cc:7245
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:4971
Gcn3ISA::Inst_VOPC__V_CMPX_U_F16
Definition: instructions.hh:21344
Gcn3ISA::Inst_SOP1__S_NOT_B32
Definition: instructions.hh:4390
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:7221
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_O
Definition: instructions.hh:78834
Gcn3ISA::Inst_VOPC__V_CMP_LT_U64
Definition: instructions.hh:30618
Gcn3ISA::Inst_VOP3__V_CMPX_U_F16
Definition: instructions.hh:34250
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FLOOR_F64
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F64(MachInst)
Definition: decoder.cc:5565
Gcn3ISA::Inst_VOP3__V_CMP_O_F64
Definition: instructions.hh:37352
Gcn3ISA::Inst_DS__DS_READ_I8
Definition: instructions.hh:61588
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:5721
Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F16(MachInst)
Definition: decoder.cc:6177
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SIN_F32
GPUStaticInst * decode_OPU_VOP3__V_SIN_F32(MachInst)
Definition: decoder.cc:5655
Gcn3ISA::Decoder::subDecode_OPU_VOP3
GPUStaticInst * subDecode_OPU_VOP3(MachInst)
Definition: decoder.cc:3181
Gcn3ISA::Decoder::decode_OP_VOP1__V_BFREV_B32
GPUStaticInst * decode_OP_VOP1__V_BFREV_B32(MachInst)
Definition: decoder.cc:9442
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst)
Definition: decoder.cc:7617
Gcn3ISA::Inst_SOPK__S_CMPK_LT_U32
Definition: instructions.hh:3670
Gcn3ISA::InFmt_VOP3::OP
unsigned int OP
Definition: gpu_decoder.hh:1555
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:4737
Gcn3ISA::Inst_VOP3__V_FMA_F32
Definition: instructions.hh:53714
Gcn3ISA::Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst)
Definition: decoder.cc:6921
Gcn3ISA::Inst_SOP2__S_ANDN2_B32
Definition: instructions.hh:1234
Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F32
Definition: instructions.hh:36758
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:10606
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F16_I16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:9508
Gcn3ISA::Inst_VOP3__V_TRIG_PREOP_F64
Definition: instructions.hh:58032
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:67834
Gcn3ISA::Inst_FLAT__FLAT_STORE_SHORT
Definition: instructions.hh:79614
Gcn3ISA::Inst_VOP3__V_CMP_LT_U64
Definition: instructions.hh:43820
Gcn3ISA::Decoder::decode_OP_VOP1__V_NOP
GPUStaticInst * decode_OP_VOP1__V_NOP(MachInst)
Definition: decoder.cc:9178
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_XOR
Definition: instructions.hh:80592
Gcn3ISA::Inst_SMEM__S_STORE_DWORD
Definition: instructions.hh:10656
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8386
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_I32(MachInst)
Definition: decoder.cc:8878
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:10306
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
Definition: instructions.hh:71006
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8302
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I32(MachInst)
Definition: decoder.cc:6507
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst)
Definition: decoder.cc:6315
Gcn3ISA::Inst_SOP2__S_MAX_U32
Definition: instructions.hh:640
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:4677
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:4281
Gcn3ISA::Decoder::tableSubDecode_OPU_VOP3
static IsaDecodeMethod tableSubDecode_OPU_VOP3[768]
Definition: gpu_decoder.hh:64
Gcn3ISA::Decoder::decode_OP_SOPP__S_SETPRIO
GPUStaticInst * decode_OP_SOPP__S_SETPRIO(MachInst)
Definition: decoder.cc:9070
Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F16
Definition: instructions.hh:21592
Gcn3ISA::Decoder::decode_OP_DS__DS_OR_B32
GPUStaticInst * decode_OP_DS__DS_OR_B32(MachInst)
Definition: decoder.cc:6387
Gcn3ISA::Inst_VOP3__V_CMPX_LT_I16
Definition: instructions.hh:40124
Gcn3ISA::Inst_DS__DS_RSUB_RTN_U64
Definition: instructions.hh:63366
Gcn3ISA::Decoder::decode_OP_VOP2__V_CNDMASK_B32
GPUStaticInst * decode_OP_VOP2__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:3237
Gcn3ISA::Inst_VOP3__V_MAD_F32
Definition: instructions.hh:52994
Gcn3ISA::Decoder::decode_OP_SMEM__S_ATC_PROBE
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE(MachInst)
Definition: decoder.cc:8548
Gcn3ISA::Inst_VOPC__V_CMPX_NE_I64
Definition: instructions.hh:31390
Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_U32(MachInst)
Definition: decoder.cc:6339
Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_BARRIER
GPUStaticInst * decode_OP_DS__DS_GWS_BARRIER(MachInst)
Definition: decoder.cc:7053
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Definition: instructions.hh:81196
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F32(MachInst)
Definition: decoder.cc:6573
Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2
Definition: instructions.hh:10044
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst)
Definition: decoder.cc:7887
Gcn3ISA::Inst_SOPP__S_CBRANCH_EXECZ
Definition: instructions.hh:8788
Gcn3ISA::Inst_VOP3__V_CMPX_LT_F16
Definition: instructions.hh:33788
Gcn3ISA::Inst_VOPC__V_CMP_F_U32
Definition: instructions.hh:28504
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_F32(MachInst)
Definition: decoder.cc:5157
Gcn3ISA::Inst_VOP1__V_MOV_B32
Definition: instructions.hh:15048
Gcn3ISA::Inst_VOP3__V_CMP_T_I32
Definition: instructions.hh:41576
Gcn3ISA::Decoder::decode_OP_VOP1__V_FRACT_F64
GPUStaticInst * decode_OP_VOP1__V_FRACT_F64(MachInst)
Definition: decoder.cc:9478
Gcn3ISA::InstFormat::iFmt_SOPC
InFmt_SOPC iFmt_SOPC
Definition: gpu_decoder.hh:1630
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst)
Definition: decoder.cc:7347
Gcn3ISA::Inst_VOP2__V_SUBREV_U16
Definition: instructions.hh:14208
Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFI_B32
GPUStaticInst * decode_OPU_VOP3__V_BFI_B32(MachInst)
Definition: decoder.cc:5913
Gcn3ISA::Inst_SOPC__S_CMP_LE_U32
Definition: instructions.hh:7804
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_SHORT
Definition: instructions.hh:69108
Gcn3ISA::Decoder::decode_OP_SOP2__S_ABSDIFF_I32
GPUStaticInst * decode_OP_SOP2__S_ABSDIFF_I32(MachInst)
Definition: decoder.cc:3801
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_OR
Definition: instructions.hh:70286
Gcn3ISA::Decoder::decode_OP_VOP1__V_RSQ_F16
GPUStaticInst * decode_OP_VOP1__V_RSQ_F16(MachInst)
Definition: decoder.cc:9538
Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P1_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:6147
Gcn3ISA::Inst_SOPK__S_CMPK_EQ_U32
Definition: instructions.hh:3430
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL
Definition: instructions.hh:78474
Gcn3ISA::Decoder::decode_OP_DS__DS_AND_B64
GPUStaticInst * decode_OP_DS__DS_AND_B64(MachInst)
Definition: decoder.cc:6717
Gcn3ISA::Inst_VOP3__V_ALIGNBIT_B32
Definition: instructions.hh:53930
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:9688
Gcn3ISA::Inst_SOP2__S_MAX_I32
Definition: instructions.hh:574
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U16(MachInst)
Definition: decoder.cc:4641
Gcn3ISA::Inst_SOPC__S_BITCMP0_B64
Definition: instructions.hh:7984
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B96
GPUStaticInst * decode_OP_DS__DS_READ_B96(MachInst)
Definition: decoder.cc:7179
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:4203
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst)
Definition: decoder.cc:7443
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F64(MachInst)
Definition: decoder.cc:4407
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:4335
Gcn3ISA::Inst_VOP3__V_CMPX_LG_F32
Definition: instructions.hh:36164
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst)
Definition: decoder.cc:7587
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst)
Definition: decoder.cc:6303
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8458
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:5481
Gcn3ISA::Inst_VOPC__V_CMPX_LT_I16
Definition: instructions.hh:27046
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_F32
GPUStaticInst * decode_OPU_VOP3__V_SUB_F32(MachInst)
Definition: decoder.cc:5139
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:4299
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst)
Definition: decoder.cc:6255
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:5169
Gcn3ISA::Inst_SOPC__S_CMP_GE_U32
Definition: instructions.hh:7684
Gcn3ISA::Inst_VOP2__V_XOR_B32
Definition: instructions.hh:12888
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U64(MachInst)
Definition: decoder.cc:5025
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:67390
Gcn3ISA::Inst_DS__DS_WRAP_RTN_B32
Definition: instructions.hh:61270
Gcn3ISA::Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst)
Definition: decoder.cc:3927
Gcn3ISA::Inst_VOPC__V_CMPX_LT_F16
Definition: instructions.hh:20910
Gcn3ISA::Inst_VOP1__V_SQRT_F32
Definition: instructions.hh:17328
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8272
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Definition: instructions.hh:81594
Gcn3ISA::Inst_VOP3__V_CMP_F_U16
Definition: instructions.hh:39530
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:10096
Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F32
Definition: instructions.hh:18108
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
Definition: instructions.hh:78906
Gcn3ISA::Inst_VOP3__V_CMPX_GT_F64
Definition: instructions.hh:38210
Gcn3ISA::Decoder::decode_OP_SOP2__S_XNOR_B32
GPUStaticInst * decode_OP_SOP2__S_XNOR_B32(MachInst)
Definition: decoder.cc:3705
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:10174
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_U32
GPUStaticInst * decode_OP_DS__DS_ADD_U32(MachInst)
Definition: decoder.cc:6327
Gcn3ISA::Inst_VOP3__V_INTERP_P1LV_F16
Definition: instructions.hh:56766
Gcn3ISA::InFmt_DS::OP
unsigned int OP
Definition: gpu_decoder.hh:1361
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2_B32(MachInst)
Definition: decoder.cc:6411
Gcn3ISA::Inst_SOPK__S_CBRANCH_I_FORK
Definition: instructions.hh:3910
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:9784
Gcn3ISA::Inst_VOP3__V_CMPX_GT_I64
Definition: instructions.hh:44546
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:4377
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:5121
Gcn3ISA::Inst_SMEM__S_ATC_PROBE_BUFFER
Definition: instructions.hh:11430
Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORD
Definition: instructions.hh:79304
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:7521
Gcn3ISA::Inst_VOP1__V_NOT_B32
Definition: instructions.hh:17568
Gcn3ISA::Decoder::decode_OP_SOP2__S_BFM_B64
GPUStaticInst * decode_OP_SOP2__S_BFM_B64(MachInst)
Definition: decoder.cc:3759
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:72102
Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE0
Definition: instructions.hh:49514
Gcn3ISA::Decoder::decode_OP_DS__DS_READ2ST64_B32
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B32(MachInst)
Definition: decoder.cc:6615
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FRACT_F16
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F16(MachInst)
Definition: decoder.cc:5823
Gcn3ISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst)
Definition: decoder.cc:9154
Gcn3ISA::Inst_SOP1__S_FLBIT_I32
Definition: instructions.hh:5350
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I64(MachInst)
Definition: decoder.cc:7113
Gcn3ISA::InFmt_VOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1578
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:7233
Gcn3ISA::Inst_DS__DS_XOR_SRC2_B32
Definition: instructions.hh:65400
Gcn3ISA::Decoder::decode_OP_SOP2__S_NAND_B32
GPUStaticInst * decode_OP_SOP2__S_NAND_B32(MachInst)
Definition: decoder.cc:3681
Gcn3ISA::Inst_DS__DS_XOR_B32
Definition: instructions.hh:59154
Gcn3ISA::Inst_VOP3__V_SUBREV_U32
Definition: instructions.hh:47006
Gcn3ISA::Inst_VOP1__V_EXP_F16
Definition: instructions.hh:18696
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I64(MachInst)
Definition: decoder.cc:6819
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_F16
GPUStaticInst * decode_OPU_VOP3__V_SUB_F16(MachInst)
Definition: decoder.cc:5307
Gcn3ISA::Inst_SOP1__S_XOR_SAVEEXEC_B64
Definition: instructions.hh:6184
Gcn3ISA::Inst_VOPC__V_CMPX_LG_F32
Definition: instructions.hh:23202
Gcn3ISA::Inst_VOP3__V_OR_B32
Definition: instructions.hh:46664
Gcn3ISA::Inst_VOP3__V_CMP_NLT_F32
Definition: instructions.hh:35702
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:7299
Gcn3ISA::Inst_DS__DS_CMPST_B32
Definition: instructions.hh:59472
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:10528
Gcn3ISA::InFmt_SOPP::OP
unsigned int OP
Definition: gpu_decoder.hh:1522
Gcn3ISA::Inst_SOPC__S_CMP_LG_U64
Definition: instructions.hh:8284
Gcn3ISA::Inst_VOP3__V_LDEXP_F64
Definition: instructions.hh:57174
Gcn3ISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:6153
Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F16
Definition: instructions.hh:19672
Gcn3ISA::Inst_SOP2__S_XNOR_B64
Definition: instructions.hh:1828
Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F16
Definition: instructions.hh:34316
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE
Definition: instructions.hh:74298
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8332
Gcn3ISA::Inst_VOP3__V_MAD_U16
Definition: instructions.hh:56048
Gcn3ISA::Inst_VOP2__V_MAX_U32
Definition: instructions.hh:12492
Gcn3ISA::Inst_VOP2__V_OR_B32
Definition: instructions.hh:12822
Gcn3ISA::Inst_VOPC__V_CMP_NLE_F32
Definition: instructions.hh:22632
Gcn3ISA::Inst_VOP3__V_SQRT_F64
Definition: instructions.hh:50894
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:10240
Gcn3ISA::Inst_VOP3__V_CUBEID_F32
Definition: instructions.hh:53210
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_B32(MachInst)
Definition: decoder.cc:6423
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst)
Definition: decoder.cc:6027
Gcn3ISA::Inst_VOPC__V_CMP_O_F64
Definition: instructions.hh:24346
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:7965
Gcn3ISA::Inst_DS__DS_READ_U16
Definition: instructions.hh:61770
Gcn3ISA::Decoder::decode_OP_VOP1__V_FFBH_I32
GPUStaticInst * decode_OP_VOP1__V_FFBH_I32(MachInst)
Definition: decoder.cc:9460
Gcn3ISA::Inst_DS__DS_CMPST_F32
Definition: instructions.hh:59532
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:9952
Gcn3ISA::Inst_SOP1__S_SWAPPC_B64
Definition: instructions.hh:5944
Gcn3ISA::Inst_VOP3__V_LDEXP_F32
Definition: instructions.hh:57438
Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:9556
Gcn3ISA::Decoder::decode_OP_SOPK__S_MOVK_I32
GPUStaticInst * decode_OP_SOPK__S_MOVK_I32(MachInst)
Definition: decoder.cc:3813
Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F32
Definition: instructions.hh:23450
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:10108
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FFBH_U32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_U32(MachInst)
Definition: decoder.cc:5679
Gcn3ISA::Inst_SOPK__S_CMPK_LT_I32
Definition: instructions.hh:3310
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst)
Definition: decoder.cc:9124
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORD
Definition: instructions.hh:68730
Gcn3ISA::Decoder::decode_OP_SOPC__S_SETVSKIP
GPUStaticInst * decode_OP_SOPC__S_SETVSKIP(MachInst)
Definition: decoder.cc:8956
Gcn3ISA::Inst_VOPC__V_CMP_LT_U16
Definition: instructions.hh:26522
Gcn3ISA::Inst_VOPC__V_CMPX_GT_F64
Definition: instructions.hh:25184
Gcn3ISA::Inst_VOP2__V_ASHRREV_I32
Definition: instructions.hh:12624
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8380
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F32(MachInst)
Definition: decoder.cc:4209
Gcn3ISA::Inst_VOP3__V_MUL_HI_I32
Definition: instructions.hh:57372
Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_F16
GPUStaticInst * decode_OP_VOP1__V_RCP_F16(MachInst)
Definition: decoder.cc:9526
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_RTN_U64
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U64(MachInst)
Definition: decoder.cc:6783
Gcn3ISA::Decoder::decode_OP_SOP2__S_CSELECT_B64
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B64(MachInst)
Definition: decoder.cc:3615
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U16
Definition: instructions.hh:27604
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:5037
Gcn3ISA::Inst_VOPC__V_CMP_LE_U64
Definition: instructions.hh:30750
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:7971
Gcn3ISA::Inst_DS__DS_MAX_RTN_F64
Definition: instructions.hh:64488
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X
Definition: instructions.hh:71806
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:9922
Gcn3ISA::Inst_VOPC__V_CMPX_GT_I64
Definition: instructions.hh:31328
Gcn3ISA::Decoder::decode_OP_VOP2__V_MADAK_F16
GPUStaticInst * decode_OP_VOP2__V_MADAK_F16(MachInst)
Definition: decoder.cc:3459
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:4713
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:4065
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:4563
Gcn3ISA::Inst_VOPC__V_CMP_EQ_U64
Definition: instructions.hh:30684
Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U32(MachInst)
Definition: decoder.cc:6483
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOV_B64
GPUStaticInst * decode_OP_SOP1__S_MOV_B64(MachInst)
Definition: decoder.cc:8566
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:9724
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBREV_U16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U16(MachInst)
Definition: decoder.cc:5343
Gcn3ISA::Decoder::decode_OP_DS__DS_RSUB_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_U64(MachInst)
Definition: decoder.cc:6675
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I16(MachInst)
Definition: decoder.cc:10276
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:4461
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELD_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B64(MachInst)
Definition: decoder.cc:8830
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:4731
Gcn3ISA::Inst_VOP3__V_CMP_LT_U16
Definition: instructions.hh:39596
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_I64(MachInst)
Definition: decoder.cc:6693
Gcn3ISA::Inst_DS__DS_MAX_RTN_I64
Definition: instructions.hh:63630
Gcn3ISA::Inst_VOP3__V_TRUNC_F32
Definition: instructions.hh:50174
Gcn3ISA::InstFormat::iFmt_SOPP
InFmt_SOPP iFmt_SOPP
Definition: gpu_decoder.hh:1632
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:7989
Gcn3ISA::InstFormat::iFmt_VINTRP
InFmt_VINTRP iFmt_VINTRP
Definition: gpu_decoder.hh:1633
Gcn3ISA::InFmt_SMEM::OP
unsigned int OP
Definition: gpu_decoder.hh:1483
Gcn3ISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst)
Definition: decoder.cc:6549
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SAD_HI_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_HI_U8(MachInst)
Definition: decoder.cc:6009
Gcn3ISA::Inst_VOP3__V_CMP_LE_U64
Definition: instructions.hh:43952
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:10570
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F32(MachInst)
Definition: decoder.cc:7005
Gcn3ISA::Inst_VOP1__V_SQRT_F16
Definition: instructions.hh:18516
Gcn3ISA::Inst_VOP2__V_MAX_I32
Definition: instructions.hh:12360
Gcn3ISA::Inst_DS__DS_MSKOR_RTN_B64
Definition: instructions.hh:64026
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:9718
Gcn3ISA::Inst_VOP3__V_CMP_EQ_U64
Definition: instructions.hh:43886
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:4719
Gcn3ISA::Inst_VOP3__V_CMP_F_U32
Definition: instructions.hh:41642
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:4365
Gcn3ISA::Decoder::decode_OP_DS__DS_AND_B32
GPUStaticInst * decode_OP_DS__DS_AND_B32(MachInst)
Definition: decoder.cc:6381
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst)
Definition: decoder.cc:7947
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:4467
Gcn3ISA::Decoder::subDecode_OP_SOPC
GPUStaticInst * subDecode_OP_SOPC(MachInst)
Definition: decoder.cc:3157
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst)
Definition: decoder.cc:7731
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:7497
Gcn3ISA::Inst_VOPC__V_CMP_NGT_F64
Definition: instructions.hh:24610
Gcn3ISA::Inst_SOPP__S_BRANCH
Definition: instructions.hh:8452
Gcn3ISA::Inst_VOPC__V_CMP_F_I32
Definition: instructions.hh:27976
Gcn3ISA::Inst_SOP1__S_MOVRELS_B32
Definition: instructions.hh:6664
Gcn3ISA::Inst_VOP2__V_AND_B32
Definition: instructions.hh:12756
Gcn3ISA::Decoder::decode_OP_DS__DS_READ2_B32
GPUStaticInst * decode_OP_DS__DS_READ2_B32(MachInst)
Definition: decoder.cc:6609
Gcn3ISA::Inst_VOP1__V_RCP_F64
Definition: instructions.hh:17208
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U16
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:5349
Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F16
Definition: instructions.hh:21716
Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFM_B32
GPUStaticInst * decode_OPU_VOP3__V_BFM_B32(MachInst)
Definition: decoder.cc:6291
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_B
Definition: instructions.hh:75234
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_CL_O
Definition: instructions.hh:77970
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_GE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_I32(MachInst)
Definition: decoder.cc:3843
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:10114
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:67316
Gcn3ISA::Decoder::decode_OP_VOP1__V_COS_F32
GPUStaticInst * decode_OP_VOP1__V_COS_F32(MachInst)
Definition: decoder.cc:9430
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:8098
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_F16
GPUStaticInst * decode_OP_VOP2__V_MUL_F16(MachInst)
Definition: decoder.cc:3441
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_SSHORT
Definition: instructions.hh:68656
Gcn3ISA::Inst_VOP2__V_MAX_F32
Definition: instructions.hh:12228
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_F64(MachInst)
Definition: decoder.cc:6771
Gcn3ISA::Inst_VOPC__V_CMP_F_F32
Definition: instructions.hh:21840
Gcn3ISA::Inst_VOP3__V_MUL_HI_U32
Definition: instructions.hh:57306
Gcn3ISA::Inst_DS__DS_MSKOR_B64
Definition: instructions.hh:62744
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_OR_X2
Definition: instructions.hh:71222
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:4311
Gcn3ISA::Inst_SOPC__S_SETVSKIP
Definition: instructions.hh:8104
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:67760
Gcn3ISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:9472
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:3273
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:4395
Gcn3ISA::Inst_SOPC__S_CMP_GT_U32
Definition: instructions.hh:7624
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:7419
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MOV_FED_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:5463
Gcn3ISA::Decoder::decode_OPU_VOP3__V_BFE_U32
GPUStaticInst * decode_OPU_VOP3__V_BFE_U32(MachInst)
Definition: decoder.cc:5901
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F64_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:9202
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U16
Definition: instructions.hh:40718
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_U32(MachInst)
Definition: decoder.cc:8926
Gcn3ISA::Inst_SOP1__S_SET_GPR_IDX_IDX
Definition: instructions.hh:7084
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst)
Definition: decoder.cc:7851
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RCP_F64
GPUStaticInst * decode_OPU_VOP3__V_RCP_F64(MachInst)
Definition: decoder.cc:5631
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:10024
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:10000
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F32(MachInst)
Definition: decoder.cc:4215
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:7413
Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_I32
GPUStaticInst * decode_OP_VOP2__V_MIN_I32(MachInst)
Definition: decoder.cc:3309
Gcn3ISA::Decoder::decode_OP_VOP1__V_RNDNE_F64
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F64(MachInst)
Definition: decoder.cc:9328
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:4047
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1(MachInst)
Definition: decoder.cc:8248
Gcn3ISA::Inst_SOPP__S_SETPRIO
Definition: instructions.hh:9166
Gcn3ISA::Inst_DS__DS_MSKOR_RTN_B32
Definition: instructions.hh:60742
Gcn3ISA::Decoder::decode_OPU_VOP3__V_EXP_F16
GPUStaticInst * decode_OPU_VOP3__V_EXP_F16(MachInst)
Definition: decoder.cc:5781
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Definition: instructions.hh:80928
Gcn3ISA::Inst_MIMG__IMAGE_STORE_MIP_PCK
Definition: instructions.hh:73306
Gcn3ISA::Inst_VOP2__V_SUBBREV_U32
Definition: instructions.hh:13524
Gcn3ISA::Inst_DS__DS_WRITE2ST64_B64
Definition: instructions.hh:62934
Gcn3ISA::Inst_VOP3__V_LOG_F16
Definition: instructions.hh:52142
Gcn3ISA::Inst_SOPK__S_CMPK_EQ_I32
Definition: instructions.hh:3070
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:4809
Gcn3ISA::Inst_DS__DS_DEC_RTN_U64
Definition: instructions.hh:63498
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F32(MachInst)
Definition: decoder.cc:9892
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:9778
Gcn3ISA::Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst)
Definition: decoder.cc:8530
Gcn3ISA::Decoder::decode_OP_SOP2__S_SUB_I32
GPUStaticInst * decode_OP_SOP2__S_SUB_I32(MachInst)
Definition: decoder.cc:3567
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUBB_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBB_U32(MachInst)
Definition: decoder.cc:5289
Gcn3ISA::Decoder::decode_OP_SOP2__S_NAND_B64
GPUStaticInst * decode_OP_SOP2__S_NAND_B64(MachInst)
Definition: decoder.cc:3687
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:7401
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Definition: instructions.hh:81262
Gcn3ISA::Inst_VOPC__V_CMP_EQ_F32
Definition: instructions.hh:21972
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MED3_F32
GPUStaticInst * decode_OPU_VOP3__V_MED3_F32(MachInst)
Definition: decoder.cc:5985
Gcn3ISA::Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8794
Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8428
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:7377
Gcn3ISA::Inst_VOPC__V_CMP_LT_U32
Definition: instructions.hh:28570
Gcn3ISA::Inst_VOPC__V_CMPX_GT_U16
Definition: instructions.hh:27728
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst)
Definition: decoder.cc:7563
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_O
Definition: instructions.hh:77898
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8031
Gcn3ISA::InFmt_SMEM
Definition: gpu_decoder.hh:1477
Gcn3ISA::Inst_VOP3__V_CMP_F_I16
Definition: instructions.hh:39002
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U32
Definition: instructions.hh:29652
Gcn3ISA::Inst_VOP3__V_XOR_B32
Definition: instructions.hh:46730
Gcn3ISA::Decoder::decode_OP_SOP2__S_ASHR_I64
GPUStaticInst * decode_OP_SOP2__S_ASHR_I64(MachInst)
Definition: decoder.cc:3747
Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F64
Definition: instructions.hh:32402
Gcn3ISA::Inst_VOP1__V_LOG_LEGACY_F32
Definition: instructions.hh:19356
Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F64
Definition: instructions.hh:25742
Gcn3ISA::Decoder::subDecode_OP_SOPP
GPUStaticInst * subDecode_OP_SOPP(MachInst)
Definition: decoder.cc:3165
Gcn3ISA::Inst_VOP3__V_BFI_B32
Definition: instructions.hh:53642
Gcn3ISA::Inst_VOPC__V_CMP_EQ_I32
Definition: instructions.hh:28108
Gcn3ISA::Inst_VOP3__V_CMP_F_F16
Definition: instructions.hh:32666
Gcn3ISA::Inst_VOP3__V_CMP_F_U64
Definition: instructions.hh:43754
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LERP_U8
GPUStaticInst * decode_OPU_VOP3__V_LERP_U8(MachInst)
Definition: decoder.cc:5931
Gcn3ISA::Inst_VOP3__V_CMP_LT_U32
Definition: instructions.hh:41708
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:8134
Gcn3ISA::Inst_VOP3__V_CMP_EQ_F32
Definition: instructions.hh:34910
Gcn3ISA::Inst_DS__DS_CMPST_B64
Definition: instructions.hh:62994
Gcn3ISA::Inst_VOPC__V_CMPX_O_F64
Definition: instructions.hh:25370
Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F16
Definition: instructions.hh:20654
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:10492
Gcn3ISA::Inst_DS__DS_MIN_RTN_F32
Definition: instructions.hh:61138
Gcn3ISA::Inst_VOP1__V_RNDNE_F16
Definition: instructions.hh:19056
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:3957
Gcn3ISA::Inst_SOP1__S_BCNT0_I32_B64
Definition: instructions.hh:4810
Gcn3ISA::Inst_VOP3__V_CMPX_O_F64
Definition: instructions.hh:38408
Gcn3ISA::Decoder::decode_OP_SOP2__S_MIN_I32
GPUStaticInst * decode_OP_SOP2__S_MIN_I32(MachInst)
Definition: decoder.cc:3585
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_U32(MachInst)
Definition: decoder.cc:3393
Gcn3ISA::Inst_VOP3__V_CMP_EQ_I32
Definition: instructions.hh:41246
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst)
Definition: decoder.cc:6261
Gcn3ISA::Inst_DS__DS_MIN_RTN_I32
Definition: instructions.hh:60280
Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U64(MachInst)
Definition: decoder.cc:7101
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Definition: instructions.hh:81460
Gcn3ISA::Inst_DS__DS_CMPST_F64
Definition: instructions.hh:63054
Gcn3ISA::Inst_VOP3__V_CVT_U32_F32
Definition: instructions.hh:48914
Gcn3ISA::Inst_VOP3__V_BFE_U32
Definition: instructions.hh:53498
Gcn3ISA::Inst_VOP3__V_BCNT_U32_B32
Definition: instructions.hh:57636
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:72546
Gcn3ISA::Decoder::decode_OP_DS__DS_OR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B32(MachInst)
Definition: decoder.cc:6531
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:4923
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:10054
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SUB_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_U32(MachInst)
Definition: decoder.cc:5271
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:4887
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8278
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:10444
Gcn3ISA::IsaDecodeMethod
GPUStaticInst *(Decoder::*)(MachInst) IsaDecodeMethod
Definition: gpu_decoder.hh:52
Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_U16
GPUStaticInst * decode_OP_VOP2__V_ADD_U16(MachInst)
Definition: decoder.cc:3465
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:8326
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst)
Definition: decoder.cc:7953
Gcn3ISA::Inst_VOPC__V_CMP_GT_U64
Definition: instructions.hh:30816
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:4149
Gcn3ISA::Inst_SOPK__S_CMPK_LE_U32
Definition: instructions.hh:3730
Gcn3ISA::Decoder::decode_OP_SOP1__S_MOVRELS_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B32(MachInst)
Definition: decoder.cc:8812
Gcn3ISA::Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst)
Definition: decoder.cc:8554
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:5493
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_F32(MachInst)
Definition: decoder.cc:6435
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_LZ
Definition: instructions.hh:77394
Gcn3ISA::Inst_VOP3__V_CMPX_GT_U16
Definition: instructions.hh:40850
Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F16
Definition: instructions.hh:34712
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:4629
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U32
Definition: instructions.hh:42830
Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F64
Definition: instructions.hh:37748
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst)
Definition: decoder.cc:9118
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:4305
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8284
Gcn3ISA::Inst_DS__DS_READ_B32
Definition: instructions.hh:61402
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_STORE
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE(MachInst)
Definition: decoder.cc:7467
Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F16
Definition: instructions.hh:34448
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:5535
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I32(MachInst)
Definition: decoder.cc:10468
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:4287
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:5001
Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_V
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_V(MachInst)
Definition: decoder.cc:7035
Gcn3ISA::Inst_VOP3__V_CMP_GT_U64
Definition: instructions.hh:44018
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8452
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U32(MachInst)
Definition: decoder.cc:10516
Gcn3ISA::Inst_VOP1__V_CVT_U32_F32
Definition: instructions.hh:15408
Gcn3ISA::Inst_VOP2__V_MADMK_F32
Definition: instructions.hh:13020
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_LZ_O
Definition: instructions.hh:75954
Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I32_F64
Definition: instructions.hh:51374
Gcn3ISA::Decoder::decode_OP_VOP2__V_ADD_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_U32(MachInst)
Definition: decoder.cc:3387
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBEMA_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEMA_F32(MachInst)
Definition: decoder.cc:5895
Gcn3ISA::Decoder::decode_OP_VOP1__V_RCP_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_F32(MachInst)
Definition: decoder.cc:9382
Gcn3ISA::Decoder::decode_OP_SOPK__S_GETREG_B32
GPUStaticInst * decode_OP_SOPK__S_GETREG_B32(MachInst)
Definition: decoder.cc:3915
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_B128
GPUStaticInst * decode_OP_DS__DS_READ_B128(MachInst)
Definition: decoder.cc:7185
Gcn3ISA::Inst_VOP2__V_SUBREV_F16
Definition: instructions.hh:13734
Gcn3ISA::Inst_VOPC__V_CMPX_LE_U16
Definition: instructions.hh:27666
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:9292
Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_B64(MachInst)
Definition: decoder.cc:6735
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C
Definition: instructions.hh:74874
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:10480
Gcn3ISA::Inst_DS__DS_AND_B32
Definition: instructions.hh:59034
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_LDS_DWORD
Definition: instructions.hh:69478
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAC_F16
GPUStaticInst * decode_OP_VOP2__V_MAC_F16(MachInst)
Definition: decoder.cc:3447
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_I32(MachInst)
Definition: decoder.cc:8872
Gcn3ISA::Inst_SOP1__S_FF0_I32_B32
Definition: instructions.hh:4990
Gcn3ISA::Inst_VOP3__V_CMP_F_I32
Definition: instructions.hh:41114
Gcn3ISA::Inst_VOP3__V_DIV_FMAS_F64
Definition: instructions.hh:55460
Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_B32
GPUStaticInst * decode_OP_DS__DS_XOR_B32(MachInst)
Definition: decoder.cc:6393
Gcn3ISA::Decoder::decode_OP_VOP1__V_RSQ_F64
GPUStaticInst * decode_OP_VOP1__V_RSQ_F64(MachInst)
Definition: decoder.cc:9406
Gcn3ISA::Inst_DS__DS_OR_RTN_B32
Definition: instructions.hh:60610
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U16(MachInst)
Definition: decoder.cc:10282
Gcn3ISA::Inst_SOPP__S_TTRACEDATA
Definition: instructions.hh:9544
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_BYTE
Definition: instructions.hh:69026
Gcn3ISA::Inst_VOP1__V_SQRT_F64
Definition: instructions.hh:17388
Gcn3ISA::Inst_VOP3__V_CMP_U_F16
Definition: instructions.hh:33194
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_L
Definition: instructions.hh:76746
Gcn3ISA::InstFormat::iFmt_DS
InFmt_DS iFmt_DS
Definition: gpu_decoder.hh:1613
Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_BR
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_BR(MachInst)
Definition: decoder.cc:7041
Gcn3ISA::Decoder::decode_OPU_VOP3__V_SIN_F16
GPUStaticInst * decode_OPU_VOP3__V_SIN_F16(MachInst)
Definition: decoder.cc:5829
Gcn3ISA::Inst_VOP3__V_CMP_F_F32
Definition: instructions.hh:34778
Gcn3ISA::Inst_VOP3__V_MAX_I32
Definition: instructions.hh:46202
Gcn3ISA::Decoder::decode_OP_DS__DS_AND_RTN_B32
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B32(MachInst)
Definition: decoder.cc:6525
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:10540
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:10630
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:10786
Gcn3ISA::Inst_VOPC__V_CMP_NGT_F16
Definition: instructions.hh:20522
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_SBYTE
Definition: instructions.hh:68508
Gcn3ISA::Inst_VOPC__V_CMP_NLG_F32
Definition: instructions.hh:22500
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:4083
Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F32
Definition: instructions.hh:22698
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:4575
Gcn3ISA::Inst_VOP3__V_CVT_PKNORM_I16_F32
Definition: instructions.hh:58164
Gcn3ISA::Decoder::decode_OP_SOP2__S_ORN2_B64
GPUStaticInst * decode_OP_SOP2__S_ORN2_B64(MachInst)
Definition: decoder.cc:3675
Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:67464
Gcn3ISA::Inst_VOP3__V_AND_B32
Definition: instructions.hh:46598
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst)
Definition: decoder.cc:7797
Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4
Definition: instructions.hh:10792
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:5109
Gcn3ISA::Inst_VOPC__V_CMP_NLT_F64
Definition: instructions.hh:24808
Gcn3ISA::Inst_VINTRP__V_INTERP_P2_F32
Definition: instructions.hh:32138
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:4893
Gcn3ISA::Inst_DS__DS_READ_B128
Definition: instructions.hh:67182
Gcn3ISA::Inst_VOP3__V_CEIL_F64
Definition: instructions.hh:49934
Gcn3ISA::Inst_SOPP__S_SENDMSG
Definition: instructions.hh:9220
Gcn3ISA::Inst_DS__DS_WRITE2ST64_B32
Definition: instructions.hh:59404
Gcn3ISA::Inst_VOP3__V_MAX_F32
Definition: instructions.hh:46070
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst)
Definition: decoder.cc:9130
Gcn3ISA::Inst_SOP1__S_OR_SAVEEXEC_B64
Definition: instructions.hh:6124
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:10168
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst)
Definition: decoder.cc:7611
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD
Definition: instructions.hh:80060
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_I32
GPUStaticInst * decode_OP_DS__DS_MAX_I32(MachInst)
Definition: decoder.cc:6363
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:10804
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:4131
Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4
Definition: instructions.hh:10112
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:72398
Gcn3ISA::Inst_VOPC__V_CMP_LT_F64
Definition: instructions.hh:23950
Gcn3ISA::Decoder::decode_OP_SOPP__S_ICACHE_INV
GPUStaticInst * decode_OP_SOPP__S_ICACHE_INV(MachInst)
Definition: decoder.cc:9094
Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F64
Definition: instructions.hh:25556
Gcn3ISA::Inst_VOP3__V_CMPX_LE_U16
Definition: instructions.hh:40784
Gcn3ISA::Decoder::decode_OP_VOP1__V_RSQ_F32
GPUStaticInst * decode_OP_VOP1__V_RSQ_F32(MachInst)
Definition: decoder.cc:9394
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:3993
Gcn3ISA::Inst_VOP3__V_INTERP_MOV_F32
Definition: instructions.hh:56634
Gcn3ISA::Inst_VOPC__V_CMPX_GE_U64
Definition: instructions.hh:31948
Gcn3ISA::Inst_SOP1__S_NOR_SAVEEXEC_B64
Definition: instructions.hh:6424
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F16
Definition: instructions.hh:33854
Gcn3ISA::Inst_MIMG__IMAGE_GET_LOD
Definition: instructions.hh:78330
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:8446
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:4665
Gcn3ISA::Decoder::decode_OP_VOP2__V_ADDC_U32
GPUStaticInst * decode_OP_VOP2__V_ADDC_U32(MachInst)
Definition: decoder.cc:3405
Gcn3ISA::Decoder::decode_OP_SOP1__S_GETPC_B64
GPUStaticInst * decode_OP_SOP1__S_GETPC_B64(MachInst)
Definition: decoder.cc:8728
Gcn3ISA::Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8764
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:9520
Gcn3ISA::Inst_VOPC__V_CMP_LT_I64
Definition: instructions.hh:30090
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I16
Definition: instructions.hh:40190
Gcn3ISA::Inst_DS__DS_WRITE_B8
Definition: instructions.hh:59826
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F16(MachInst)
Definition: decoder.cc:9658
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX_I32(MachInst)
Definition: decoder.cc:5205
Gcn3ISA::Inst_VOP3__V_CVT_PK_U16_U32
Definition: instructions.hh:58362
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U32(MachInst)
Definition: decoder.cc:4833
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_O(MachInst)
Definition: decoder.cc:7839
Gcn3ISA::Inst_VOP3__V_CMP_LT_F64
Definition: instructions.hh:36956
Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16
Definition: instructions.hh:10588
Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst)
Definition: decoder.cc:7023
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_B_O
Definition: instructions.hh:75810
Gcn3ISA::Inst_VOP2__V_MADAK_F32
Definition: instructions.hh:13086
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_U32(MachInst)
Definition: decoder.cc:3861
Gcn3ISA::Decoder::decode_OP_DS__DS_BPERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_BPERMUTE_B32(MachInst)
Definition: decoder.cc:6657
Gcn3ISA::Inst_DS__DS_MAX_U64
Definition: instructions.hh:62504
Gcn3ISA::Inst_VOPC__V_CMP_F_U64
Definition: instructions.hh:30552
Gcn3ISA::Inst_VOP3__V_SUBREV_F32
Definition: instructions.hh:45542
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_B32(MachInst)
Definition: decoder.cc:6405
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:10672
Gcn3ISA::Inst_VOP3__V_CMP_LT_I64
Definition: instructions.hh:43292
Gcn3ISA::Inst_VOP3__V_CMP_F_I64
Definition: instructions.hh:43226
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_L_O
Definition: instructions.hh:77610
Gcn3ISA::Decoder::decode_OP_DS__DS_SWIZZLE_B32
GPUStaticInst * decode_OP_DS__DS_SWIZZLE_B32(MachInst)
Definition: decoder.cc:6645
Gcn3ISA::Inst_SOP1__S_CMOV_B32
Definition: instructions.hh:4270
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:4341
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUB_F32
GPUStaticInst * decode_OP_VOP2__V_SUB_F32(MachInst)
Definition: decoder.cc:3249
Gcn3ISA::Inst_VOPC__V_CMP_TRU_F64
Definition: instructions.hh:24874
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8338
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:3963
Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRUNC_F32
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F32(MachInst)
Definition: decoder.cc:5577
Gcn3ISA::Inst_SOPC__S_CMP_LE_I32
Definition: instructions.hh:7444
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst)
Definition: decoder.cc:7929
Gcn3ISA::Inst_VOP3__V_CMP_F_F64
Definition: instructions.hh:36890
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst)
Definition: decoder.cc:9034
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAD_I64_I32
GPUStaticInst * decode_OPU_VOP3__V_MAD_I64_I32(MachInst)
Definition: decoder.cc:6099
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RNDNE_F64
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F64(MachInst)
Definition: decoder.cc:5559
Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHL_B64
GPUStaticInst * decode_OP_SOP2__S_LSHL_B64(MachInst)
Definition: decoder.cc:3723
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ
Definition: instructions.hh:75378
Gcn3ISA::Inst_VOP3__V_CVT_PK_U8_F32
Definition: instructions.hh:55010
Gcn3ISA::Decoder::decode_OP_VOP2__V_LDEXP_F16
GPUStaticInst * decode_OP_VOP2__V_LDEXP_F16(MachInst)
Definition: decoder.cc:3543
Gcn3ISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst)
Definition: decoder.cc:9028
Gcn3ISA::Inst_VOP1__V_RNDNE_F64
Definition: instructions.hh:16488
Gcn3ISA::Inst_VOP2__V_SUBB_U32
Definition: instructions.hh:13446
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:10588
Gcn3ISA::Decoder::decode_OP_SOPP__S_ENDPGM_SAVED
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_SAVED(MachInst)
Definition: decoder.cc:9142
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
Definition: instructions.hh:70934
Gcn3ISA::Inst_SOP2__S_AND_B64
Definition: instructions.hh:904
Gcn3ISA::Decoder::decode_OP_VOP2__V_SUBREV_U16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U16(MachInst)
Definition: decoder.cc:3477
Gcn3ISA::Inst_DS__DS_RSUB_U32
Definition: instructions.hh:58614
Gcn3ISA::Inst_VOP3__V_CMPX_GE_U64
Definition: instructions.hh:45206
Gcn3ISA::Inst_DS__DS_WRXCHG_RTN_B64
Definition: instructions.hh:64092
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F16
Definition: instructions.hh:20972
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:5451
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:4635
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:9742
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst)
Definition: decoder.cc:7893
Gcn3ISA::Inst_VOP3__V_MSAD_U8
Definition: instructions.hh:55532
Gcn3ISA::Decoder::decode_OP_DS__DS_READ_U8
GPUStaticInst * decode_OP_DS__DS_READ_U8(MachInst)
Definition: decoder.cc:6627
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MED3_I32
GPUStaticInst * decode_OPU_VOP3__V_MED3_I32(MachInst)
Definition: decoder.cc:5991
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_L
Definition: instructions.hh:75162
Gcn3ISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:8470
Gcn3ISA::Decoder::subDecode_OP_SMEM
GPUStaticInst * subDecode_OP_SMEM(MachInst)
Definition: decoder.cc:3173
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_I32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:9196
Gcn3ISA::Decoder::decode_OPU_VOP3__V_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_OR_B32(MachInst)
Definition: decoder.cc:5247
Gcn3ISA::Inst_SOPK__S_CMPK_LE_I32
Definition: instructions.hh:3370
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I16
Definition: instructions.hh:27108
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:5013
Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHLREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:3345
Gcn3ISA::Inst_SOPK__S_SETREG_IMM32_B32
Definition: instructions.hh:4090
Gcn3ISA::Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64
GPUStaticInst * decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst)
Definition: decoder.cc:3807
Gcn3ISA::Inst_VOP3__V_MAD_U32_U24
Definition: instructions.hh:53138
Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F16
Definition: instructions.hh:56364
Gcn3ISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B32(MachInst)
Definition: decoder.cc:6543
Gcn3ISA::Decoder::decode_OP_DS__DS_SUB_U32
GPUStaticInst * decode_OP_DS__DS_SUB_U32(MachInst)
Definition: decoder.cc:6333
Gcn3ISA::Inst_SOPC__S_CMP_GE_I32
Definition: instructions.hh:7324
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:9226
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst)
Definition: decoder.cc:7461
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:9982
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_B
Definition: instructions.hh:77250
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:10132
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_L_O
Definition: instructions.hh:78042
Gcn3ISA::InstFormat::iFmt_SOP2
InFmt_SOP2 iFmt_SOP2
Definition: gpu_decoder.hh:1629
Gcn3ISA::Decoder::decode_OP_SOPP__S_SENDMSG
GPUStaticInst * decode_OP_SOPP__S_SENDMSG(MachInst)
Definition: decoder.cc:9076
Gcn3ISA::Inst_VOP3__V_LOG_LEGACY_F32
Definition: instructions.hh:52862
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:10402
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:10774
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F16_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:9238
Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHRREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:3495
Gcn3ISA::Decoder::decode_OP_VOP1__V_TRUNC_F64
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F64(MachInst)
Definition: decoder.cc:9316
Gcn3ISA::Decoder::decode_OP_VOP2__V_ASHRREV_I16
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:3501
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4(MachInst)
Definition: decoder.cc:7767
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:7227
Gcn3ISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64
Definition: instructions.hh:6244
Gcn3ISA::Inst_VOP3__V_CMPX_GT_F16
Definition: instructions.hh:33986
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst)
Definition: decoder.cc:7827
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:7527
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:4005
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F32
Definition: instructions.hh:35966
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:7503
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:5163
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_CL
Definition: instructions.hh:74946
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:7539
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:8074
Gcn3ISA::Decoder::decode_OP_SOP1__S_NOT_B32
GPUStaticInst * decode_OP_SOP1__S_NOT_B32(MachInst)
Definition: decoder.cc:8584
Gcn3ISA::Decoder::decode
GPUStaticInst * decode(MachInst mach_inst)
Definition: decoder.cc:3125
Gcn3ISA::Inst_DS__DS_WRITE_B96
Definition: instructions.hh:67002
Gcn3ISA::Inst_VOP3__V_MAX_U16
Definition: instructions.hh:48236
gpu_decoder.hh
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:72620
Gcn3ISA::Inst_VOP3__V_CMPX_GT_I16
Definition: instructions.hh:40322
Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I32
Definition: instructions.hh:42302
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst)
Definition: decoder.cc:7743
Gcn3ISA::Inst_VOPC__V_CMPX_LT_U64
Definition: instructions.hh:31638
Gcn3ISA::Inst_VOP3__V_DIV_SCALE_F32
Definition: instructions.hh:55226
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst)
Definition: decoder.cc:7323
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN3_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I32(MachInst)
Definition: decoder.cc:5955
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LDEXP_F32
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F32(MachInst)
Definition: decoder.cc:6231
Gcn3ISA::Inst_SOP2__S_SUB_U32
Definition: instructions.hh:112
Gcn3ISA::InstFormat
Definition: gpu_decoder.hh:1612
Gcn3ISA::InstFormat::iFmt_VOP3_SDST_ENC
InFmt_VOP3_SDST_ENC iFmt_VOP3_SDST_ENC
Definition: gpu_decoder.hh:1638
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:10138
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:4815
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_I16
GPUStaticInst * decode_OP_VOP2__V_MAX_I16(MachInst)
Definition: decoder.cc:3525
Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:8434
Gcn3ISA::Inst_SOP1__S_FF0_I32_B64
Definition: instructions.hh:5050
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
Definition: instructions.hh:73506
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:4317
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:10750
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U16(MachInst)
Definition: decoder.cc:4599
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:4353
Gcn3ISA::Inst_DS__DS_CONDXCHG32_RTN_B64
Definition: instructions.hh:64740
Gcn3ISA::Inst_SOPK__S_CMPK_LG_U32
Definition: instructions.hh:3490
Gcn3ISA::Decoder::decode_OP_SOP2__S_BFE_I64
GPUStaticInst * decode_OP_SOP2__S_BFE_I64(MachInst)
Definition: decoder.cc:3789
Gcn3ISA::Inst_SOPK__S_ADDK_I32
Definition: instructions.hh:3790
Gcn3ISA::Inst_VOP3__V_MAD_I16
Definition: instructions.hh:56120
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_C_L_O
Definition: instructions.hh:76314
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:4557
Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F16
Definition: instructions.hh:34514
Gcn3ISA::Inst_SOP2__S_NOR_B32
Definition: instructions.hh:1630
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:3261
Gcn3ISA::Decoder::decode_OP_SOP2__S_SUBB_U32
GPUStaticInst * decode_OP_SOP2__S_SUBB_U32(MachInst)
Definition: decoder.cc:3579
Gcn3ISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:72472
Gcn3ISA::Inst_VOP3__V_RSQ_F16
Definition: instructions.hh:52082
Gcn3ISA::Inst_VOP3__V_RCP_F16
Definition: instructions.hh:51962
Gcn3ISA::Inst_VOPC__V_CMPX_GT_F16
Definition: instructions.hh:21096
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
Definition: instructions.hh:70718
Gcn3ISA::Inst_MIMG__IMAGE_STORE_PCK
Definition: instructions.hh:73238
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_F32
GPUStaticInst * decode_OP_DS__DS_MAX_F32(MachInst)
Definition: decoder.cc:6441
Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F16
Definition: instructions.hh:52262
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:10792
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F32
Definition: instructions.hh:23016
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I32
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:5229
Gcn3ISA::Inst_VOP3__V_MAD_F16
Definition: instructions.hh:55976
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:4473
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:3999
Gcn3ISA::Inst_VOP3__V_CMPX_LE_I16
Definition: instructions.hh:40256
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:71584
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst)
Definition: decoder.cc:6087
Gcn3ISA::Inst_SOP2__S_BFM_B64
Definition: instructions.hh:2356
Gcn3ISA::Inst_VOPC__V_CMPX_GT_I16
Definition: instructions.hh:27232
Gcn3ISA::Inst_VOPC__V_CMP_EQ_U16
Definition: instructions.hh:26588
Gcn3ISA::Inst_VOPC__V_CMP_LT_F16
Definition: instructions.hh:19862
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_F64
GPUStaticInst * decode_OPU_VOP3__V_MUL_F64(MachInst)
Definition: decoder.cc:6189
Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I32
Definition: instructions.hh:29156
Gcn3ISA::Inst_VOP3__V_CMPX_LT_U64
Definition: instructions.hh:44876
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:10036
Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64
GPUStaticInst * decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst)
Definition: decoder.cc:6285
Gcn3ISA::Decoder::decode_OPU_VOP3__V_TRUNC_F16
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F16(MachInst)
Definition: decoder.cc:5811
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:9298
Gcn3ISA::Inst_VOP3__V_CMPX_LE_F16
Definition: instructions.hh:33920
Gcn3ISA::Inst_VOPC__V_CMP_LE_F64
Definition: instructions.hh:24082
Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_I64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_I64(MachInst)
Definition: decoder.cc:8686
Gcn3ISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B64(MachInst)
Definition: decoder.cc:8674
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I32(MachInst)
Definition: decoder.cc:6501
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FMA_F32
GPUStaticInst * decode_OPU_VOP3__V_FMA_F32(MachInst)
Definition: decoder.cc:5919
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:4959
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst)
Definition: decoder.cc:7701
Gcn3ISA::InstFormat::imm_u32
uint32_t imm_u32
Definition: gpu_decoder.hh:1642
Gcn3ISA::Inst_VOPC__V_CMP_EQ_F64
Definition: instructions.hh:24016
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8188
Gcn3ISA::Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8752
Gcn3ISA::Inst_VOP3__V_CMP_EQ_U16
Definition: instructions.hh:39662
Gcn3ISA::Inst_VOPC__V_CMP_LT_I16
Definition: instructions.hh:25994
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst)
Definition: decoder.cc:7215
Gcn3ISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst)
Definition: decoder.cc:9148
Gcn3ISA::Inst_VOPC__V_CMP_F_I64
Definition: instructions.hh:30024
Gcn3ISA::Decoder::decode_OP_SOPP__S_SENDMSGHALT
GPUStaticInst * decode_OP_SOPP__S_SENDMSGHALT(MachInst)
Definition: decoder.cc:9082
Gcn3ISA::Inst_DS__DS_READ2_B32
Definition: instructions.hh:61464
Gcn3ISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:5235
Gcn3ISA::Inst_SOP2__S_SUB_I32
Definition: instructions.hh:244
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_AND
Definition: instructions.hh:70214
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8344
Gcn3ISA::Inst_VOPC__V_CMP_LE_I64
Definition: instructions.hh:30222
Gcn3ISA::Inst_VOP3__V_CMP_LT_F16
Definition: instructions.hh:32732
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst)
Definition: decoder.cc:7449
Gcn3ISA::Inst_VOP1__V_LOG_F16
Definition: instructions.hh:18636
Gcn3ISA::Inst_VOP1__V_CEIL_F64
Definition: instructions.hh:16428
Gcn3ISA::Inst_VOP3__V_SIN_F16
Definition: instructions.hh:52682
Gcn3ISA::Inst_VOP3__V_ADDC_U32
Definition: instructions.hh:47078
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:9208
Gcn3ISA::Inst_VOPC__V_CMP_EQ_I64
Definition: instructions.hh:30156
Gcn3ISA::Inst_VOPC__V_CMP_F_F64
Definition: instructions.hh:23884
Gcn3ISA::Inst_VOP3__V_CMP_LE_F64
Definition: instructions.hh:37088
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:10198
Gcn3ISA::Inst_SOP2__S_ABSDIFF_I32
Definition: instructions.hh:2818
Gcn3ISA::Inst_SOP1__S_BREV_B64
Definition: instructions.hh:4690
Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B32(MachInst)
Definition: decoder.cc:6537
Gcn3ISA::Inst_VOP3__V_CMP_LT_I16
Definition: instructions.hh:39068
Gcn3ISA::Inst_VOP3__V_CMP_EQ_F64
Definition: instructions.hh:37022
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FLOOR_F16
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F16(MachInst)
Definition: decoder.cc:5799
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:10060
Gcn3ISA::Inst_VOP3__V_CMP_LE_I64
Definition: instructions.hh:43424
Gcn3ISA::Inst_VOP3__V_FLOOR_F64
Definition: instructions.hh:50054
Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE1
Definition: instructions.hh:49574
Gcn3ISA::Inst_SOPC__S_CMP_GT_I32
Definition: instructions.hh:7264
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:10144
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst)
Definition: decoder.cc:7935
Gcn3ISA::Inst_VOP3__V_CMP_EQ_I64
Definition: instructions.hh:43358
Gcn3ISA::Inst_VOP3__V_CVT_I32_F64
Definition: instructions.hh:48674
Gcn3ISA::Inst_VOPC__V_CMPX_LE_I16
Definition: instructions.hh:27170
Gcn3ISA::Decoder::subDecode_OP_FLAT
GPUStaticInst * subDecode_OP_FLAT(MachInst)
Definition: decoder.cc:3205
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8290
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:4329
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:9928
Gcn3ISA::Decoder::decode_OP_SOP1__S_SWAPPC_B64
GPUStaticInst * decode_OP_SOP1__S_SWAPPC_B64(MachInst)
Definition: decoder.cc:8740
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:3969
Gcn3ISA::Inst_SOP1__S_WQM_B64
Definition: instructions.hh:4570
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8194
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8350
Gcn3ISA::Decoder::decode_OPU_VOP3__V_WRITELANE_B32
GPUStaticInst * decode_OPU_VOP3__V_WRITELANE_B32(MachInst)
Definition: decoder.cc:6243
Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHRREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:3333
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD
Definition: instructions.hh:78402
Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORD
Definition: instructions.hh:10316
Gcn3ISA::Inst_SOP1__S_GETPC_B64
Definition: instructions.hh:5830
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst)
Definition: decoder.cc:7209
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:4965
Gcn3ISA::Decoder::decode_OP_SOPC__S_BITCMP0_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B32(MachInst)
Definition: decoder.cc:8932
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst)
Definition: decoder.cc:7689
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORD
Definition: instructions.hh:69182
Gcn3ISA::Inst_VOPC__V_CMPX_LE_F16
Definition: instructions.hh:21034
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8025
Gcn3ISA::Decoder::decode_OP_DS__DS_MIN_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U64(MachInst)
Definition: decoder.cc:6825
Gcn3ISA::Decoder::decode_OP_VOP2__V_ASHRREV_I32
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:3339
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F16(MachInst)
Definition: decoder.cc:9700
Gcn3ISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B32(MachInst)
Definition: decoder.cc:6993
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B64(MachInst)
Definition: decoder.cc:6879
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:5793
Gcn3ISA::Inst_VOP1__V_CVT_I32_F64
Definition: instructions.hh:15168
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:9280
Gcn3ISA::Inst_VOP3__V_CMPX_GE_F64
Definition: instructions.hh:38342
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:10510
Gcn3ISA::Inst_SOP1__S_BCNT0_I32_B32
Definition: instructions.hh:4750
Gcn3ISA::Inst_DS__DS_APPEND
Definition: instructions.hh:66072
Gcn3ISA::Inst_DS__DS_NOP
Definition: instructions.hh:59712
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F32(MachInst)
Definition: decoder.cc:6585
Gcn3ISA::Inst_VOP3__V_INTERP_P1_F32
Definition: instructions.hh:56502
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F64_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:9274
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_LG_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U32(MachInst)
Definition: decoder.cc:8902
Gcn3ISA::Inst_SOPP__S_CBRANCH_CDBGUSER
Definition: instructions.hh:9652
Gcn3ISA::Decoder::decode_OP_SOP2__S_ADD_I32
GPUStaticInst * decode_OP_SOP2__S_ADD_I32(MachInst)
Definition: decoder.cc:3561
Gcn3ISA::Inst_VOP3__V_CVT_FLR_I32_F32
Definition: instructions.hh:49274
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst)
Definition: decoder.cc:7695
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:4425
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:4089
Gcn3ISA::Decoder::decode_OP_VOP1__V_EXP_F16
GPUStaticInst * decode_OP_VOP1__V_EXP_F16(MachInst)
Definition: decoder.cc:9550
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_U32
GPUStaticInst * decode_OP_DS__DS_MAX_U32(MachInst)
Definition: decoder.cc:6375
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:10366
Gcn3ISA::InFmt_MIMG
Definition: gpu_decoder.hh:1411
Gcn3ISA::Inst_VOP3__V_CMPX_GE_I64
Definition: instructions.hh:44678
Gcn3ISA::Decoder::decode_OP_SOPP__S_NOP
GPUStaticInst * decode_OP_SOPP__S_NOP(MachInst)
Definition: decoder.cc:8980
Gcn3ISA::Decoder::decode_OPU_VOP3__V_RSQ_F16
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F16(MachInst)
Definition: decoder.cc:5769
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:72176
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:4947
Gcn3ISA::Inst_VOPC__V_CMP_LE_U16
Definition: instructions.hh:26654
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMOVK_I32
GPUStaticInst * decode_OP_SOPK__S_CMOVK_I32(MachInst)
Definition: decoder.cc:3819
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B32(MachInst)
Definition: decoder.cc:6999
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:4839
Gcn3ISA::Inst_VOP2__V_MAC_F32
Definition: instructions.hh:12954
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:3951
Gcn3ISA::Inst_VOPC__V_CMP_LT_F32
Definition: instructions.hh:21906
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN
Definition: instructions.hh:69998
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst)
Definition: decoder.cc:7605
Gcn3ISA::Inst_VOP3__V_CVT_F16_I16
Definition: instructions.hh:51782
Gcn3ISA::InstFormat::iFmt_VOP1
InFmt_VOP1 iFmt_VOP1
Definition: gpu_decoder.hh:1634
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
Definition: instructions.hh:78762
Gcn3ISA::Decoder::decode_OP_SOP1__S_WQM_B64
GPUStaticInst * decode_OP_SOP1__S_WQM_B64(MachInst)
Definition: decoder.cc:8602
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8374
Gcn3ISA::Inst_VOPC__V_CMPX_O_F32
Definition: instructions.hh:23326
Gcn3ISA::Inst_VOP3__V_CMP_LE_U16
Definition: instructions.hh:39728
Gcn3ISA::Inst_VOP3__V_MUL_HI_I32_I24
Definition: instructions.hh:45806
Gcn3ISA::Inst_VOP3__V_ADD_F64
Definition: instructions.hh:56910
Gcn3ISA::Inst_VOP3__V_CMP_NLE_F32
Definition: instructions.hh:35570
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:10720
Gcn3ISA::Inst_VOP3__V_CMPX_O_F32
Definition: instructions.hh:36296
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:10246
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
Definition: instructions.hh:70862
Gcn3ISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B32(MachInst)
Definition: decoder.cc:8620
Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F32
Definition: instructions.hh:36428
Gcn3ISA::Inst_VOP2__V_MAX_U16
Definition: instructions.hh:14670
Gcn3ISA::Inst_VOPC__V_CMP_LT_I32
Definition: instructions.hh:28042
Gcn3ISA::Inst_VOP3__V_LSHLREV_B64
Definition: instructions.hh:57834
Gcn3ISA::Decoder::decode_OP_SOPP__S_DECPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_DECPERFLEVEL(MachInst)
Definition: decoder.cc:9106
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
Definition: instructions.hh:71438
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:9868
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B64(MachInst)
Definition: decoder.cc:6753
Gcn3ISA::InFmt_VINTRP::OP
unsigned int OP
Definition: gpu_decoder.hh:1530
Gcn3ISA::Inst_VOP1__V_CVT_F16_I16
Definition: instructions.hh:18276
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F16(MachInst)
Definition: decoder.cc:4017
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:9808
Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F32
Definition: instructions.hh:32270
Gcn3ISA::Inst_VOP3__V_CMP_LT_F32
Definition: instructions.hh:34844
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:4749
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:10030
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:9646
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:4497
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst)
Definition: decoder.cc:7815
Gcn3ISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst)
Definition: decoder.cc:6051
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MSAD_U8
GPUStaticInst * decode_OPU_VOP3__V_MSAD_U8(MachInst)
Definition: decoder.cc:6069
Gcn3ISA::Inst_VOP3__V_BFE_I32
Definition: instructions.hh:53570
Gcn3ISA::Decoder::tableSubDecode_OP_SOPP
static IsaDecodeMethod tableSubDecode_OP_SOPP[128]
Definition: gpu_decoder.hh:73
Gcn3ISA::Inst_VOPC__V_CMPX_U_F64
Definition: instructions.hh:25432
Gcn3ISA::Inst_VOP3__V_FLOOR_F32
Definition: instructions.hh:50354
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:10150
Gcn3ISA::Inst_VOP3__V_CMPX_U_F64
Definition: instructions.hh:38474
Gcn3ISA::Inst_SOP2__S_AND_B32
Definition: instructions.hh:838
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:9814
Gcn3ISA::Inst_VOP3__V_CMP_LT_I32
Definition: instructions.hh:41180
Gcn3ISA::Inst_SOPK__S_CMPK_LG_I32
Definition: instructions.hh:3130
Gcn3ISA::Inst_VOPC__V_CMPX_GE_F64
Definition: instructions.hh:25308
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:70646
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:10456
Gcn3ISA::Inst_VOP3__V_LSHRREV_B64
Definition: instructions.hh:57900
Gcn3ISA::Inst_SOP2__S_ADD_U32
Definition: instructions.hh:46
Gcn3ISA::Inst_SOP2__S_CBRANCH_G_FORK
Definition: instructions.hh:2752
Gcn3ISA::Inst_DS__DS_MAX_I64
Definition: instructions.hh:62384
Gcn3ISA::Inst_SOPP__S_CBRANCH_VCCZ
Definition: instructions.hh:8668
Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8
Definition: instructions.hh:10180
Gcn3ISA::Inst_VOPC__V_CMPX_U_F32
Definition: instructions.hh:23388
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst)
Definition: decoder.cc:7749
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:10354
Gcn3ISA::Inst_VOPC__V_CMPX_GE_I64
Definition: instructions.hh:31452
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B128
GPUStaticInst * decode_OP_DS__DS_WRITE_B128(MachInst)
Definition: decoder.cc:7173
Gcn3ISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:7383
Gcn3ISA::Inst_VOP3__V_CMPX_U_F32
Definition: instructions.hh:36362
Gcn3ISA::Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6075
Gcn3ISA::Decoder::decode_OP_DS__DS_AND_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B64(MachInst)
Definition: decoder.cc:7131
Gcn3ISA::Decoder::decode_OPU_VOP3__V_FRACT_F32
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F32(MachInst)
Definition: decoder.cc:5571
Gcn3ISA::Inst_VOPC__V_CMP_GT_F64
Definition: instructions.hh:24148
Gcn3ISA::Decoder::decode_OP_SOP1__S_BREV_B64
GPUStaticInst * decode_OP_SOP1__S_BREV_B64(MachInst)
Definition: decoder.cc:8614
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:10252
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:4041
Gcn3ISA::Inst_SOPC__S_CMP_LG_U32
Definition: instructions.hh:7564
Gcn3ISA::Inst_DS__DS_OR_SRC2_B64
Definition: instructions.hh:66732
Gcn3ISA::Inst_VOP3__V_FMA_F16
Definition: instructions.hh:56292
Gcn3ISA::Decoder::decode_OP_VOP2__V_MAX_U16
GPUStaticInst * decode_OP_VOP2__V_MAX_U16(MachInst)
Definition: decoder.cc:3519
Gcn3ISA::Inst_DS__DS_MAX_F64
Definition: instructions.hh:63174
Gcn3ISA::Inst_VOP2__V_MAX_I16
Definition: instructions.hh:14736
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:10738
Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F16
Definition: instructions.hh:34646
Gcn3ISA::Inst_VOP3__V_CMP_NGT_F64
Definition: instructions.hh:37616
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MAX3_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F32(MachInst)
Definition: decoder.cc:5967
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8410
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B64(MachInst)
Definition: decoder.cc:7149
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U32(MachInst)
Definition: decoder.cc:6927
Gcn3ISA::Inst_VOP3__V_CMPX_LT_I64
Definition: instructions.hh:44348
Gcn3ISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:71732
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:4761
Gcn3ISA::Inst_DS__DS_GWS_SEMA_RELEASE_ALL
Definition: instructions.hh:65670
Gcn3ISA::Inst_VOPC__V_CMP_GT_I64
Definition: instructions.hh:30288
Gcn3ISA::Inst_DS__DS_MAX_RTN_U32
Definition: instructions.hh:60478
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B32(MachInst)
Definition: decoder.cc:6417
Gcn3ISA::Inst_VOPC__V_CMP_NGE_F64
Definition: instructions.hh:24478
Gcn3ISA::Inst_SOPP__S_SLEEP
Definition: instructions.hh:9112
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst)
Definition: decoder.cc:7941
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:4647
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP
Definition: instructions.hh:69638
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2_B64(MachInst)
Definition: decoder.cc:6747
Gcn3ISA::Inst_VOP3__V_MAD_U64_U32
Definition: instructions.hh:55820
Gcn3ISA::Inst_VOP3__V_CMPX_LT_F64
Definition: instructions.hh:38012
Gcn3ISA::Inst_VOP3__V_CMP_GT_F64
Definition: instructions.hh:37154
Gcn3ISA::Inst_VOP2__V_MAX_F16
Definition: instructions.hh:14538
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:4137
Gcn3ISA::Inst_VOP3__V_MAD_I32_I24
Definition: instructions.hh:53066
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst)
Definition: decoder.cc:7641
Gcn3ISA::Decoder::decode_OP_SOP2__S_LSHR_B32
GPUStaticInst * decode_OP_SOP2__S_LSHR_B32(MachInst)
Definition: decoder.cc:3729
Gcn3ISA::Inst_SOP2__S_ADD_I32
Definition: instructions.hh:178
Gcn3ISA::Decoder::decode_OP_SOPK__S_CMPK_LT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_U32(MachInst)
Definition: decoder.cc:3885
Gcn3ISA::Inst_VOPC__V_CMP_LE_U32
Definition: instructions.hh:28702
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst)
Definition: decoder.cc:6141
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:4911
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CUBEID_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEID_F32(MachInst)
Definition: decoder.cc:5877
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:4953
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:68130
Gcn3ISA::Inst_VOP3__V_CMP_GT_I64
Definition: instructions.hh:43490
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst)
Definition: decoder.cc:6297
Gcn3ISA::Decoder::tableSubDecode_OP_MUBUF
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128]
Definition: gpu_decoder.hh:69
Gcn3ISA::Decoder::decode_OP_VOP2__V_LSHLREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:3489
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:9682
Gcn3ISA::Inst_VOP3__V_CVT_I32_F32
Definition: instructions.hh:48974
Gcn3ISA::Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:8770
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:4755
Gcn3ISA::Inst_SOP2__S_XOR_B32
Definition: instructions.hh:1102
Gcn3ISA::Inst_DS__DS_BPERMUTE_B32
Definition: instructions.hh:61958
Gcn3ISA::Inst_VOPC__V_CMPX_O_F16
Definition: instructions.hh:21282
Gcn3ISA::Decoder::tableSubDecode_OP_VINTRP
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4]
Definition: gpu_decoder.hh:74
Gcn3ISA::Inst_VOP3__V_CMP_LE_U32
Definition: instructions.hh:41840
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_F32(MachInst)
Definition: decoder.cc:7017
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F64(MachInst)
Definition: decoder.cc:7161
Gcn3ISA::Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:5841
Gcn3ISA::Inst_VOP3__V_CMPX_O_F16
Definition: instructions.hh:34184
Gcn3ISA::Inst_VOPC__V_CMP_NLT_F16
Definition: instructions.hh:20720
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN_U16(MachInst)
Definition: decoder.cc:5397
Gcn3ISA::Inst_DS__DS_OR_B32
Definition: instructions.hh:59094
Gcn3ISA::Inst_SOPC__S_BITCMP0_B32
Definition: instructions.hh:7864
Gcn3ISA::Inst_MIMG__IMAGE_GATHER4_C_LZ_O
Definition: instructions.hh:78258
Gcn3ISA::Inst_VOP3__V_CEIL_F16
Definition: instructions.hh:52442
Gcn3ISA::Inst_DS__DS_CONSUME
Definition: instructions.hh:66012
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:5499
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:9862
Gcn3ISA::Inst_DS__DS_ADD_U32
Definition: instructions.hh:58494
Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_OR
Definition: instructions.hh:74034
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN
Definition: instructions.hh:69926
Gcn3ISA::Inst_VOP1__V_CVT_I32_F32
Definition: instructions.hh:15468
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:8128
Gcn3ISA::Decoder::decode_OP_DS__DS_GWS_SEMA_P
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_P(MachInst)
Definition: decoder.cc:7047
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB
Definition: instructions.hh:80128
Gcn3ISA::Decoder::decode_OP_DS__DS_DEC_U64
GPUStaticInst * decode_OP_DS__DS_DEC_U64(MachInst)
Definition: decoder.cc:6687
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN_F16(MachInst)
Definition: decoder.cc:5379
Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16
Definition: instructions.hh:10248
Gcn3ISA::Inst_VOP3__V_FLOOR_F16
Definition: instructions.hh:52382
Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F64
Definition: instructions.hh:38804
Gcn3ISA::Decoder::decode_OP_DS__DS_CMPST_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_F64(MachInst)
Definition: decoder.cc:6765
Gcn3ISA::Inst_VOPC__V_CMP_GE_U32
Definition: instructions.hh:28900
Gcn3ISA::Inst_VOPC__V_CMPX_LT_I64
Definition: instructions.hh:31142
Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F64
Definition: instructions.hh:19610
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:4275
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CLREXCP
GPUStaticInst * decode_OPU_VOP3__V_CLREXCP(MachInst)
Definition: decoder.cc:5727
Gcn3ISA::Inst_VOP3__V_CVT_PKNORM_U16_F32
Definition: instructions.hh:58230
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst)
Definition: decoder.cc:8254
Gcn3ISA::Inst_VOP3__V_CMPX_LG_F16
Definition: instructions.hh:34052
Gcn3ISA::Decoder::decode_OP_DS__DS_ORDERED_COUNT
GPUStaticInst * decode_OP_DS__DS_ORDERED_COUNT(MachInst)
Definition: decoder.cc:7071
Gcn3ISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8392
Gcn3ISA::Inst_VOPC__V_CMPX_LT_F64
Definition: instructions.hh:24998
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:4539
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:10642
Gcn3ISA::Decoder::decode_OPU_VOP3__V_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_U32(MachInst)
Definition: decoder.cc:5265
Gcn3ISA::InstFormat::iFmt_MTBUF
InFmt_MTBUF iFmt_MTBUF
Definition: gpu_decoder.hh:1622
Gcn3ISA::Decoder::decode_OP_SMEM__S_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORD(MachInst)
Definition: decoder.cc:8416
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst)
Definition: decoder.cc:7809
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:9676
Gcn3ISA::Inst_VOP3__V_CMP_GE_U32
Definition: instructions.hh:42038
Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F16
Definition: instructions.hh:33524
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX3
Definition: instructions.hh:69330
Gcn3ISA::Decoder::decode_OP_VOP2__V_MIN_I16
GPUStaticInst * decode_OP_VOP2__V_MIN_I16(MachInst)
Definition: decoder.cc:3537
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I32(MachInst)
Definition: decoder.cc:6963
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:9286
Gcn3ISA::Decoder::decode_OP_VINTRP__V_INTERP_P2_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:9166
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I64(MachInst)
Definition: decoder.cc:4935
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
Definition: instructions.hh:70790
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:9748
Gcn3ISA::Inst_SOPP__S_SETKILL
Definition: instructions.hh:8950
Gcn3ISA::Decoder::decode_OP_DS__DS_ADD_U64
GPUStaticInst * decode_OP_DS__DS_ADD_U64(MachInst)
Definition: decoder.cc:6663
Gcn3ISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:8049
Gcn3ISA::Decoder::decode_OP_DS__DS_WRITE_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_B64(MachInst)
Definition: decoder.cc:6741
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:4899
Gcn3ISA::Decoder::decode_OP_SOPC__S_CMP_GT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_U32(MachInst)
Definition: decoder.cc:8908
Gcn3ISA::Inst_VOP3__V_FFBH_U32
Definition: instructions.hh:51194
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:9940
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:4239
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:3291
Gcn3ISA::Inst_SOP1__S_BITSET0_B32
Definition: instructions.hh:5590
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst)
Definition: decoder.cc:6309
Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Definition: instructions.hh:80996
Gcn3ISA::Decoder::decode_OP_VOPC__V_CMP_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:10432
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:4431
Gcn3ISA::Inst_VOP3__V_MAC_F32
Definition: instructions.hh:46796
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:4029
Gcn3ISA::Decoder::decode_OP_SOP2__S_NOR_B64
GPUStaticInst * decode_OP_SOP2__S_NOR_B64(MachInst)
Definition: decoder.cc:3699
Gcn3ISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U64(MachInst)
Definition: decoder.cc:7125
Gcn3ISA::Inst_VINTRP__V_INTERP_MOV_F32
Definition: instructions.hh:32204
Gcn3ISA::Decoder::decode_OPU_VOP3__V_PERM_B32
GPUStaticInst * decode_OPU_VOP3__V_PERM_B32(MachInst)
Definition: decoder.cc:6123
Gcn3ISA::Inst_MIMG__IMAGE_SAMPLE_D
Definition: instructions.hh:74442
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst)
Definition: decoder.cc:7923
Gcn3ISA::Decoder::decode_OP_SOPP__S_BRANCH
GPUStaticInst * decode_OP_SOPP__S_BRANCH(MachInst)
Definition: decoder.cc:8992
Gcn3ISA::Inst_SOP2__S_ORN2_B64
Definition: instructions.hh:1432
Gcn3ISA::Decoder::decode_OP_SOP2__S_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_ADD_U32(MachInst)
Definition: decoder.cc:3549
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:4245
Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F64
Definition: instructions.hh:19544
Gcn3ISA::Inst_VOP3__V_CMP_U_F64
Definition: instructions.hh:37418
Gcn3ISA::Decoder::decode_OP_VOP1__V_CVT_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:9514
Gcn3ISA::Inst_DS__DS_PERMUTE_B32
Definition: instructions.hh:61892
Gcn3ISA::Decoder::decode_OP_VOP2__V_XOR_B32
GPUStaticInst * decode_OP_VOP2__V_XOR_B32(MachInst)
Definition: decoder.cc:3363
Gcn3ISA::Inst_VOP3__V_CVT_RPI_I32_F32
Definition: instructions.hh:49214
Gcn3ISA::Inst_VOPC__V_CMP_T_U16
Definition: instructions.hh:26918
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst)
Definition: decoder.cc:7761
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32(MachInst)
Definition: decoder.cc:6225
Gcn3ISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:68204
Gcn3ISA::Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:3279
Gcn3ISA::Inst_VOP3__V_SUBREV_U16
Definition: instructions.hh:47774
Gcn3ISA::Inst_VOP3__V_CVT_F16_U16
Definition: instructions.hh:51722
Gcn3ISA::Decoder::decode_OP_VOP1__V_TRUNC_F32
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F32(MachInst)
Definition: decoder.cc:9346
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:4263
Gcn3ISA::Decoder::decode_OP_DS__DS_INC_U32
GPUStaticInst * decode_OP_DS__DS_INC_U32(MachInst)
Definition: decoder.cc:6345
Gcn3ISA::Inst_VOPC__V_CMPX_LG_F16
Definition: instructions.hh:21158
Gcn3ISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:4857
Gcn3ISA::Inst_DS__DS_WRXCHG2ST64_RTN_B64
Definition: instructions.hh:64224
Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX2
Definition: instructions.hh:79366
Gcn3ISA::Decoder::decode_OPU_VOP3__V_MIN3_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U32(MachInst)
Definition: decoder.cc:5961
Gcn3ISA::Inst_MUBUF__BUFFER_ATOMIC_XOR
Definition: instructions.hh:70358
Gcn3ISA::Inst_VOP3__V_MBCNT_HI_U32_B32
Definition: instructions.hh:57768
Gcn3ISA::Inst_VOP3__V_MIN_U16
Definition: instructions.hh:48368
Gcn3ISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst)
Definition: decoder.cc:7869
Gcn3ISA::Decoder::decode_OP_SMEM__S_MEMTIME
GPUStaticInst * decode_OP_SMEM__S_MEMTIME(MachInst)
Definition: decoder.cc:8536

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