gem5
v20.1.0.0
arch
generic
isa.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright 2020 Google Inc.
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* Redistribution and use in source and binary forms, with or without
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*/
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#ifndef __ARCH_GENERIC_ISA_HH__
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#define __ARCH_GENERIC_ISA_HH__
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#include "
sim/sim_object.hh
"
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class
ThreadContext
;
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class
BaseISA
:
public
SimObject
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{
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protected
:
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using
SimObject::SimObject
;
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ThreadContext
*
tc
=
nullptr
;
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public
:
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virtual
void
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takeOverFrom
(
ThreadContext
*new_tc,
ThreadContext
*old_tc)
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{}
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virtual
void
setThreadContext
(
ThreadContext
*_tc) {
tc
= _tc; }
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};
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#endif // __ARCH_GENERIC_ISA_HH__
BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition:
isa.hh:59
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
sim_object.hh
BaseISA::tc
ThreadContext * tc
Definition:
isa.hh:52
BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition:
isa.hh:56
SimObject::SimObject
SimObject(const Params *_params)
Definition:
sim_object.cc:55
BaseISA
Definition:
isa.hh:47
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:92
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