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arm
generic_timer_miscregs_types.hh
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/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
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#define __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
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#include "
base/bitunion.hh
"
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namespace
ArmISA
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{
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BitUnion64
(CNTKCTL)
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// IF Armv8.6-ECV
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Bitfield<17> evntis;
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// ENDIF Armv8.6-ECV
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Bitfield<9>
el0pten
;
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Bitfield<8>
el0vten
;
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Bitfield<7,4>
evnti
;
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Bitfield<3>
evntdir
;
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Bitfield<2>
evnten
;
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Bitfield<1>
el0vcten
;
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Bitfield<0>
el0pcten
;
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EndBitUnion
(CNTKCTL)
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BitUnion64
(CNTHCTL)
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// IF Armv8.6-ECV
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Bitfield<17> evntis;
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Bitfield<16>
el1nvvct
;
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Bitfield<15>
el1nvpct
;
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Bitfield<14>
el1tvct
;
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Bitfield<13>
el1tvt
;
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Bitfield<12>
ecv
;
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// ENDIF Armv8.6-ECV
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Bitfield<7,4>
evnti
;
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Bitfield<3>
evntdir
;
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Bitfield<2>
evnten
;
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Bitfield<1>
el1pcen
;
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Bitfield<0>
el1pcten
;
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EndBitUnion
(CNTHCTL)
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// IF Armv8.1-VHE && HCR_EL2.E2H == 1
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BitUnion64
(CNTHCTL_E2H)
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// IF Armv8.6-ECV
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Bitfield<17> evntis;
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Bitfield<16>
el1nvvct
;
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Bitfield<15>
el1nvpct
;
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Bitfield<14>
el1tvct
;
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Bitfield<13>
el1tvt
;
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Bitfield<12>
ecv
;
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// ENDIF Armv8.6-ECV
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Bitfield<11>
el1pten
;
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Bitfield<10>
el1pcten
;
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Bitfield<9>
el0pten
;
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Bitfield<8>
el0vten
;
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Bitfield<7,4>
evnti
;
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Bitfield<3>
evntdir
;
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Bitfield<2>
evnten
;
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Bitfield<1>
el0vcten
;
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Bitfield<0>
el0pcten
;
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EndBitUnion
(CNTHCTL_E2H)
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// ENDIF Armv8.1-VHE && HCR_EL2.E2H == 1
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}
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#endif // __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
ArmISA::el1tvct
Bitfield< 14 > el1tvct
Definition:
generic_timer_miscregs_types.hh:63
ArmISA::EndBitUnion
EndBitUnion(CPSR) BitUnion64(AA64DFR0) Bitfield< 43
ArmISA::el0pten
Bitfield< 9 > el0pten
Definition:
generic_timer_miscregs_types.hh:49
ArmISA::el1tvt
Bitfield< 13 > el1tvt
Definition:
generic_timer_miscregs_types.hh:64
ArmISA
Definition:
ccregs.hh:41
ArmISA::evntdir
Bitfield< 3 > evntdir
Definition:
generic_timer_miscregs_types.hh:52
ArmISA::el0pcten
Bitfield< 0 > el0pcten
Definition:
generic_timer_miscregs_types.hh:55
bitunion.hh
ArmISA::evnten
Bitfield< 2 > evnten
Definition:
generic_timer_miscregs_types.hh:53
ArmISA::evnti
Bitfield< 7, 4 > evnti
Definition:
generic_timer_miscregs_types.hh:51
ArmISA::el0vten
Bitfield< 8 > el0vten
Definition:
generic_timer_miscregs_types.hh:50
ArmISA::ecv
ecv
Definition:
miscregs_types.hh:118
ArmISA::el1nvvct
Bitfield< 16 > el1nvvct
Definition:
generic_timer_miscregs_types.hh:61
ArmISA::el1pcten
Bitfield< 0 > el1pcten
Definition:
generic_timer_miscregs_types.hh:71
ArmISA::el1pten
Bitfield< 11 > el1pten
Definition:
generic_timer_miscregs_types.hh:83
ArmISA::el1pcen
Bitfield< 1 > el1pcen
Definition:
generic_timer_miscregs_types.hh:70
ArmISA::el1nvpct
Bitfield< 15 > el1nvpct
Definition:
generic_timer_miscregs_types.hh:62
ArmISA::BitUnion64
BitUnion64(CNTKCTL) Bitfield< 17 > evntis
ArmISA::el0vcten
Bitfield< 1 > el0vcten
Definition:
generic_timer_miscregs_types.hh:54
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