gem5  v20.1.0.0
gpu_static_inst.cc
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1 /*
2  * Copyright (c) 2015 Advanced Micro Devices, Inc.
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11  * this list of conditions and the following disclaimer.
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14  * this list of conditions and the following disclaimer in the documentation
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33 
35 
37  : executed_as(Enums::SC_NONE), _opcode(opcode),
38  _instNum(0), _instAddr(0), srcVecOperands(-1), dstVecOperands(-1),
39  srcVecDWORDs(-1), dstVecDWORDs(-1)
40 {
41 }
42 
43 const std::string&
45 {
46  if (disassembly.empty()) {
48  assert(!disassembly.empty());
49  }
50 
51  return disassembly;
52 }
53 
54 int
56 {
57  if (srcVecOperands > -1)
58  return srcVecOperands;
59 
60  srcVecOperands = 0;
61  if (!isScalar()) {
62  for (int k = 0; k < getNumOperands(); ++k) {
65  }
66  }
67  return srcVecOperands;
68 }
69 
70 int
72 {
73  if (dstVecOperands > -1)
74  return dstVecOperands;
75 
76  dstVecOperands = 0;
77  if (!isScalar()) {
78  for (int k = 0; k < getNumOperands(); ++k) {
81  }
82  }
83  return dstVecOperands;
84 }
85 
86 int
88 {
89  if (srcVecDWORDs > -1) {
90  return srcVecDWORDs;
91  }
92 
93  srcVecDWORDs = 0;
94  if (!isScalar()) {
95  for (int i = 0; i < getNumOperands(); i++) {
96  if (isVectorRegister(i) && isSrcOperand(i)) {
97  int dwords = numOpdDWORDs(i);
98  srcVecDWORDs += dwords;
99  }
100  }
101  }
102  return srcVecDWORDs;
103 }
104 
105 int
107 {
108  if (dstVecDWORDs > -1) {
109  return dstVecDWORDs;
110  }
111 
112  dstVecDWORDs = 0;
113  if (!isScalar()) {
114  for (int i = 0; i < getNumOperands(); i++) {
115  if (isVectorRegister(i) && isDstOperand(i)) {
116  int dwords = numOpdDWORDs(i);
117  dstVecDWORDs += dwords;
118  }
119  }
120  }
121  return dstVecDWORDs;
122 }
123 
124 int
126 {
127  return getOperandSize(operandIdx) <= 4 ? 1
128  : getOperandSize(operandIdx) / 4;
129 }
GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition: gpu_static_inst.cc:55
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
GPUStaticInst::getNumOperands
virtual int getNumOperands()=0
GPUStaticInst::GPUStaticInst
GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:36
gpu_static_inst.hh
GPUStaticInst::numOpdDWORDs
int numOpdDWORDs(int operandIdx)
Definition: gpu_static_inst.cc:125
GPUStaticInst::disassemble
const std::string & disassemble()
Definition: gpu_static_inst.cc:44
GPUStaticInst::isVectorRegister
virtual bool isVectorRegister(int operandIndex)=0
GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:261
MipsISA::k
Bitfield< 23 > k
Definition: dt_constants.hh:78
GPUStaticInst::isDstOperand
virtual bool isDstOperand(int operandIndex)=0
GPUStaticInst::dstVecDWORDs
int dstVecDWORDs
Definition: gpu_static_inst.hh:267
GPUStaticInst::isSrcOperand
virtual bool isSrcOperand(int operandIndex)=0
GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition: gpu_static_inst.cc:71
GPUStaticInst::getOperandSize
virtual int getOperandSize(int operandIndex)=0
GPUStaticInst::srcVecDWORDs
int srcVecDWORDs
Definition: gpu_static_inst.hh:266
ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:101
GPUStaticInst::isScalar
bool isScalar() const
Definition: gpu_static_inst.hh:139
GPUStaticInst::generateDisassembly
virtual void generateDisassembly()=0
GPUStaticInst::srcVecOperands
int srcVecOperands
Definition: gpu_static_inst.hh:264
GPUStaticInst::dstVecOperands
int dstVecOperands
Definition: gpu_static_inst.hh:265
sc_core::SC_NONE
@ SC_NONE
Definition: sc_report.hh:50
GPUStaticInst::numDstVecDWORDs
int numDstVecDWORDs()
Definition: gpu_static_inst.cc:106
GPUStaticInst::numSrcVecDWORDs
int numSrcVecDWORDs()
Definition: gpu_static_inst.cc:87

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