gem5
v20.1.0.0
gpu-compute
gpu_static_inst.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
gpu-compute/gpu_static_inst.hh
"
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GPUStaticInst::GPUStaticInst
(
const
std::string &
opcode
)
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: executed_as(Enums::
SC_NONE
), _opcode(
opcode
),
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_instNum(0), _instAddr(0), srcVecOperands(-1), dstVecOperands(-1),
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srcVecDWORDs(-1), dstVecDWORDs(-1)
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{
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}
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const
std::string&
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GPUStaticInst::disassemble
()
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{
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if
(
disassembly
.empty()) {
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generateDisassembly
();
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assert(!
disassembly
.empty());
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}
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return
disassembly
;
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}
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int
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GPUStaticInst::numSrcVecOperands
()
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{
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if
(
srcVecOperands
> -1)
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return
srcVecOperands
;
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srcVecOperands
= 0;
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if
(!
isScalar
()) {
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for
(
int
k
= 0;
k
<
getNumOperands
(); ++
k
) {
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if
(
isVectorRegister
(
k
) &&
isSrcOperand
(
k
))
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srcVecOperands
++;
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}
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}
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return
srcVecOperands
;
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}
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int
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GPUStaticInst::numDstVecOperands
()
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{
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if
(
dstVecOperands
> -1)
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return
dstVecOperands
;
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dstVecOperands
= 0;
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if
(!
isScalar
()) {
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for
(
int
k
= 0;
k
<
getNumOperands
(); ++
k
) {
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if
(
isVectorRegister
(
k
) &&
isDstOperand
(
k
))
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dstVecOperands
++;
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}
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}
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return
dstVecOperands
;
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}
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int
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GPUStaticInst::numSrcVecDWORDs
()
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{
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if
(
srcVecDWORDs
> -1) {
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return
srcVecDWORDs
;
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}
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srcVecDWORDs
= 0;
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if
(!
isScalar
()) {
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for
(
int
i
= 0;
i
<
getNumOperands
();
i
++) {
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if
(
isVectorRegister
(
i
) &&
isSrcOperand
(
i
)) {
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int
dwords =
numOpdDWORDs
(
i
);
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srcVecDWORDs
+= dwords;
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}
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}
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}
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return
srcVecDWORDs
;
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}
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int
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GPUStaticInst::numDstVecDWORDs
()
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{
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if
(
dstVecDWORDs
> -1) {
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return
dstVecDWORDs
;
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}
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dstVecDWORDs
= 0;
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if
(!
isScalar
()) {
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for
(
int
i
= 0;
i
<
getNumOperands
();
i
++) {
115
if
(
isVectorRegister
(
i
) &&
isDstOperand
(
i
)) {
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int
dwords =
numOpdDWORDs
(
i
);
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dstVecDWORDs
+= dwords;
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}
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}
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}
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return
dstVecDWORDs
;
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}
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int
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GPUStaticInst::numOpdDWORDs
(
int
operandIdx)
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{
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return
getOperandSize
(operandIdx) <= 4 ? 1
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:
getOperandSize
(operandIdx) / 4;
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}
GPUStaticInst::numSrcVecOperands
int numSrcVecOperands()
Definition:
gpu_static_inst.cc:55
ArmISA::i
Bitfield< 7 > i
Definition:
miscregs_types.hh:63
GPUStaticInst::getNumOperands
virtual int getNumOperands()=0
GPUStaticInst::GPUStaticInst
GPUStaticInst(const std::string &opcode)
Definition:
gpu_static_inst.cc:36
gpu_static_inst.hh
GPUStaticInst::numOpdDWORDs
int numOpdDWORDs(int operandIdx)
Definition:
gpu_static_inst.cc:125
GPUStaticInst::disassemble
const std::string & disassemble()
Definition:
gpu_static_inst.cc:44
GPUStaticInst::isVectorRegister
virtual bool isVectorRegister(int operandIndex)=0
GPUStaticInst::disassembly
std::string disassembly
Definition:
gpu_static_inst.hh:261
MipsISA::k
Bitfield< 23 > k
Definition:
dt_constants.hh:78
GPUStaticInst::isDstOperand
virtual bool isDstOperand(int operandIndex)=0
GPUStaticInst::dstVecDWORDs
int dstVecDWORDs
Definition:
gpu_static_inst.hh:267
GPUStaticInst::isSrcOperand
virtual bool isSrcOperand(int operandIndex)=0
GPUStaticInst::numDstVecOperands
int numDstVecOperands()
Definition:
gpu_static_inst.cc:71
GPUStaticInst::getOperandSize
virtual int getOperandSize(int operandIndex)=0
GPUStaticInst::srcVecDWORDs
int srcVecDWORDs
Definition:
gpu_static_inst.hh:266
ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition:
types.hh:101
GPUStaticInst::isScalar
bool isScalar() const
Definition:
gpu_static_inst.hh:139
GPUStaticInst::generateDisassembly
virtual void generateDisassembly()=0
GPUStaticInst::srcVecOperands
int srcVecOperands
Definition:
gpu_static_inst.hh:264
GPUStaticInst::dstVecOperands
int dstVecOperands
Definition:
gpu_static_inst.hh:265
sc_core::SC_NONE
@ SC_NONE
Definition:
sc_report.hh:50
GPUStaticInst::numDstVecDWORDs
int numDstVecDWORDs()
Definition:
gpu_static_inst.cc:106
GPUStaticInst::numSrcVecDWORDs
int numSrcVecDWORDs()
Definition:
gpu_static_inst.cc:87
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