gem5
v20.1.0.0
gpu-compute
gpu_exec_context.hh
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/*
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* Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GPU_EXEC_CONTEXT_HH__
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#define __GPU_EXEC_CONTEXT_HH__
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#include "arch/gpu_isa.hh"
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#include "
base/types.hh
"
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#include "config/the_gpu_isa.hh"
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class
ComputeUnit
;
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class
Wavefront
;
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class
GPUExecContext
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{
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public
:
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GPUExecContext
(
ComputeUnit
*_cu,
Wavefront
*_wf);
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Wavefront
*
wavefront
();
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ComputeUnit
*
computeUnit
();
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template
<
typename
T> T
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readConstVal
(
int
opIdx)
const
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{
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return
gpuISA
->readConstVal<T>(opIdx);
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}
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RegVal
readMiscReg
(
int
opIdx)
const
;
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void
writeMiscReg
(
int
opIdx,
RegVal
operandVal);
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protected
:
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ComputeUnit
*
cu
;
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Wavefront
*
wf
;
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TheGpuISA::GPUISA *
gpuISA
;
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};
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#endif // __GPU_EXEC_CONTEXT_HH__
GPUExecContext::readConstVal
T readConstVal(int opIdx) const
Definition:
gpu_exec_context.hh:52
GPUExecContext::wavefront
Wavefront * wavefront()
Definition:
gpu_exec_context.cc:49
ComputeUnit
Definition:
compute_unit.hh:198
GPUExecContext::wf
Wavefront * wf
Definition:
gpu_exec_context.hh:62
GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition:
gpu_exec_context.cc:55
GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition:
gpu_exec_context.hh:63
GPUExecContext::cu
ComputeUnit * cu
Definition:
gpu_exec_context.hh:61
types.hh
GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition:
gpu_exec_context.cc:62
Wavefront
Definition:
wavefront.hh:57
GPUExecContext
Definition:
gpu_exec_context.hh:44
GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition:
gpu_exec_context.cc:43
GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition:
gpu_exec_context.cc:37
RegVal
uint64_t RegVal
Definition:
types.hh:168
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