gem5  v20.1.0.0
gpu_exec_context.hh
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33 
34 #ifndef __GPU_EXEC_CONTEXT_HH__
35 #define __GPU_EXEC_CONTEXT_HH__
36 
37 #include "arch/gpu_isa.hh"
38 #include "base/types.hh"
39 #include "config/the_gpu_isa.hh"
40 
41 class ComputeUnit;
42 class Wavefront;
43 
45 {
46  public:
50 
51  template<typename T> T
52  readConstVal(int opIdx) const
53  {
54  return gpuISA->readConstVal<T>(opIdx);
55  }
56 
57  RegVal readMiscReg(int opIdx) const;
58  void writeMiscReg(int opIdx, RegVal operandVal);
59 
60  protected:
63  TheGpuISA::GPUISA *gpuISA;
64 };
65 
66 #endif // __GPU_EXEC_CONTEXT_HH__
GPUExecContext::readConstVal
T readConstVal(int opIdx) const
Definition: gpu_exec_context.hh:52
GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:49
ComputeUnit
Definition: compute_unit.hh:198
GPUExecContext::wf
Wavefront * wf
Definition: gpu_exec_context.hh:62
GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition: gpu_exec_context.cc:55
GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition: gpu_exec_context.hh:63
GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:61
types.hh
GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition: gpu_exec_context.cc:62
Wavefront
Definition: wavefront.hh:57
GPUExecContext
Definition: gpu_exec_context.hh:44
GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:43
GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition: gpu_exec_context.cc:37
RegVal
uint64_t RegVal
Definition: types.hh:168

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