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io_controller1.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  io_controller1.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /*
39 ############################################################################
40 # Siemens AG copyright 2000
41 # All Rights Reserved
42 #
43 # File name : io_controller.h
44 #
45 # Title : I/O-Controller
46 #
47 # Purpose : definitions for I/O-Controller-module
48 #
49 # Author : Hannes Muhr
50 # PSE EZE MSA
51 #
52 ##############################################################################
53 # Modification History :
54 #
55 #
56 ##############################################################################*/
57 
58 #ifndef IO_CONTROLLER_INC
59 #define IO_CONTROLLER_INC
60 
61 #ifdef LOGGING
62 #include <fstream>
63 #endif
64 #include "systemc.h"
65 
66 
67 #ifdef LOGGING
68 /* stream for logging */
69 extern ofstream flog;
70 #endif
71 
72 #define SCAN_INTERVAL 200000 // 200 us
73 #define NS *1e-9
74 
75 #define MII_FRAME_SIZE 400
76 
77 SC_MODULE(io_controller_m){
78 
79  /* ports */
80  sc_in_clk clk_i486_if;
81 
82  sc_out<sc_uint<30> > addr30_o1;
83  sc_out<sc_uint<30> > addr30_o2;
84  sc_inout<sc_uint<32> > data32_i;
85  sc_out<sc_uint<32> > data32_o1;
86  sc_out<sc_uint<32> > data32_o2;
87  sc_out<bool> ads_n_o1;
88  sc_out<bool> ads_n_o2;
89  sc_out<bool> wr_n_o1;
90  sc_out<bool> wr_n_o2;
91  sc_in<bool> rdy_n_i;
92  sc_in<bool> ar_i;
93  sc_in<bool> res_n_i;
94 
95  sc_out<sc_uint<4> > mii_data4_o;
96  sc_out<bool> mii_en_o;
97  sc_in<sc_uint<4> > mii_data4_i;
98  sc_in<bool> mii_en_i;
99  sc_in<bool> mii_coll_det;
100  sc_in_clk clk_mii;
101 
102  /* signals */
103  sc_signal<bool> start_mux;
104  sc_signal<bool> ready_mux;
105  sc_signal<bool> start_read;
106  sc_signal<bool> out_fifo_reset;
107 
108  /* variables */
109  sc_uint<32> addr_tx_frame_ptr;
110  sc_uint<32> rx_ptr_array;
111  sc_signal<bool> sem1; // mutual exclusion for i486-if
112  sc_signal<bool> sem2; // mutual exclusion for i486-if
113  sc_uint<32> shared_mem1[MII_FRAME_SIZE]; // for write
114  sc_uint<32> shared_mem2[MII_FRAME_SIZE]; // for read
115 
116  SC_CTOR(io_controller_m){
117 
118  SC_CTHREAD(control_write, clk_i486_if.pos());
119  //reset_signal_is(mii_coll_det, true);
120  reset_signal_is(res_n_i, false);
121 
122  SC_CTHREAD(control_read, clk_i486_if.pos());
123 
124  SC_CTHREAD(mux, clk_mii.pos());
125  SC_CTHREAD(shift, clk_mii.pos());
126 
127 
128  /* Initialize */
129  start_mux = 0;
130  ready_mux = 0;
131  start_read = 0;
132  out_fifo_reset = 0;
133 
134  sem1 = false;
135  sem2 = false;
136  // init shared memory
137  for (int i=0; i < MII_FRAME_SIZE; i++)
138  shared_mem1[i] = shared_mem2[i] = 0;
139  }
140  void control_write();
141  void control_read();
142  void mux();
143  void shift();
144  sc_uint<32> read_from_memory0(sc_uint<32>);
145  sc_uint<32> read_from_memory1(sc_uint<32>);
146  void write_into_memory0(sc_uint<32>, sc_uint<32>);
147  void write_into_memory1(sc_uint<32>, sc_uint<32>);
148 
149 };
150 
151 #endif
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
SC_CTOR
#define SC_CTOR(name)
Definition: sc_module.hh:293
SC_MODULE
SC_MODULE(io_controller_m)
Definition: io_controller1.h:77
MII_FRAME_SIZE
#define MII_FRAME_SIZE
Definition: io_controller1.h:75
ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:126
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319

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