gem5
v20.1.0.0
mem
probes
base.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
mem/probes/base.hh
"
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#include "params/BaseMemProbe.hh"
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BaseMemProbe::BaseMemProbe
(BaseMemProbeParams *
p
)
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:
SimObject
(
p
)
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{
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}
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void
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BaseMemProbe::regProbeListeners
()
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{
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const
BaseMemProbeParams *
p
(
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dynamic_cast<
const
BaseMemProbeParams *
>
(
params
()));
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assert(
p
);
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listeners
.resize(
p
->manager.size());
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for
(
int
i
= 0;
i
<
p
->manager.size();
i
++) {
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ProbeManager
*
const
mgr(
p
->manager[
i
]->getProbeManager());
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listeners
[
i
].reset(
new
PacketListener
(*
this
, mgr,
p
->probe_name));
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}
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}
ArmISA::i
Bitfield< 7 > i
Definition:
miscregs_types.hh:63
base.hh
BaseMemProbe::regProbeListeners
void regProbeListeners() override
Register probe listeners for this object.
Definition:
base.cc:48
BaseMemProbe::BaseMemProbe
BaseMemProbe(BaseMemProbeParams *params)
Definition:
base.cc:42
BaseMemProbe::PacketListener
Definition:
base.hh:75
SimObject::params
const Params * params() const
Definition:
sim_object.hh:119
ProbeManager
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
Definition:
probe.hh:150
BaseMemProbe::listeners
std::vector< std::unique_ptr< PacketListener > > listeners
Definition:
base.hh:91
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:92
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