gem5
v20.1.0.0
systemc
tests
systemc
misc
user_guide
param_model
param.h
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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/*****************************************************************************
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param.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/***************************************/
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/* Interface Filename: param.h */
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/***************************************/
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#include "
common.h
"
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SC_MODULE
( param )
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{
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SC_HAS_PROCESS
( param );
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sc_in_clk
clk;
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// Inputs
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const
sc_signal<bool>&
reset
;
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const
signal_bool_vector
&
a
;
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const
signal_bool_vector
&
b
;
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const
sc_signal<bool>& cin;
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const
sc_signal<bool>& ready;
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// Outputs
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signal_bool_vector
&
sum
;
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sc_signal<bool>& co;
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sc_signal<bool>& done;
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// Parameters
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const
int
data_width;
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// Constructor
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param (sc_module_name NAME,
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sc_clock& TICK,
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const
sc_signal<bool>& RESET,
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const
signal_bool_vector
& A,
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const
signal_bool_vector
& B,
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const
sc_signal<bool>& CIN,
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const
sc_signal<bool>& READY,
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signal_bool_vector
& SUM,
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sc_signal<bool>& CO,
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sc_signal<bool>& DONE,
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const
int
DATA_WIDTH = 4)
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:
reset
(RESET),
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a
(A),
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b
(B),
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cin (CIN),
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ready (READY),
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sum
(SUM),
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co (CO),
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done (DONE),
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data_width (DATA_WIDTH)
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{
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clk(TICK);
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SC_CTHREAD
( entry, clk.pos() );
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reset_signal_is(
reset
,
false
);
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}
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void
entry();
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};
RiscvISA::sum
Bitfield< 18 > sum
Definition:
registers.hh:609
Stats::reset
void reset()
Definition:
statistics.cc:569
SC_MODULE
SC_MODULE(param)
Definition:
param.h:44
ArmISA::a
Bitfield< 8 > a
Definition:
miscregs_types.hh:62
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition:
common.h:44
ArmISA::b
Bitfield< 7 > b
Definition:
miscregs_types.hh:376
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
common.h
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