gem5  v20.1.0.0
rdy.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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18  *****************************************************************************/
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20 /*****************************************************************************
21 
22  rdy.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "systemc.h"
39 
40 /******************************************************************************/
41 /*************************** rdy Function **********************/
42 /******************************************************************************/
43 
44 SC_MODULE( RDY )
45 {
46  SC_HAS_PROCESS( RDY );
47 
48  sc_in_clk clk;
49 
50  /*** Input and Output Ports ***/
51  sc_signal<bool>& data;
52 
53  /*** Constructor ***/
54  RDY ( sc_module_name NAME,
55  sc_clock& TICK_N,
56  sc_signal<bool>& DATA )
57 
58  :
59  data (DATA)
60 
61  {
62  clk (TICK_N);
63  SC_CTHREAD( entry, clk.neg() );
64  }
65 
66  /*** Call to Process Functionality ***/
67  void entry();
68 
69 };
70 
71 void
72 RDY::entry()
73 {
74  // IMPLICIT wait(); AT FIRST NEGEDGE
75  cout << sc_time_stamp() << " : " // Time 10
76  << "ready = " << data
77  << "\t\t (RDY) "
78  << endl;
79  data.write(0);
80 
81  wait(); // Time 30
82  cout << sc_time_stamp() << " : "
83  << "ready = " << data
84  << "\t\t (RDY) "
85  << endl;
86  data.write(1);
87 
88  wait(); // Time 50
89  cout << sc_time_stamp() << " : "
90  << "ready = " << data
91  << "\t\t (RDY) "
92  << endl;
93  data.write(0);
94 
95  wait(); // Time 70
96  cout << sc_time_stamp() << " : "
97  << "ready = " << data
98  << "\t\t (RDY) "
99  << endl;
100  data.write(1);
101 
102  wait(); // Time 90
103  cout << sc_time_stamp() << " : "
104  << "ready = " << data
105  << "\t\t (RDY) "
106  << endl;
107 
108  halt();
109 }
data
const char data[]
Definition: circlebuf.test.cc:42
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_core::wait
void wait()
Definition: sc_module.cc:653
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_MODULE
SC_MODULE(RDY)
Definition: rdy.h:44
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
MipsISA::halt
Bitfield< 26 > halt
Definition: dt_constants.hh:44
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:128
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