gem5
v20.1.0.0
systemc
tests
systemc
misc
synth
add_chain
reset_stim.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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reset_stim.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#include "
define.h
"
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/******************************************************************************/
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/*************************** reset_stim Function **********************/
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/******************************************************************************/
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bool_vector8
mem
[
LIMIT
+ 1];
// Stimulus input memory
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SC_MODULE
( RESET_STIM )
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{
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SC_HAS_PROCESS
( RESET_STIM );
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sc_in_clk
clk;
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/*** Input and Output Ports ***/
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sc_signal<bool>& ready;
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sc_signal<bool>&
reset
;
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sc_signal<int>&
addr
;
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/*** Constructor ***/
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RESET_STIM ( sc_module_name NAME,
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sc_clock& TICK_N,
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sc_signal<bool>& READY,
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sc_signal<bool>& RESET,
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sc_signal<int>& ADDR )
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:
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ready (READY),
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reset
(RESET),
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addr
(ADDR)
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{
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clk (TICK_N);
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SC_CTHREAD
( entry, clk.neg() );
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}
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/*** Call to Process Functionality ***/
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void
entry();
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};
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void
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RESET_STIM::entry()
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{
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// LOAD MEMORY WITH DATA AT TIME ZERO
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ifstream stimulus (
"add_chain/add_chain.dat"
);
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char
buffer[
WIDTH
+1];
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for
(
int
i
=1;
i
<
LIMIT
+1;
i
++) {
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stimulus >> buffer;
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mem
[
i
] = buffer;
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}
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stimulus.close();
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// INITIALIZE reset AND addr, THEN REMOVE RESET AFTER 2 CLOCK CYCLES
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reset
.write(0);
// reset = 0
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addr
.write(1);
// addr = 1
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wait
(2);
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reset
.write(1);
// reset = 1
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wait
();
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// WAIT FOR LAST MEMORY ADDRESS, THEN 3 CLOCKS, THEN STOP SIMULATION
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// do { wait(); } while (addr == LIMIT);
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do
{
wait
(); }
while
(!(
addr
==
LIMIT
));
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wait
(
LATENCY
);
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do
{
wait
(); }
while
(ready != 1);
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sc_stop
();
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halt
();
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}
ArmISA::i
Bitfield< 7 > i
Definition:
miscregs_types.hh:63
LIMIT
#define LIMIT
Definition:
define.h:40
Stats::reset
void reset()
Definition:
statistics.cc:569
sc_core::sc_stop
void sc_stop()
Definition:
sc_main.cc:104
LATENCY
#define LATENCY
Definition:
define.h:42
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
WIDTH
#define WIDTH
Definition:
define.h:41
define.h
mem
bool_vector8 mem[LIMIT+1]
Definition:
reset_stim.h:43
sc_core::wait
void wait()
Definition:
sc_module.cc:653
SC_MODULE
SC_MODULE(RESET_STIM)
Definition:
reset_stim.h:45
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
addr
ip6_addr_t addr
Definition:
inet.hh:423
bool_vector8
sc_bv< 8 > bool_vector8
Definition:
common.h:45
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
MipsISA::halt
Bitfield< 26 > halt
Definition:
dt_constants.hh:44
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