gem5  v20.1.0.0
fs_workload.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_RISCV_FS_WORKLOAD_HH__
31 #define __ARCH_RISCV_FS_WORKLOAD_HH__
32 
33 #include "params/RiscvFsWorkload.hh"
34 #include "sim/sim_object.hh"
35 #include "sim/workload.hh"
36 
37 namespace RiscvISA
38 {
39 
40 class FsWorkload : public Workload
41 {
42  protected:
43  // checker for bare metal application
45  // entry point for simulation
47 
48  public:
49  FsWorkload(RiscvFsWorkloadParams *p) : Workload(p),
50  _isBareMetal(p->bare_metal), _resetVect(p->reset_vect)
51  {}
52 
53  // return reset vector
54  Addr resetVect() const { return _resetVect; }
55 
56  // return bare metal checker
57  bool isBareMetal() const { return _isBareMetal; }
58 
59  Addr getEntry() const override { return _resetVect; }
60 };
61 
62 } // namespace RiscvISA
63 
64 #endif // __ARCH_RISCV_FS_WORKLOAD_HH__
RiscvISA::FsWorkload::_isBareMetal
bool _isBareMetal
Definition: fs_workload.hh:44
Workload
Definition: workload.hh:40
RiscvISA::FsWorkload
Definition: fs_workload.hh:40
RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
workload.hh
RiscvISA::FsWorkload::isBareMetal
bool isBareMetal() const
Definition: fs_workload.hh:57
RiscvISA
Definition: fs_workload.cc:36
sim_object.hh
RiscvISA::FsWorkload::FsWorkload
FsWorkload(RiscvFsWorkloadParams *p)
Definition: fs_workload.hh:49
RiscvISA::FsWorkload::getEntry
Addr getEntry() const override
Definition: fs_workload.hh:59
RiscvISA::FsWorkload::resetVect
Addr resetVect() const
Definition: fs_workload.hh:54
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
RiscvISA::FsWorkload::_resetVect
Addr _resetVect
Definition: fs_workload.hh:46

Generated on Wed Sep 30 2020 14:01:59 for gem5 by doxygen 1.8.17