gem5
v20.1.0.0
arch
riscv
fs_workload.hh
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_RISCV_FS_WORKLOAD_HH__
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#define __ARCH_RISCV_FS_WORKLOAD_HH__
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#include "params/RiscvFsWorkload.hh"
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#include "
sim/sim_object.hh
"
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#include "
sim/workload.hh
"
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namespace
RiscvISA
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{
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class
FsWorkload
:
public
Workload
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{
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protected
:
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// checker for bare metal application
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bool
_isBareMetal
;
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// entry point for simulation
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Addr
_resetVect
;
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public
:
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FsWorkload
(RiscvFsWorkloadParams *
p
) :
Workload
(
p
),
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_isBareMetal
(
p
->bare_metal),
_resetVect
(
p
->reset_vect)
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{}
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// return reset vector
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Addr
resetVect
()
const
{
return
_resetVect
; }
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// return bare metal checker
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bool
isBareMetal
()
const
{
return
_isBareMetal
; }
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Addr
getEntry
()
const override
{
return
_resetVect
; }
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};
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}
// namespace RiscvISA
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#endif // __ARCH_RISCV_FS_WORKLOAD_HH__
RiscvISA::FsWorkload::_isBareMetal
bool _isBareMetal
Definition:
fs_workload.hh:44
Workload
Definition:
workload.hh:40
RiscvISA::FsWorkload
Definition:
fs_workload.hh:40
RiscvISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
workload.hh
RiscvISA::FsWorkload::isBareMetal
bool isBareMetal() const
Definition:
fs_workload.hh:57
RiscvISA
Definition:
fs_workload.cc:36
sim_object.hh
RiscvISA::FsWorkload::FsWorkload
FsWorkload(RiscvFsWorkloadParams *p)
Definition:
fs_workload.hh:49
RiscvISA::FsWorkload::getEntry
Addr getEntry() const override
Definition:
fs_workload.hh:59
RiscvISA::FsWorkload::resetVect
Addr resetVect() const
Definition:
fs_workload.hh:54
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
RiscvISA::FsWorkload::_resetVect
Addr _resetVect
Definition:
fs_workload.hh:46
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