gem5  v20.1.0.0
pra_constants.hh
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28 
29 #ifndef __ARCH_RISCV_PRA_CONSTANTS_HH__
30 #define __ARCH_RISCV_PRA_CONSTANTS_HH__
31 
32 #include "arch/riscv/types.hh"
33 #include "base/bitunion.hh"
34 
35 namespace RiscvISA
36 {
37 
38 BitUnion32(IndexReg)
39  Bitfield<31> p;
40  // Need to figure out how to put in the TLB specific bits here
41  // For now, we assume that the entire length is used by the index
42  // field In reality, Index_HI = N-1, where
43  // N = Ceiling(log2(TLB Entries))
44  Bitfield<30, 0> index;
45 EndBitUnion(IndexReg)
46 
47 BitUnion32(RandomReg)
48  // This has a problem similar to the IndexReg index field. We'll keep
49  // both consistent at 30 for now
50  Bitfield<30, 0> random;
51 EndBitUnion(RandomReg)
52 
53 BitUnion64(EntryLoReg)
54  Bitfield<63, 30> fill;
55  Bitfield<29, 6> pfn; // Page frame number
56  Bitfield<5, 3> c; // Coherency attribute
57  Bitfield<2> d; // Dirty Bit
58  Bitfield<1> v; // Valid Bit
59  Bitfield<0> g; // Global Bit
60 EndBitUnion(EntryLoReg)
61 
62 BitUnion64(ContextReg)
63  Bitfield<63, 23> pteBase;
64  Bitfield<22, 4> badVPN2;
65  // Bits 3-0 are 0
66 EndBitUnion(ContextReg)
67 
68 BitUnion32(PageMaskReg)
69  // Bits 31-29 are 0
70  Bitfield<28, 13> mask;
71  Bitfield<12, 11> maskx;
72  // Bits 10-0 are zero
73 EndBitUnion(PageMaskReg)
74 
75 BitUnion32(PageGrainReg)
76  Bitfield<31, 30> aseUp;
77  Bitfield<29> elpa;
78  Bitfield<28> esp;
79  // Bits 27-13 are zeros
80  Bitfield<12, 8> aseDn;
81  // Bits 7-0 are zeros
82 EndBitUnion(PageGrainReg)
83 
84 BitUnion32(WiredReg)
85  // See note on Index register above
86  Bitfield<30, 0> wired;
87 EndBitUnion(WiredReg)
88 
89 BitUnion32(HWREnaReg)
90  Bitfield<31, 30> impl;
91  Bitfield<3, 0> mask;
92 EndBitUnion(HWREnaReg)
93 
94 BitUnion64(EntryHiReg)
95  Bitfield<63, 62> r;
96  Bitfield<61, 40> fill;
97  Bitfield<39, 13> vpn2;
98  Bitfield<12, 11> vpn2x;
99  Bitfield<7, 0> asid;
100 EndBitUnion(EntryHiReg)
101 
102 BitUnion32(StatusReg)
103  SubBitUnion(cu, 31, 28)
104  Bitfield<31> cu3;
105  Bitfield<30> cu2;
106  Bitfield<29> cu1;
107  Bitfield<28> cu0;
108  EndSubBitUnion(cu)
109  Bitfield<27> rp;
110  Bitfield<26> fr;
111  Bitfield<25> re;
112  Bitfield<24> mx;
113  Bitfield<23> px;
114  Bitfield<22> bev;
115  Bitfield<21> ts;
116  Bitfield<20> sr;
117  Bitfield<19> nmi;
118  // Bit 18 is zero
119  Bitfield<17, 16> impl;
120  Bitfield<15, 10> ipl;
121  SubBitUnion(im, 15, 8)
122  Bitfield<15> im7;
123  Bitfield<14> im6;
124  Bitfield<13> im5;
125  Bitfield<12> im4;
126  Bitfield<11> im3;
127  Bitfield<10> im2;
128  Bitfield<9> im1;
129  Bitfield<8> im0;
130  EndSubBitUnion(im)
131  Bitfield<7> kx;
132  Bitfield<6> sx;
133  Bitfield<5> ux;
134  Bitfield<4, 3> ksu;
135  Bitfield<4> um;
136  Bitfield<3> r0;
137  Bitfield<2> erl;
138  Bitfield<1> exl;
139  Bitfield<0> ie;
140 EndBitUnion(StatusReg)
141 
142 BitUnion32(IntCtlReg)
143  Bitfield<31, 29> ipti;
144  Bitfield<28, 26> ippci;
145  // Bits 26-10 are zeros
146  Bitfield<9, 5> vs;
147  // Bits 4-0 are zeros
148 EndBitUnion(IntCtlReg)
149 
150 BitUnion32(SRSCtlReg)
151  // Bits 31-30 are zeros
152  Bitfield<29, 26> hss;
153  // Bits 25-22 are zeros
154  Bitfield<21, 18> eicss;
155  // Bits 17-16 are zeros
156  Bitfield<15, 12> ess;
157  // Bits 11-10 are zeros
158  Bitfield<9, 6> pss;
159  // Bits 5-4 are zeros
160  Bitfield<3, 0> css;
161 EndBitUnion(SRSCtlReg)
162 
163 BitUnion32(SRSMapReg)
164  Bitfield<31, 28> ssv7;
165  Bitfield<27, 24> ssv6;
166  Bitfield<23, 20> ssv5;
167  Bitfield<19, 16> ssv4;
168  Bitfield<15, 12> ssv3;
169  Bitfield<11, 8> ssv2;
170  Bitfield<7, 4> ssv1;
171  Bitfield<3, 0> ssv0;
172 EndBitUnion(SRSMapReg)
173 
174 BitUnion32(CauseReg)
175  Bitfield<31> bd;
176  Bitfield<30> ti;
177  Bitfield<29, 28> ce;
178  Bitfield<27> dc;
179  Bitfield<26> pci;
180  // Bits 25-24 are zeros
181  Bitfield<23> iv;
182  Bitfield<22> wp;
183  // Bits 21-16 are zeros
184  Bitfield<15, 10> ripl;
185  SubBitUnion(ip, 15, 8)
186  Bitfield<15> ip7;
187  Bitfield<14> ip6;
188  Bitfield<13> ip5;
189  Bitfield<12> ip4;
190  Bitfield<11> ip3;
191  Bitfield<10> ip2;
192  Bitfield<9> ip1;
193  Bitfield<8> ip0;
195  // Bit 7 is zero
196  Bitfield<6, 2> excCode;
197  // Bits 1-0 are zeros
198 EndBitUnion(CauseReg)
199 
200 BitUnion32(PRIdReg)
201  Bitfield<31, 24> coOp;
202  Bitfield<23, 16> coId;
203  Bitfield<15, 8> procId;
204  Bitfield<7, 0> rev;
205 EndBitUnion(PRIdReg)
206 
207 BitUnion32(EBaseReg)
208  // Bit 31 is one
209  // Bit 30 is zero
210  Bitfield<29, 12> exceptionBase;
211  // Bits 11-10 are zeros
212  Bitfield<9, 9> cpuNum;
213 EndBitUnion(EBaseReg)
214 
215 BitUnion32(ConfigReg)
216  Bitfield<31> m;
217  Bitfield<30, 28> k23;
218  Bitfield<27, 25> ku;
219  Bitfield<24, 16> impl;
220  Bitfield<15> be;
221  Bitfield<14, 13> at;
222  Bitfield<12, 10> ar;
223  Bitfield<9, 7> mt;
224  // Bits 6-4 are zeros
225  Bitfield<3> vi;
226  Bitfield<2, 0> k0;
227 EndBitUnion(ConfigReg)
228 
229 BitUnion32(Config1Reg)
230  Bitfield<31> m;
231  Bitfield<30, 25> mmuSize;
232  Bitfield<24, 22> is;
233  Bitfield<21, 19> il;
234  Bitfield<18, 16> ia;
235  Bitfield<15, 13> ds;
236  Bitfield<12, 10> dl;
237  Bitfield<9, 7> da;
238  Bitfield<6> c2;
239  Bitfield<5> md;
240  Bitfield<4> pc;
241  Bitfield<3> wr;
242  Bitfield<2> ca;
243  Bitfield<1> ep;
244  Bitfield<0> fp;
245 EndBitUnion(Config1Reg)
246 
247 BitUnion32(Config2Reg)
248  Bitfield<31> m;
249  Bitfield<30, 28> tu;
250  Bitfield<27, 24> ts;
251  Bitfield<23, 20> tl;
252  Bitfield<19, 16> ta;
253  Bitfield<15, 12> su;
254  Bitfield<11, 8> ss;
255  Bitfield<7, 4> sl;
256  Bitfield<3, 0> sa;
257 EndBitUnion(Config2Reg)
258 
259 BitUnion32(Config3Reg)
260  Bitfield<31> m;
261  // Bits 30-11 are zeros
262  Bitfield<10> dspp;
263  // Bits 9-8 are zeros
264  Bitfield<7> lpa;
265  Bitfield<6> veic;
266  Bitfield<5> vint;
267  Bitfield<4> sp;
268  // Bit 3 is zero
269  Bitfield<2> mt;
270  Bitfield<1> sm;
271  Bitfield<0> tl;
272 EndBitUnion(Config3Reg)
273 
274 BitUnion64(WatchLoReg)
275  Bitfield<63, 3> vaddr;
276  Bitfield<2> i;
277  Bitfield<1> r;
278  Bitfield<0> w;
279 EndBitUnion(WatchLoReg)
280 
281 BitUnion32(WatchHiReg)
282  Bitfield<31> m;
283  Bitfield<30> g;
284  // Bits 29-24 are zeros
285  Bitfield<23, 16> asid;
286  // Bits 15-12 are zeros
287  Bitfield<11, 3> mask;
288  Bitfield<2> i;
289  Bitfield<1> r;
290  Bitfield<0> w;
291 EndBitUnion(WatchHiReg)
292 
293 BitUnion32(PerfCntCtlReg)
294  Bitfield<31> m;
295  Bitfield<30> w;
296  // Bits 29-11 are zeros
297  Bitfield<10, 5> event;
298  Bitfield<4> ie;
299  Bitfield<3> u;
300  Bitfield<2> s;
301  Bitfield<1> k;
302  Bitfield<0> exl;
303 EndBitUnion(PerfCntCtlReg)
304 
305 BitUnion32(CacheErrReg)
306  Bitfield<31> er;
307  Bitfield<30> ec;
308  Bitfield<29> ed;
309  Bitfield<28> et;
310  Bitfield<27> es;
311  Bitfield<26> ee;
312  Bitfield<25> eb;
313  Bitfield<24, 22> impl;
314  Bitfield<22, 0> index;
315 EndBitUnion(CacheErrReg)
316 
317 BitUnion32(TagLoReg)
318  Bitfield<31, 8> pTagLo;
319  Bitfield<7, 6> pState;
320  Bitfield<5> l;
321  Bitfield<4, 3> impl;
322  // Bits 2-1 are zeros
323  Bitfield<0> p;
324 EndBitUnion(TagLoReg)
325 
326 } // namespace RiscvISA
327 
328 #endif
RiscvISA::um
Bitfield< 4 > um
Definition: pra_constants.hh:135
RiscvISA::rev
Bitfield< 7, 0 > rev
Definition: pra_constants.hh:204
RiscvISA::ti
Bitfield< 30 > ti
Definition: pra_constants.hh:176
RiscvISA::erl
Bitfield< 2 > erl
Definition: pra_constants.hh:137
RiscvISA::tu
Bitfield< 30, 28 > tu
Definition: pra_constants.hh:249
RiscvISA::c
Bitfield< 5, 3 > c
Definition: pra_constants.hh:56
RiscvISA::sa
Bitfield< 3, 0 > sa
Definition: pra_constants.hh:256
RiscvISA::il
Bitfield< 21, 19 > il
Definition: pra_constants.hh:233
RiscvISA::pci
Bitfield< 26 > pci
Definition: pra_constants.hh:179
RiscvISA::cpuNum
Bitfield< 9, 9 > cpuNum
Definition: pra_constants.hh:212
RiscvISA::exl
Bitfield< 1 > exl
Definition: pra_constants.hh:138
RiscvISA::vpn2
Bitfield< 39, 13 > vpn2
Definition: pra_constants.hh:97
RiscvISA::ee
Bitfield< 26 > ee
Definition: pra_constants.hh:311
RiscvISA::im3
Bitfield< 11 > im3
Definition: pra_constants.hh:126
RiscvISA::aseDn
Bitfield< 12, 8 > aseDn
Definition: pra_constants.hh:80
RiscvISA::im4
Bitfield< 12 > im4
Definition: pra_constants.hh:125
RiscvISA::eicss
Bitfield< 21, 18 > eicss
Definition: pra_constants.hh:154
RiscvISA::hss
hss
Definition: pra_constants.hh:152
RiscvISA::at
Bitfield< 14, 13 > at
Definition: pra_constants.hh:221
RiscvISA::ssv1
Bitfield< 7, 4 > ssv1
Definition: pra_constants.hh:170
RiscvISA::k23
Bitfield< 30, 28 > k23
Definition: pra_constants.hh:217
RiscvISA::fp
Bitfield< 0 > fp
Definition: pra_constants.hh:244
RiscvISA::sl
Bitfield< 7, 4 > sl
Definition: pra_constants.hh:255
RiscvISA::fr
Bitfield< 26 > fr
Definition: pra_constants.hh:110
RiscvISA::w
Bitfield< 2 > w
Definition: pagetable.hh:70
RiscvISA::pteBase
pteBase
Definition: pra_constants.hh:63
RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
RiscvISA::ux
Bitfield< 5 > ux
Definition: pra_constants.hh:133
RiscvISA::sx
Bitfield< 6 > sx
Definition: pra_constants.hh:132
RiscvISA::ssv5
Bitfield< 23, 20 > ssv5
Definition: pra_constants.hh:166
RiscvISA::mmuSize
Bitfield< 30, 25 > mmuSize
Definition: pra_constants.hh:231
RiscvISA::SubBitUnion
SubBitUnion(im, 15, 8) Bitfield< 15 > im7
RiscvISA::lpa
Bitfield< 7 > lpa
Definition: pra_constants.hh:264
RiscvISA::mt
Bitfield< 9, 7 > mt
Definition: pra_constants.hh:223
RiscvISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:235
RiscvISA::g
Bitfield< 5 > g
Definition: pagetable.hh:66
RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
RiscvISA::random
random
Definition: pra_constants.hh:50
RiscvISA::excCode
Bitfield< 6, 2 > excCode
Definition: pra_constants.hh:196
RiscvISA::ip1
Bitfield< 9 > ip1
Definition: pra_constants.hh:192
RiscvISA::asid
Bitfield< 59, 44 > asid
Definition: pagetable.hh:43
RiscvISA::ce
Bitfield< 29, 28 > ce
Definition: pra_constants.hh:177
RiscvISA::pfn
Bitfield< 29, 6 > pfn
Definition: pra_constants.hh:55
RiscvISA::ssv0
Bitfield< 3, 0 > ssv0
Definition: pra_constants.hh:171
RiscvISA::su
Bitfield< 15, 12 > su
Definition: pra_constants.hh:253
RiscvISA::cu0
Bitfield< 28 > cu0
Definition: pra_constants.hh:107
RiscvISA::u
Bitfield< 4 > u
Definition: pagetable.hh:67
RiscvISA::sp
Bitfield< 4 > sp
Definition: pra_constants.hh:267
RiscvISA::im5
Bitfield< 13 > im5
Definition: pra_constants.hh:124
RiscvISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:297
RiscvISA::ssv4
Bitfield< 19, 16 > ssv4
Definition: pra_constants.hh:167
RiscvISA::maskx
Bitfield< 12, 11 > maskx
Definition: pra_constants.hh:71
RiscvISA
Definition: fs_workload.cc:36
RiscvISA::im0
Bitfield< 8 > im0
Definition: pra_constants.hh:129
RiscvISA::sm
Bitfield< 1 > sm
Definition: pra_constants.hh:270
RiscvISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:44
RiscvISA::vaddr
vaddr
Definition: pra_constants.hh:275
RiscvISA::ssv3
Bitfield< 15, 12 > ssv3
Definition: pra_constants.hh:168
RiscvISA::im2
Bitfield< 10 > im2
Definition: pra_constants.hh:127
RiscvISA::r0
Bitfield< 3 > r0
Definition: pra_constants.hh:136
RiscvISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:251
RiscvISA::ssv2
Bitfield< 11, 8 > ssv2
Definition: pra_constants.hh:169
RiscvISA::ip0
Bitfield< 8 > ip0
Definition: pra_constants.hh:193
RiscvISA::fill
fill
Definition: pra_constants.hh:54
RiscvISA::dc
Bitfield< 27 > dc
Definition: pra_constants.hh:178
RiscvISA::nmi
Bitfield< 19 > nmi
Definition: pra_constants.hh:117
RiscvISA::EndSubBitUnion
EndSubBitUnion(cu) Bitfield< 27 > rp
RiscvISA::is
Bitfield< 24, 22 > is
Definition: pra_constants.hh:232
RiscvISA::be
Bitfield< 15 > be
Definition: pra_constants.hh:220
RiscvISA::badVPN2
Bitfield< 22, 4 > badVPN2
Definition: pra_constants.hh:64
RiscvISA::ip6
Bitfield< 14 > ip6
Definition: pra_constants.hh:187
RiscvISA::ca
Bitfield< 2 > ca
Definition: pra_constants.hh:242
RiscvISA::ed
Bitfield< 29 > ed
Definition: pra_constants.hh:308
RiscvISA::md
Bitfield< 5 > md
Definition: pra_constants.hh:239
RiscvISA::eb
Bitfield< 25 > eb
Definition: pra_constants.hh:312
RiscvISA::ar
Bitfield< 12, 10 > ar
Definition: pra_constants.hh:222
RiscvISA::BitUnion64
BitUnion64(SATP) Bitfield< 63
bitunion.hh
types.hh
RiscvISA::bev
Bitfield< 22 > bev
Definition: pra_constants.hh:114
RiscvISA::ssv7
ssv7
Definition: pra_constants.hh:164
RiscvISA::pTagLo
pTagLo
Definition: pra_constants.hh:318
RiscvISA::vi
Bitfield< 3 > vi
Definition: pra_constants.hh:225
RiscvISA::wired
wired
Definition: pra_constants.hh:86
RiscvISA::elpa
Bitfield< 29 > elpa
Definition: pra_constants.hh:77
RiscvISA::wp
Bitfield< 22 > wp
Definition: pra_constants.hh:182
RiscvISA::cu2
Bitfield< 30 > cu2
Definition: pra_constants.hh:105
RiscvISA::ie
Bitfield< 0 > ie
Definition: pra_constants.hh:139
RiscvISA::veic
Bitfield< 6 > veic
Definition: pra_constants.hh:265
RiscvISA::ip5
Bitfield< 13 > ip5
Definition: pra_constants.hh:188
RiscvISA::vs
Bitfield< 9, 5 > vs
Definition: pra_constants.hh:146
RiscvISA::coOp
coOp
Definition: pra_constants.hh:201
RiscvISA::procId
Bitfield< 15, 8 > procId
Definition: pra_constants.hh:203
RiscvISA::px
Bitfield< 23 > px
Definition: pra_constants.hh:113
RiscvISA::css
Bitfield< 3, 0 > css
Definition: pra_constants.hh:160
RiscvISA::im1
Bitfield< 9 > im1
Definition: pra_constants.hh:128
RiscvISA::k0
Bitfield< 2, 0 > k0
Definition: pra_constants.hh:226
RiscvISA::ta
Bitfield< 19, 16 > ta
Definition: pra_constants.hh:252
RiscvISA::re
Bitfield< 25 > re
Definition: pra_constants.hh:111
RiscvISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:320
RiscvISA::exceptionBase
exceptionBase
Definition: pra_constants.hh:210
RiscvISA::pss
Bitfield< 9, 6 > pss
Definition: pra_constants.hh:158
RiscvISA::v
Bitfield< 0 > v
Definition: pagetable.hh:72
RiscvISA::ipti
ipti
Definition: pra_constants.hh:143
RiscvISA::wr
Bitfield< 3 > wr
Definition: pra_constants.hh:241
RiscvISA::mx
Bitfield< 24 > mx
Definition: pra_constants.hh:112
RiscvISA::da
Bitfield< 9, 7 > da
Definition: pra_constants.hh:237
RiscvISA::cu1
Bitfield< 29 > cu1
Definition: pra_constants.hh:106
RiscvISA::mask
mask
Definition: pra_constants.hh:70
RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:276
RiscvISA::BitUnion32
BitUnion32(IndexReg) Bitfield< 31 > p
RiscvISA::dspp
Bitfield< 10 > dspp
Definition: pra_constants.hh:262
RiscvISA::EndBitUnion
EndBitUnion(SATP) enum AddrXlateMode
Definition: pagetable.hh:45
RiscvISA::ippci
Bitfield< 28, 26 > ippci
Definition: pra_constants.hh:144
RiscvISA::vpn2x
Bitfield< 12, 11 > vpn2x
Definition: pra_constants.hh:98
RiscvISA::pState
Bitfield< 7, 6 > pState
Definition: pra_constants.hh:319
RiscvISA::ssv6
Bitfield< 27, 24 > ssv6
Definition: pra_constants.hh:165
RiscvISA::vint
Bitfield< 5 > vint
Definition: pra_constants.hh:266
RiscvISA::ip2
Bitfield< 10 > ip2
Definition: pra_constants.hh:191
iGbReg::TxdOp::ip
bool ip(TxDesc *d)
Definition: i8254xGBe_defs.hh:261
RiscvISA::dl
Bitfield< 12, 10 > dl
Definition: pra_constants.hh:236
RiscvISA::esp
Bitfield< 28 > esp
Definition: pra_constants.hh:78
RiscvISA::ipl
Bitfield< 15, 10 > ipl
Definition: pra_constants.hh:120
RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:71
RiscvISA::cu3
Bitfield< 31 > cu3
Definition: pra_constants.hh:103
RiscvISA::ku
Bitfield< 27, 25 > ku
Definition: pra_constants.hh:218
RiscvISA::coId
Bitfield< 23, 16 > coId
Definition: pra_constants.hh:202
RiscvISA::es
Bitfield< 27 > es
Definition: pra_constants.hh:310
RiscvISA::ip4
Bitfield< 12 > ip4
Definition: pra_constants.hh:189
RiscvISA::aseUp
aseUp
Definition: pra_constants.hh:76
RiscvISA::ripl
Bitfield< 15, 10 > ripl
Definition: pra_constants.hh:184
RiscvISA::im6
Bitfield< 14 > im6
Definition: pra_constants.hh:123
RiscvISA::k
Bitfield< 1 > k
Definition: pra_constants.hh:301
RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:254
RiscvISA::impl
impl
Definition: pra_constants.hh:90
RiscvISA::c2
Bitfield< 6 > c2
Definition: pra_constants.hh:238
RiscvISA::et
Bitfield< 28 > et
Definition: pra_constants.hh:309
RiscvISA::ess
Bitfield< 15, 12 > ess
Definition: pra_constants.hh:156
RiscvISA::s
Bitfield< 2 > s
Definition: pra_constants.hh:300
RiscvISA::ep
Bitfield< 1 > ep
Definition: pra_constants.hh:243
RiscvISA::d
Bitfield< 7 > d
Definition: pagetable.hh:64
RiscvISA::ia
Bitfield< 18, 16 > ia
Definition: pra_constants.hh:234
RiscvISA::iv
Bitfield< 23 > iv
Definition: pra_constants.hh:181
RiscvISA::ec
Bitfield< 30 > ec
Definition: pra_constants.hh:307
RiscvISA::sr
Bitfield< 20 > sr
Definition: pra_constants.hh:116
RiscvISA::ksu
Bitfield< 4, 3 > ksu
Definition: pra_constants.hh:134
PowerISA::bd
Bitfield< 15, 2 > bd
Definition: types.hh:61
RiscvISA::ip3
Bitfield< 11 > ip3
Definition: pra_constants.hh:190
ArmISA::m
Bitfield< 0 > m
Definition: miscregs_types.hh:389
RiscvISA::ts
Bitfield< 21 > ts
Definition: pra_constants.hh:115

Generated on Wed Sep 30 2020 14:02:07 for gem5 by doxygen 1.8.17