gem5
v20.1.0.0
sim
port.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2011-2012,2015,2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
sim/port.hh
"
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#include "
base/logging.hh
"
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Port::Port
(
const
std::string& _name,
PortID
_id) :
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portName(_name),
id
(_id), _peer(nullptr), _connected(false)
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{}
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Port::~Port
() {}
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void
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Port::reportUnbound
()
const
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{
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fatal
(
"%s: Unconnected port!"
,
name
());
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}
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition:
logging.hh:183
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition:
types.hh:237
Port::Port
Port(const std::string &_name, PortID _id)
Abstract base class for ports.
Definition:
port.cc:50
Port::reportUnbound
void reportUnbound() const
Definition:
port.cc:57
Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition:
port.hh:106
port.hh
logging.hh
ArmISA::id
Bitfield< 33 > id
Definition:
miscregs_types.hh:247
Port::~Port
virtual ~Port()
Virtual destructor due to inheritance.
Definition:
port.cc:53
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