gem5  v20.1.0.0
simple_indirect.cc
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28 
30 
31 #include "base/intmath.hh"
32 #include "debug/Indirect.hh"
33 
35  const SimpleIndirectPredictorParams * params)
36  : IndirectPredictor(params),
37  hashGHR(params->indirectHashGHR),
38  hashTargets(params->indirectHashTargets),
39  numSets(params->indirectSets),
40  numWays(params->indirectWays),
41  tagBits(params->indirectTagSize),
42  pathLength(params->indirectPathLength),
43  instShift(params->instShiftAmt),
44  ghrNumBits(params->indirectGHRBits),
45  ghrMask((1 << params->indirectGHRBits)-1)
46 {
47  if (!isPowerOf2(numSets)) {
48  panic("Indirect predictor requires power of 2 number of sets");
49  }
50 
51  threadInfo.resize(params->numThreads);
52 
53  targetCache.resize(numSets);
54  for (unsigned i = 0; i < numSets; i++) {
55  targetCache[i].resize(numWays);
56  }
57 
58  fatal_if(ghrNumBits > (sizeof(ThreadInfo::ghr)*8), "ghr_size is too big");
59 }
60 
61 void
63  void* & indirect_history)
64 {
65  // record the GHR as it was before this prediction
66  // It will be used to recover the history in case this prediction is
67  // wrong or belongs to bad path
68  indirect_history = new unsigned(threadInfo[tid].ghr);
69 }
70 
71 void
73  ThreadID tid, bool actually_taken)
74 {
75  threadInfo[tid].ghr <<= 1;
76  threadInfo[tid].ghr |= actually_taken;
77  threadInfo[tid].ghr &= ghrMask;
78 }
79 
80 void
82  void * indirect_history, bool actually_taken)
83 {
84  unsigned * previousGhr = static_cast<unsigned *>(indirect_history);
85  threadInfo[tid].ghr = ((*previousGhr) << 1) + actually_taken;
86  threadInfo[tid].ghr &= ghrMask;
87 }
88 
89 bool
91  ThreadID tid)
92 {
93  Addr set_index = getSetIndex(br_addr, threadInfo[tid].ghr, tid);
94  Addr tag = getTag(br_addr);
95 
96  assert(set_index < numSets);
97 
98  DPRINTF(Indirect, "Looking up %x (set:%d)\n", br_addr, set_index);
99  const auto &iset = targetCache[set_index];
100  for (auto way = iset.begin(); way != iset.end(); ++way) {
101  if (way->tag == tag) {
102  DPRINTF(Indirect, "Hit %x (target:%s)\n", br_addr, way->target);
103  target = way->target;
104  return true;
105  }
106  }
107  DPRINTF(Indirect, "Miss %x\n", br_addr);
108  return false;
109 }
110 
111 void
113  InstSeqNum seq_num, ThreadID tid)
114 {
115  DPRINTF(Indirect, "Recording %x seq:%d\n", br_addr, seq_num);
116  HistoryEntry entry(br_addr, tgt_addr, seq_num);
117  threadInfo[tid].pathHist.push_back(entry);
118 }
119 
120 void
122  void * indirect_history)
123 {
124  DPRINTF(Indirect, "Committing seq:%d\n", seq_num);
125  ThreadInfo &t_info = threadInfo[tid];
126 
127  // we do not need to recover the GHR, so delete the information
128  unsigned * previousGhr = static_cast<unsigned *>(indirect_history);
129  delete previousGhr;
130 
131  if (t_info.pathHist.empty()) return;
132 
133  if (t_info.headHistEntry < t_info.pathHist.size() &&
134  t_info.pathHist[t_info.headHistEntry].seqNum <= seq_num) {
135  if (t_info.headHistEntry >= pathLength) {
136  t_info.pathHist.pop_front();
137  } else {
138  ++t_info.headHistEntry;
139  }
140  }
141 }
142 
143 void
145 {
146  DPRINTF(Indirect, "Squashing seq:%d\n", seq_num);
147  ThreadInfo &t_info = threadInfo[tid];
148  auto squash_itr = t_info.pathHist.begin();
149  while (squash_itr != t_info.pathHist.end()) {
150  if (squash_itr->seqNum > seq_num) {
151  break;
152  }
153  ++squash_itr;
154  }
155  if (squash_itr != t_info.pathHist.end()) {
156  DPRINTF(Indirect, "Squashing series starting with sn:%d\n",
157  squash_itr->seqNum);
158  }
159  t_info.pathHist.erase(squash_itr, t_info.pathHist.end());
160 }
161 
162 void
164  void * indirect_history)
165 {
166  unsigned * previousGhr = static_cast<unsigned *>(indirect_history);
167  threadInfo[tid].ghr = *previousGhr;
168 
169  delete previousGhr;
170 }
171 
172 void
174  InstSeqNum seq_num, void * indirect_history, const TheISA::PCState& target,
175  ThreadID tid)
176 {
177  ThreadInfo &t_info = threadInfo[tid];
178 
179  unsigned * ghr = static_cast<unsigned *>(indirect_history);
180 
181  // Should have just squashed so this branch should be the oldest
182  auto hist_entry = *(t_info.pathHist.rbegin());
183  // Temporarily pop it off the history so we can calculate the set
184  t_info.pathHist.pop_back();
185  Addr set_index = getSetIndex(hist_entry.pcAddr, *ghr, tid);
186  Addr tag = getTag(hist_entry.pcAddr);
187  hist_entry.targetAddr = target.instAddr();
188  t_info.pathHist.push_back(hist_entry);
189 
190  assert(set_index < numSets);
191 
192  auto &iset = targetCache[set_index];
193  for (auto way = iset.begin(); way != iset.end(); ++way) {
194  if (way->tag == tag) {
195  DPRINTF(Indirect, "Updating Target (seq: %d br:%x set:%d target:"
196  "%s)\n", seq_num, hist_entry.pcAddr, set_index, target);
197  way->target = target;
198  return;
199  }
200  }
201 
202  DPRINTF(Indirect, "Allocating Target (seq: %d br:%x set:%d target:%s)\n",
203  seq_num, hist_entry.pcAddr, set_index, target);
204  // Did not find entry, random replacement
205  auto &way = iset[rand() % numWays];
206  way.tag = tag;
207  way.target = target;
208 }
209 
210 
211 inline Addr
213 {
214  ThreadInfo &t_info = threadInfo[tid];
215 
216  Addr hash = br_addr >> instShift;
217  if (hashGHR) {
218  hash ^= ghr;
219  }
220  if (hashTargets) {
221  unsigned hash_shift = floorLog2(numSets) / pathLength;
222  for (int i = t_info.pathHist.size()-1, p = 0;
223  i >= 0 && p < pathLength; i--, p++) {
224  hash ^= (t_info.pathHist[i].targetAddr >>
225  (instShift + p*hash_shift));
226  }
227  }
228  return hash & (numSets-1);
229 }
230 
231 inline Addr
233 {
234  return (br_addr >> instShift) & ((0x1<<tagBits)-1);
235 }
236 
238 SimpleIndirectPredictorParams::create()
239 {
240  return new SimpleIndirectPredictor(this);
241 }
SimpleIndirectPredictor::ghrNumBits
const unsigned ghrNumBits
Definition: simple_indirect.hh:65
SimpleIndirectPredictor::ThreadInfo
Definition: simple_indirect.hh:90
SimpleIndirectPredictor::getTag
Addr getTag(Addr br_addr)
Definition: simple_indirect.cc:232
SimpleIndirectPredictor::numSets
const unsigned numSets
Definition: simple_indirect.hh:60
SimpleIndirectPredictor::getSetIndex
Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid)
Definition: simple_indirect.cc:212
SimpleIndirectPredictor::HistoryEntry
Definition: simple_indirect.hh:80
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
SimpleIndirectPredictor::instShift
const unsigned instShift
Definition: simple_indirect.hh:64
SimpleIndirectPredictor::targetCache
std::vector< std::vector< IPredEntry > > targetCache
Definition: simple_indirect.hh:75
IndirectPredictor
Definition: indirect.hh:38
SimpleIndirectPredictor::tagBits
const unsigned tagBits
Definition: simple_indirect.hh:62
floorLog2
std::enable_if< std::is_integral< T >::value, int >::type floorLog2(T x)
Definition: intmath.hh:63
SimpleIndirectPredictor::hashTargets
const bool hashTargets
Definition: simple_indirect.hh:59
SimpleIndirectPredictor::genIndirectInfo
void genIndirectInfo(ThreadID tid, void *&indirect_history)
Definition: simple_indirect.cc:62
SimpleIndirectPredictor::commit
void commit(InstSeqNum seq_num, ThreadID tid, void *indirect_history)
Definition: simple_indirect.cc:121
SimpleIndirectPredictor::ThreadInfo::ghr
unsigned ghr
Definition: simple_indirect.hh:95
SimpleIndirectPredictor::ghrMask
const unsigned ghrMask
Definition: simple_indirect.hh:66
SimpleIndirectPredictor::hashGHR
const bool hashGHR
Definition: simple_indirect.hh:58
SimpleIndirectPredictor::lookup
bool lookup(Addr br_addr, TheISA::PCState &br_target, ThreadID tid)
Definition: simple_indirect.cc:90
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
SimpleIndirectPredictor::threadInfo
std::vector< ThreadInfo > threadInfo
Definition: simple_indirect.hh:98
SimpleIndirectPredictor::ThreadInfo::headHistEntry
unsigned headHistEntry
Definition: simple_indirect.hh:94
simple_indirect.hh
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
SimObject::params
const Params * params() const
Definition: sim_object.hh:119
SimpleIndirectPredictor::updateDirectionInfo
void updateDirectionInfo(ThreadID tid, bool actually_taken)
Definition: simple_indirect.cc:72
SimpleIndirectPredictor::numWays
const unsigned numWays
Definition: simple_indirect.hh:61
SimpleIndirectPredictor::recordTarget
void recordTarget(InstSeqNum seq_num, void *indirect_history, const TheISA::PCState &target, ThreadID tid)
Definition: simple_indirect.cc:173
SimpleIndirectPredictor::deleteIndirectInfo
void deleteIndirectInfo(ThreadID tid, void *indirect_history)
Definition: simple_indirect.cc:163
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
SimpleIndirectPredictor::recordIndirect
void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, ThreadID tid)
Definition: simple_indirect.cc:112
SimpleIndirectPredictor::SimpleIndirectPredictor
SimpleIndirectPredictor(const SimpleIndirectPredictorParams *params)
Definition: simple_indirect.cc:34
SimpleIndirectPredictor::squash
void squash(InstSeqNum seq_num, ThreadID tid)
Definition: simple_indirect.cc:144
SimpleIndirectPredictor::changeDirectionPrediction
void changeDirectionPrediction(ThreadID tid, void *indirect_history, bool actually_taken)
Definition: simple_indirect.cc:81
SimpleIndirectPredictor::ThreadInfo::pathHist
std::deque< HistoryEntry > pathHist
Definition: simple_indirect.hh:93
SimpleIndirectPredictor::pathLength
const unsigned pathLength
Definition: simple_indirect.hh:63
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
intmath.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:219
isPowerOf2
bool isPowerOf2(const T &n)
Definition: intmath.hh:102
SimpleIndirectPredictor
Definition: simple_indirect.hh:39
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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