gem5  v20.1.0.0
stim.h
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20 /*****************************************************************************
21 
22  stim.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /******************************************************************************/
39 /*************************** stimulus Class Definition ********************/
40 /******************************************************************************/
41 
42 #include "common.h"
43 
44 SC_MODULE( STIM )
45 {
46  SC_HAS_PROCESS( STIM );
47 
48  sc_in_clk clk;
49 
50  sc_signal<bool>& reset;
51  sc_signal<bool>& in_ok;
52  sc_signal<bool>& out_ok;
53  const sc_signal<bool>& instrb;
54  const sc_signal<bool>& outstrb;
55  signal_bool_vector &a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8;// -128 to 127
56  const signal_bool_vector &d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8;
57 
58 
59  STIM( sc_module_name NAME,
60  sc_clock& TICK_P,
61  sc_signal<bool>& RESET,
62  sc_signal<bool>& IN_OK,
63  sc_signal<bool>& OUT_OK,
64  const sc_signal<bool>& INSTRB,
65  const sc_signal<bool>& OUTSTRB,
82  )
83  :
84  reset (RESET),
85  in_ok (IN_OK),
86  out_ok (OUT_OK),
87  instrb (INSTRB),
88  outstrb (OUTSTRB),
89  a1 (A1), a2(A2), a3(A3), a4(A4),
90  a5 (A5), a6(A6), a7(A7), a8(A8),
91  d1 (D1), d2(D2), d3(D3), d4(D4),
92  d5 (D5), d6(D6), d7(D7), d8(D8)
93  {
94  clk(TICK_P);
95  SC_CTHREAD( entry, clk.neg() );
96  }
97  void entry();
98 };
99 
100 /******************************************************************************/
101 /*************************** testbench Entry Function **********************/
102 /******************************************************************************/
103 void
104 STIM::entry()
105 {
106 
107 // INITIAL INPUT VALUES
108 
109  a1.write(0); // Are quotes necessary ???
110  a2.write(0);
111  a3.write(0);
112  a4.write(0);
113  a5.write(0);
114  a6.write(0);
115  a7.write(0);
116  a8.write(0);
117  in_ok.write(0);
118  out_ok.write(0);
119  reset.write(1);
120  wait(2);
121 
122 // REMOVE RESET
123 
124  reset.write(0);
125  wait();
126 
127 // WAIT FOR REQUEST FOR INPUT
128 
129  do { wait(); } while (instrb == 0);
130 
131 // SEND INPUT DATA TO BE SORTED
132  a1.write(-76);
133  a2.write( 1);
134  a3.write( 12);
135  a4.write( 85);
136  a5.write( 15);
137  a6.write(103);
138  a7.write( -2);
139  a8.write( 3);
140  in_ok.write(1);
141  wait();
142 
143 // WAIT FOR OUTPUT READY
144 
145  do { wait(); } while (outstrb == 0);
146 
147 // READ OUTPUT & DISPLAY RESULTS
148 
149  cout << "\n" << endl;
150  cout << "\t\t INPUT DATA \t\t SORTED DATA" << endl;
151  cout << "\t\t " << a1.read().to_int() << " \t\t "
152  << d1.read().to_int() << endl;
153  cout << "\t\t " << a2.read().to_int() << " \t\t "
154  << d2.read().to_int() << endl;
155  cout << "\t\t " << a3.read().to_int() << " \t\t "
156  << d3.read().to_int() << endl;
157  cout << "\t\t " << a4.read().to_int() << " \t\t "
158  << d4.read().to_int() << endl;
159  cout << "\t\t " << a5.read().to_int() << " \t\t "
160  << d5.read().to_int() << endl;
161  cout << "\t\t " << a6.read().to_int() << " \t\t "
162  << d6.read().to_int() << endl;
163  cout << "\t\t " << a7.read().to_int() << " \t\t "
164  << d7.read().to_int() << endl;
165  cout << "\t\t " << a8.read().to_int() << " \t\t "
166  << d8.read().to_int() << endl;
167  cout << "\n" << endl;
168 
169 // SEND FINISHED READING OUTPUT FLAG
170 
171  in_ok.write(0);
172  out_ok.write(1);
173  wait();
174 
175 // STOP SIMULATION
176 
177  sc_stop();
178 }
SC_MODULE
SC_MODULE(STIM)
Definition: stim.h:44
Stats::reset
void reset()
Definition: statistics.cc:569
sc_core::sc_stop
void sc_stop()
Definition: sc_main.cc:104
common.h
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition: common.h:44
sc_core::wait
void wait()
Definition: sc_module.cc:653
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
ArmISA::a1
Bitfield< 22 > a1
Definition: miscregs_types.hh:495

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