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arch
generic
traits.hh
Go to the documentation of this file.
1
/*
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* Copyright (c) 2016, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Auxiliary structs for architecture traits. */
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#ifndef __ARCH_COMMON_TRAITS_HH__
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#define __ARCH_COMMON_TRAITS_HH__
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#include "
arch/generic/isa.hh
"
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#include "arch/types.hh"
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#include "enums/VecRegRenameMode.hh"
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52
template
<
typename
ISA>
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struct
RenameMode
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{
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static
Enums::VecRegRenameMode
init
(
const
BaseISA
*) {
return
Enums::Full; }
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static
Enums::VecRegRenameMode
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mode
(
const
TheISA::PCState
&)
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{
return
Enums::Full; }
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65
static
bool
equalsInit
(
const
BaseISA
*,
const
BaseISA
*) {
return
true
; }
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};
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#endif
/* __ARCH_COMMON_TRAITS_HH__ */
RenameMode::equalsInit
static bool equalsInit(const BaseISA *, const BaseISA *)
Compare the initial rename mode of two instances of the ISA.
Definition:
traits.hh:65
RenameMode::mode
static Enums::VecRegRenameMode mode(const TheISA::PCState &)
Definition:
traits.hh:58
RenameMode
Helper structure to get the vector register mode for a given ISA.
Definition:
traits.hh:53
RenameMode::init
static Enums::VecRegRenameMode init(const BaseISA *)
Definition:
traits.hh:55
isa.hh
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition:
types.hh:41
BaseISA
Definition:
isa.hh:47
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