gem5  v20.1.0.0
stim.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  stim.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
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29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /* Filename stim.h */
39 /* This is the interface file for synchronous process `stim' */
40 
41 #include "common.h"
42 
43 SC_MODULE( stim )
44 {
45  SC_HAS_PROCESS( stim );
46 
47  sc_in_clk clk;
48 
49  // Inputs
50  const sc_signal<bool>& done;
51  // Outputs
52  sc_signal<bool>& reset;
55  sc_signal<bool>& cin;
56  sc_signal<bool>& ready;
57  // Parameters
58  const int data_width;
59 
60  // Constructor
61  stim (sc_module_name NAME,
62  sc_clock& TICK,
63  const sc_signal<bool>& DONE,
64  sc_signal<bool>& RESET,
67  sc_signal<bool>& CIN,
68  sc_signal<bool>& READY,
69  const int DATA_WIDTH = 8)
70  : done(DONE), reset(RESET),
71  a(A),b(B), cin(CIN),
72  ready(READY),
73  data_width(DATA_WIDTH)
74  {
75  clk(TICK);
76  SC_CTHREAD( entry, clk.neg() );
77  }
78 
79  // Process functionality in member function below
80  void entry();
81 };
SC_MODULE
SC_MODULE(STIM)
Definition: stim.h:44
Stats::reset
void reset()
Definition: statistics.cc:569
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
common.h
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition: common.h:44
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319

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