vec_reg.hh File Reference

#include <array>
#include <cassert>
#include <iostream>
#include <string>
#include <type_traits>
#include <vector>
#include "base/cprintf.hh"
#include "base/logging.hh"

Go to the source code of this file.

Classes
class	VecRegContainer< SIZE >
	Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers. More...
class	VecRegT< VecElem, NumElems, Const >
	Vector Register Abstraction This generic class is a view in a particularization of MVC, to vector registers. More...
class	VecLaneT< VecElem, Const >
	Vector Lane abstraction Another view of a container. More...
class	VecRegContainer< SIZE >
	Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers. More...
class	LaneData< LS >
	LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values just depending on its width. More...
class	VecLaneT< VecElem, Const >
	Vector Lane abstraction Another view of a container. More...
struct	std::add_const< VecLaneT< T, Const > >

Namespaces
	std
	Overload hash function for BasicBlockRange type.

Enumerations
enum	LaneSize {   LaneSize::Empty = 0, LaneSize::Byte, LaneSize::TwoByte, LaneSize::FourByte,   LaneSize::EightByte }
	We define an auxiliary abstraction for LaneData. More...

Functions
template<LaneSize LS>
std::ostream &	operator<< (std::ostream &os, const LaneData< LS > &d)
	Output operator overload for LaneData<Size>. More...

Variables
constexpr unsigned	MaxVecRegLenInBytes = 4096
using	VecLane8 = VecLaneT< uint8_t, false >
using	VecLane16 = VecLaneT< uint16_t, false >
using	VecLane32 = VecLaneT< uint32_t, false >
using	VecLane64 = VecLaneT< uint64_t, false >
using	ConstVecLane8 = VecLaneT< uint8_t, true >
using	ConstVecLane16 = VecLaneT< uint16_t, true >
using	ConstVecLane32 = VecLaneT< uint32_t, true >
using	ConstVecLane64 = VecLaneT< uint64_t, true >
template<size_t Sz>
bool	to_number (const std::string &value, VecRegContainer< Sz > &v)
	Calls required for serialization/deserialization. More...
using	DummyVecElem = uint32_t
	Dummy type aliases and constants for architectures that do not implement vector registers. More...
using	DummyVecReg = VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, false >
using	DummyConstVecReg = VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, true >
using	DummyVecRegContainer = DummyVecReg::Container
constexpr unsigned	DummyNumVecElemPerVecReg = 2
constexpr size_t	DummyVecRegSizeBytes

Detailed Description

Vector Registers layout specification.

This register type is to be used to model the SIMD registers. It takes into account the possibility that different architectural names may overlap (like for ARMv8 AArch32 for example).

The design is having a basic vector register container that holds the bytes, unaware of anything else. This is implemented by VecRegContainer. As the (maximum) length of the physical vector register is a compile-time constant, it is defined as a template parameter.

This file also describes two views of the container that have semantic information about the bytes. The first of this views is VecRegT. A VecRegT is a view of a VecRegContainer (by reference). The VecRegT has a type (VecElem) to which bytes are casted, and the amount of such elements that the vector contains (NumElems). The size of a view, calculated as sizeof(VecElem) * NumElems must match the size of the underlying container. As VecRegT has some degree of type information it has vector semantics, and defines the index operator ([]) to get references to particular bytes understood as a VecElem. The second view of a container implemented in this file is VecLaneT, which is a view of a subset of the container. A VecLaneT is a view of a lane of a vector register, where a lane is identified by a type (VecElem) and an index (although the view is unaware of its index). Operations on the lane are directly applied to the corresponding bytes of the underlying VecRegContainer through a reference.

The intended usage is requesting views to the VecRegContainer via the member 'as' for VecRegT and the member 'laneView' for VecLaneT. Kindly find an example of usage in the following.

// We declare 512 bits vectors using Vec512 = VecRegContainer<64>; ... // We implement the physical vector register file Vec512 physicalVecRegFile[NUM_VREGS]; ... // Usage example, for a macro op: VecFloat8Add(ExecContext* xd) { // Request source vector register to the execution context (const as it // is read only). const Vec512& vsrc1raw = xc->readVecRegOperand(this, 0); // View it as a vector of floats (we could just specify the first // template parametre, the second has a default value that works, and the // last one is derived by the constness of vsrc1raw). VecRegT<float, 8, true>& vsrc1 = vsrc1raw->as<float, 8>();

// Second source and view const Vec512& vsrc2raw = xc->readVecRegOperand(this, 1); VecRegT<float, 8, true>& vsrc2 = vsrc2raw->as<float, 8>();

// Destination and view Vec512 vdstraw; VecRegT<float, 8, false>& vdst = vdstraw->as<float, 8>();

for (auto i = 0; i < 8; i++) { // This asignment sets the bits in the underlying Vec512: vdstraw vdst[i] = vsrc1[i] + vsrc2[i]; } xc->setWriteRegOperand(this, 0, vdstraw); }

// Usage example, for a micro op that operates over lane number _lidx: VecFloatLaneAdd(ExecContext* xd) { // Request source vector register to the execution context (const as it // is read only). const Vec512& vsrc1raw = xc->readVecRegOperand(this, 0); // View it as a lane of a vector of floats (we could just specify the // first template parametre, the second is derived by the constness of // vsrc1raw). VecLaneT<float, true>& src1 = vsrc1raw->laneView<float>(this->_lidx);

// Second source and view const Vec512& vsrc2raw = xc->readVecRegOperand(this, 1); VecLaneT<float, true>& src2 = vsrc2raw->laneView<float>(this->_lidx);

// (Writable) destination and view // As this is a partial write, we need the exec context to support that // through, e.g., 'readVecRegOperandToWrite' returning a writable // reference to the register Vec512 vdstraw = xc->readVecRegOperandToWrite(this, 3); VecLaneT<float, false>& dst = vdstraw->laneView<float>(this->_lidx);

dst = src1 + src2; // There is no need to copy the value back into the exec context, as // the assignment to dst modifies the appropriate bytes in vdstraw which // is in turn, a reference to the register in the cpu model. // For operations that do conditional writeback, we can decouple the // write by doing: // auto tmp = src1 + src2; // if (test) { // dst = tmp; // do writeback // } else { // // do not do writeback // } }

Definition in file vec_reg.hh.

Typedef Documentation

ConstVecLane16

using ConstVecLane16 = VecLaneT<uint16_t, true>

Definition at line 634 of file vec_reg.hh.

ConstVecLane32

using ConstVecLane32 = VecLaneT<uint32_t, true>

Definition at line 635 of file vec_reg.hh.

ConstVecLane64

using ConstVecLane64 = VecLaneT<uint64_t, true>

Definition at line 636 of file vec_reg.hh.

ConstVecLane8

using ConstVecLane8 = VecLaneT<uint8_t, true>

Definition at line 633 of file vec_reg.hh.

DummyConstVecReg

using DummyConstVecReg = VecRegT<DummyVecElem, DummyNumVecElemPerVecReg, true>

Definition at line 667 of file vec_reg.hh.

DummyVecElem

using DummyVecElem = uint32_t

Dummy type aliases and constants for architectures that do not implement vector registers.

Definition at line 664 of file vec_reg.hh.

DummyVecReg

using DummyVecReg = VecRegT<DummyVecElem, DummyNumVecElemPerVecReg, false>

Definition at line 666 of file vec_reg.hh.

DummyVecRegContainer

using DummyVecRegContainer = DummyVecReg::Container

Definition at line 668 of file vec_reg.hh.

VecLane16

using VecLane16 = VecLaneT<uint16_t, false>

Definition at line 629 of file vec_reg.hh.

VecLane32

using VecLane32 = VecLaneT<uint32_t, false>

Definition at line 630 of file vec_reg.hh.

VecLane64

using VecLane64 = VecLaneT<uint64_t, false>

Definition at line 631 of file vec_reg.hh.

VecLane8

using VecLane8 = VecLaneT<uint8_t, false>

Definition at line 628 of file vec_reg.hh.

Enumeration Type Documentation

LaneSize

enum LaneSize

strong

We define an auxiliary abstraction for LaneData.

The ISA should care about the semantics of a, e.g., 32bit element, treating it as a signed or unsigned int, or a float depending on the semantics of a particular instruction. On the other hand, the cpu model should only care about it being a 32-bit value.

Enumerator
Empty
Byte
TwoByte
FourByte
EightByte

Definition at line 432 of file vec_reg.hh.

Function Documentation

operator<<()

template<LaneSize LS>

std::ostream& operator<< ( std::ostream &  os, const LaneData< LS > &  d  )

inline

Output operator overload for LaneData<Size>.

Definition at line 498 of file vec_reg.hh.

References ArmISA::d.

to_number()

template<size_t Sz>

bool to_number ( const std::string &  value, VecRegContainer< Sz > &  v  )

inline

Calls required for serialization/deserialization.

Definition at line 644 of file vec_reg.hh.

References ArmISA::b, fatal_if, ArmISA::i, and ArmISA::v.

Variable Documentation

DummyNumVecElemPerVecReg

constexpr unsigned DummyNumVecElemPerVecReg = 2

constexpr

Definition at line 665 of file vec_reg.hh.

DummyVecRegSizeBytes

constexpr size_t DummyVecRegSizeBytes

constexpr

Initial value:

= DummyNumVecElemPerVecReg *
    sizeof(DummyVecElem)

Definition at line 669 of file vec_reg.hh.

MaxVecRegLenInBytes

constexpr unsigned MaxVecRegLenInBytes = 4096

constexpr

Definition at line 153 of file vec_reg.hh.