gem5
v20.1.0.0
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#include "arch/generic/interrupts.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/intmessage.hh"
#include "arch/x86/regs/apic.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
#include "dev/io_device.hh"
#include "dev/x86/intdev.hh"
#include "params/X86LocalApic.hh"
#include "sim/eventq.hh"
Go to the source code of this file.
Classes | |
class | X86ISA::Interrupts |
Namespaces | |
X86ISA | |
This is exposed globally, independent of the ISA. | |
Functions | |
int | divideFromConf (uint32_t conf) |
ApicRegIndex | X86ISA::decodeAddr (Addr paddr) |
int divideFromConf | ( | uint32_t | conf | ) |
Definition at line 67 of file interrupts.cc.
References ArmISA::shift.
Referenced by X86ISA::Interrupts::readReg(), and X86ISA::Interrupts::setReg().