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mem
hmc_controller.hh
Go to the documentation of this file.
1
/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2015 The University of Bologna
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_HMC_CONTROLLER_HH__
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#define __MEM_HMC_CONTROLLER_HH__
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#include "
mem/noncoherent_xbar.hh
"
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#include "
mem/port.hh
"
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#include "params/HMCController.hh"
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73
class
HMCController
:
public
NoncoherentXBar
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{
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public
:
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HMCController
(
const
HMCControllerParams *
p
);
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private
:
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// Receive range change only on one of the ports (because they all have
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// the same range)
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virtual
void
recvRangeChange
(
PortID
mem_side_port_id);
84
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// Receive a request and distribute it among response ports
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// Simply forwards the packet to the next serial link based on a
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// Round-robin counter
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virtual
bool
recvTimingReq
(
PacketPtr
pkt,
PortID
cpu_side_port_id);
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90
int
numMemSidePorts
;
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92
// The round-robin counter
93
int
rr_counter
;
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int
rotate_counter
();
99
};
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#endif //__MEM_HMC_CONTROLLER_HH__
HMCController::numMemSidePorts
int numMemSidePorts
Definition:
hmc_controller.hh:90
noncoherent_xbar.hh
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition:
types.hh:237
HMCController::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
Definition:
hmc_controller.cc:43
HMCController::recvRangeChange
virtual void recvRangeChange(PortID mem_side_port_id)
Function called by the port when the crossbar is recieving a range change.
Definition:
hmc_controller.cc:23
HMCController::HMCController
HMCController(const HMCControllerParams *p)
Definition:
hmc_controller.cc:7
HMCController::rr_counter
int rr_counter
Definition:
hmc_controller.hh:93
HMCController::rotate_counter
int rotate_counter()
Function for rotating the round robin counter.
Definition:
hmc_controller.cc:34
port.hh
HMCController
HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to ser...
Definition:
hmc_controller.hh:73
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition:
packet.hh:257
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
NoncoherentXBar
A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides,...
Definition:
noncoherent_xbar.hh:65
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