types.hh File Reference

#include <inttypes.h>
#include <cassert>
#include <memory>
#include <ostream>
#include <stdexcept>

Go to the source code of this file.

Classes
class	Cycles
	Cycles is a wrapper class for representing cycle counts, i.e. More...

Macros
#define	ULL(N)   ((uint64_t)N##ULL)
	uint64_t constant More...
#define	LL(N)   ((int64_t)N##LL)
	int64_t constant More...

Typedefs
typedef int64_t	Counter
	Statistics counter type. More...
typedef uint64_t	Tick
	Tick count type. More...
typedef uint64_t	Addr
	Address type This will probably be moved somewhere else in the near future. More...
typedef uint16_t	MicroPC
typedef uint64_t	RegVal
typedef int16_t	ThreadID
	Thread index/ID type. More...
typedef int	ContextID
	Globally unique thread context ID. More...
typedef int16_t	PortID
	Port index/ID type, and a symbolic name for an invalid port id. More...
typedef std::shared_ptr< FaultBase >	Fault

Functions
static MicroPC	romMicroPC (MicroPC upc)
static MicroPC	normalMicroPC (MicroPC upc)
static bool	isRomMicroPC (MicroPC upc)
static uint32_t	floatToBits32 (float val)
static uint64_t	floatToBits64 (double val)
static uint64_t	floatToBits (double val)
static uint32_t	floatToBits (float val)
static float	bitsToFloat32 (uint32_t val)
static double	bitsToFloat64 (uint64_t val)
static double	bitsToFloat (uint64_t val)
static float	bitsToFloat (uint32_t val)

Variables
const Tick	MaxTick = ULL(0xffffffffffffffff)
static const MicroPC	MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)
const Addr	MaxAddr = (Addr)-1
const ThreadID	InvalidThreadID = (ThreadID)-1
const ContextID	InvalidContextID = (ContextID)-1
const PortID	InvalidPortID = (PortID)-1
constexpr decltype(nullptr)	NoFault = nullptr

Detailed Description

Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.

Definition in file types.hh.

Macro Definition Documentation

LL

#define LL

(

N

)

((int64_t)N##LL)

int64_t constant

Definition at line 48 of file types.hh.

ULL

#define ULL

(

N

)

((uint64_t)N##ULL)

uint64_t constant

Definition at line 46 of file types.hh.

Typedef Documentation

Addr

typedef uint64_t Addr

Address type This will probably be moved somewhere else in the near future.

This should be at least as big as the biggest address width in use in the system, which will probably be 64 bits.

Definition at line 148 of file types.hh.

ContextID

typedef int ContextID

Globally unique thread context ID.

Definition at line 237 of file types.hh.

Counter

typedef int64_t Counter

Statistics counter type.

All counters are of 64-bit values.

Not much excuse for not using a 64-bit integer here, but if you're desperate and only run short simulations you could make this 32 bits.

Definition at line 54 of file types.hh.

Fault

typedef std::shared_ptr<FaultBase> Fault

Definition at line 246 of file types.hh.

MicroPC

typedef uint16_t MicroPC

Definition at line 150 of file types.hh.

PortID

typedef int16_t PortID

Port index/ID type, and a symbolic name for an invalid port id.

Definition at line 243 of file types.hh.

RegVal

typedef uint64_t RegVal

Definition at line 174 of file types.hh.

ThreadID

typedef int16_t ThreadID

Thread index/ID type.

Definition at line 233 of file types.hh.

Tick

typedef uint64_t Tick

Tick count type.

Definition at line 59 of file types.hh.

Function Documentation

bitsToFloat() [1/2]

static float bitsToFloat ( uint32_t  val )

inlinestatic

Definition at line 228 of file types.hh.

References bitsToFloat32(), and X86ISA::val.

bitsToFloat() [2/2]

static double bitsToFloat ( uint64_t  val )

inlinestatic

Definition at line 227 of file types.hh.

References bitsToFloat64(), and X86ISA::val.

bitsToFloat32()

static float bitsToFloat32 ( uint32_t  val )

inlinestatic

Definition at line 204 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by bitsToFloat(), GuestABI::Argument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get(), and Trace::TarmacTracerRecord::TraceRegEntry::updateFloat().

bitsToFloat64()

static double bitsToFloat64 ( uint64_t  val )

inlinestatic

Definition at line 216 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by bitsToFloat(), GuestABI::Argument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get(), and updateKvmStateFPUCommon().

floatToBits() [1/2]

static uint64_t floatToBits ( double  val )

inlinestatic

Definition at line 200 of file types.hh.

References floatToBits64(), and X86ISA::val.

Referenced by GuestABI::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::store(), and TEST().

floatToBits() [2/2]

static uint32_t floatToBits ( float  val )

inlinestatic

Definition at line 201 of file types.hh.

References floatToBits32(), and X86ISA::val.

floatToBits32()

static uint32_t floatToBits32 ( float  val )

inlinestatic

Definition at line 177 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by floatToBits(), and TEST().

floatToBits64()

static uint64_t floatToBits64 ( double  val )

inlinestatic

Definition at line 189 of file types.hh.

References ArmISA::f, ArmISA::i, ArmISA::u, and X86ISA::val.

Referenced by floatToBits(), TEST(), and updateThreadContextFPUCommon().

isRomMicroPC()

static bool isRomMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 167 of file types.hh.

References MicroPCRomBit.

Referenced by TimingSimpleCPU::fetch(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::pipelineIcacheAccesses(), BaseSimpleCPU::preExecute(), TEST(), AtomicSimpleCPU::tick(), and Checker< O3CPUImpl >::verify().

normalMicroPC()

static MicroPC normalMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 161 of file types.hh.

References MicroPCRomBit.

Referenced by X86ISAInst::MicrocodeRom::fetchMicroop(), and TEST().

romMicroPC()

static MicroPC romMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 155 of file types.hh.

References MicroPCRomBit.

Referenced by X86ISA::X86FaultBase::invoke(), X86ISA::InitInterrupt::invoke(), and TEST().

Variable Documentation

InvalidContextID

const ContextID InvalidContextID = (ContextID)-1

Definition at line 238 of file types.hh.

Referenced by AbstractMemory::checkLockedAddrList(), System::Threads::insert(), Sequencer::issueRequest(), and LockedAddr::matchesContext().

InvalidPortID

const PortID InvalidPortID = (PortID)-1

Definition at line 244 of file types.hh.

Referenced by BaseXBar::findPort(), CoherentXBar::forwardAtomic(), CoherentXBar::forwardFunctional(), CoherentXBar::forwardTiming(), FastModel::CortexR52::getPort(), SimpleMemobj::getPort(), SimpleCache::getPort(), SnoopFilter::portToMask(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), CoherentXBar::recvFunctionalSnoop(), CoherentXBar::recvTimingReq(), NoncoherentXBar::recvTimingResp(), CoherentXBar::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), CoherentXBar::recvTimingSnoopResp(), and SnoopFilter::setCPUSidePorts().

InvalidThreadID

const ThreadID InvalidThreadID = (ThreadID)-1

Definition at line 234 of file types.hh.

Referenced by DefaultFetch< Impl >::branchCount(), Minor::Execute::checkInterrupts(), DefaultFetch< Impl >::doSquash(), DefaultFetch< Impl >::drainSanityCheck(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Fetch1::evaluate(), DefaultCommit< Impl >::executingHtmTransaction(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::finishTranslation(), DefaultCommit< Impl >::getCommittingThread(), Minor::Execute::getCommittingThread(), DefaultFetch< Impl >::getFetchingThread(), FullO3CPU< O3CPUImpl >::getFreeTid(), Minor::Execute::getIssuingThread(), LSQ< Impl >::getLatestHtmUid(), Minor::Decode::getScheduledThread(), Minor::Fetch2::getScheduledThread(), Minor::Fetch1::getScheduledThread(), DefaultFetch< Impl >::iqCount(), DefaultFetch< Impl >::lsqCount(), LSQ< Impl >::numHtmStarts(), LSQ< Impl >::numHtmStops(), DefaultCommit< Impl >::oldestReady(), MipsISA::readRegOtherThread(), DefaultFetch< Impl >::recvReqRetry(), DefaultCommit< Impl >::resetHtmStartsStops(), LSQ< Impl >::resetHtmStartsStops(), DefaultCommit< Impl >::roundRobin(), DefaultFetch< Impl >::roundRobin(), LSQ< Impl >::setLastRetiredHtmUid(), and MipsISA::setRegOtherThread().

MaxAddr

const Addr MaxAddr = (Addr)-1

Definition at line 172 of file types.hh.

Referenced by Prefetcher::SignaturePath::addPrefetch(), Prefetcher::AccessMapPatternMatching::calculatePrefetch(), AddrRange::getOffset(), KernelWorkload::initState(), SectorSubBlk::insert(), TaggedEntry::invalidate(), TempCacheBlk::invalidate(), KernelWorkload::KernelWorkload(), Loader::MemoryImage::minAddr(), Prefetcher::STeMS::reconstructSequence(), and TEST().

MaxTick

const Tick MaxTick = ULL(0xffffffffffffffff)

Definition at line 61 of file types.hh.

Referenced by ElasticTrace::addCommittedInst(), ElasticTrace::addSquashedInst(), MemCtrl::addToReadQueue(), MemCtrl::chooseNextFRFCFS(), DRAMInterface::chooseNextFRFCFS(), NVMInterface::chooseNextFRFCFS(), NVMInterface::chooseRead(), PacketQueue::deferredPacketReadyTime(), BaseTrafficGen::drain(), CacheBlk::getWhenReady(), TraceCPU::FixedRetryGen::init(), CacheBlk::invalidate(), Trace::OstreamLogger::logMessage(), DRAMInterface::minBankPrep(), MemCtrl::minReadToWriteDataGap(), MemCtrl::minWriteToReadDataGap(), ExitGen::nextPacketTick(), IdleGen::nextPacketTick(), RandomGen::nextPacketTick(), LinearGen::nextPacketTick(), StridedGen::nextPacketTick(), HybridGen::nextPacketTick(), TraceGen::nextPacketTick(), Prefetcher::Multi::nextPrefetchReadyTime(), Prefetcher::Queued::nextPrefetchReadyTime(), Queue< WriteQueueEntry >::nextReadyTime(), sc_gem5::Scheduler::oneCycle(), NVMInterface::processReadReadyEvent(), pybind_init_core(), pybind_init_event(), BaseCache::recvTimingReq(), BaseCache::recvTimingResp(), BaseTrafficGen::retryReq(), sc_core::sc_max_time(), sc_core::sc_start(), PacketQueue::schedSendEvent(), BaseTrafficGen::scheduleUpdate(), BaseCache::CacheReqPacketQueue::sendDeferredPacket(), simulate(), Sp805::stopCounter(), BaseKvmCPU::tick(), Sp805::timeoutExpired(), sc_gem5::Scheduler::timeToPending(), and BaseTrafficGen::transition().

MicroPCRomBit

const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)

static

Definition at line 152 of file types.hh.

Referenced by isRomMicroPC(), normalMicroPC(), romMicroPC(), and TEST().

NoFault

constexpr decltype(nullptr) NoFault = nullptr

constexpr

Definition at line 251 of file types.hh.

Referenced by ArmISA::AArch64AArch32SystemAccessTrap(), RiscvISA::RemoteGDB::acc(), X86ISA::RemoteGDB::acc(), ElasticTrace::addCommittedInst(), ArmISA::addPACDA(), ArmISA::addPACDB(), ArmISA::addPACGA(), ArmISA::addPACIA(), ArmISA::addPACIB(), ArmISA::ISA::addressTranslation(), ArmISA::ISA::addressTranslation64(), ElasticTrace::addSquashedInst(), TimingSimpleCPU::advanceInst(), BaseSimpleCPU::advancePC(), Checker< O3CPUImpl >::advancePC(), AtomicSimpleCPU::amoMem(), amoMemAtomic(), ArmISA::authDA(), ArmISA::authDB(), ArmISA::authIA(), ArmISA::authIB(), LSQ< Impl >::SplitDataRequest::buildPackets(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), MipsISA::TLB::checkCacheability(), PowerISA::TLB::checkCacheability(), BaseSimpleCPU::checkForInterrupts(), ArmISA::ArmStaticInst::checkForWFxTrap32(), ArmISA::ArmStaticInst::checkForWFxTrap64(), ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), RiscvISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), ArmISA::ArmStaticInst::checkSETENDEnabled(), ArmISA::ArmStaticInst::checkSveEnabled(), LSQUnit< Impl >::checkViolations(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), Minor::Execute::commitInst(), DefaultCommit< Impl >::commitInsts(), ArmISAInst::MicroTfence64::completeAcc(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), DefaultCommit< Impl >::DefaultCommit(), ArmISA::TableWalker::doL1Descriptor(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2Descriptor(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptor(), ArmISA::TableWalker::doLongDescriptorWrapper(), BaseKvmCPU::doMMIOAccess(), InstructionQueue< Impl >::doSquash(), RiscvISA::TLB::doTranslate(), Minor::Decode::evaluate(), RiscvISA::MemFenceMicro::execute(), SparcISA::Nop::execute(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::execute(), SparcISA::WarnUnimplemented::execute(), ArmISAInst::Tstart64::execute(), WarnUnimplemented::execute(), ArmISAInst::Tcancel64::execute(), ArmISAInst::MicroTfence64::execute(), ArmISAInst::MicroTcommit64::execute(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::execute(), MiscRegImplDefined64::execute(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::execute(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::execute(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::execute(), McrMrcMiscInst::execute(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::execute(), DefaultIEW< Impl >::executeInsts(), LSQUnit< Impl >::executeLoad(), Minor::Execute::executeMemRefInst(), LSQUnit< Impl >::executeStore(), DefaultFetch< Impl >::fetchCacheLine(), ArmISA::TableWalker::fetchDescriptor(), Iris::TLB::finalizePhysical(), MipsISA::TLB::finalizePhysical(), RiscvISA::TLB::finalizePhysical(), X86ISA::TLB::finalizePhysical(), PowerISA::TLB::finalizePhysical(), SparcISA::TLB::finalizePhysical(), ArmISA::TLB::finalizePhysical(), ArmISA::Stage2MMU::Stage2Translation::finish(), ArmISA::Stage2LookUp::finish(), WholeTranslationState::finish(), Prefetcher::Queued::DeferredPacket::finish(), DataTranslation< ExecContextPtr >::finish(), Minor::LSQ::SingleDataRequest::finish(), Minor::LSQ::SplitDataRequest::finish(), LSQ< Impl >::SingleDataRequest::finish(), LSQ< Impl >::SplitDataRequest::finish(), DefaultFetch< Impl >::finishTranslation(), TimingSimpleCPU::finishTranslation(), WholeTranslationState::getFault(), Iris::Interrupts::getInterrupt(), RiscvISA::Interrupts::getInterrupt(), SparcISA::Interrupts::getInterrupt(), X86ISA::Interrupts::getInterrupt(), ArmISA::TLB::getResultTe(), ArmISA::Stage2LookUp::getTe(), ArmISA::TLB::getTE(), DefaultCommit< Impl >::handleInterrupt(), Minor::Execute::handleMemResponse(), Minor::Fetch1::handleTLBResponse(), LSQ< Impl >::HtmCmdRequest::HtmCmdRequest(), ArmISAInst::MicroTfence64::initiateAcc(), Minor::ExecContext::initiateHtmCmd(), TimingSimpleCPU::initiateHtmCmd(), CheckerCPU::initiateHtmCmd(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), BaseDynInst< Impl >::initVars(), DefaultCommit< Impl >::isDrained(), Minor::ForwardLineData::isFault(), Minor::MinorDynInst::isFault(), Minor::LSQ::LSQRequest::makePacket(), ArmISA::Stage2LookUp::mergeTe(), Minor::Fetch1::minorTraceResponseLine(), BaseCPU::mwaitAtomic(), Minor::operator<<(), FullO3CPU< O3CPUImpl >::processInterrupts(), Minor::Fetch1::processResponse(), ArmISA::TableWalker::processWalkWrapper(), DefaultCommit< Impl >::propagateInterrupt(), Minor::LSQ::pushRequest(), LSQ< Impl >::pushRequest(), LSQUnit< Impl >::read(), ArmISA::Stage2MMU::readDataUntimed(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), X86ISA::readMemAtomic(), readMemAtomic(), Trace::TarmacParserRecord::readMemNoEffect(), X86ISA::readPackedMemAtomic(), RiscvISA::Walker::WalkerState::recvPacket(), X86ISA::Walker::WalkerState::recvPacket(), Minor::ForwardLineData::reportData(), Minor::MinorDynInst::reportData(), Minor::LSQ::SplitDataRequest::retireResponse(), TimingSimpleCPU::sendFetch(), WholeTranslationState::setNoFault(), RiscvISA::Walker::start(), X86ISA::Walker::start(), RiscvISA::Walker::WalkerState::startFunctional(), X86ISA::Walker::WalkerState::startFunctional(), RiscvISA::Walker::WalkerState::startWalk(), X86ISA::Walker::WalkerState::startWalk(), RiscvISA::Walker::WalkerState::stepWalk(), X86ISA::Walker::WalkerState::stepWalk(), ArmISA::stripPAC(), Minor::Execute::takeInterrupt(), ArmISA::SelfDebug::testBreakPoints(), ArmISA::SelfDebug::testDebug(), ArmISA::TLB::testTranslation(), ArmISA::SelfDebug::testVectorCatch(), ArmISA::TLB::testWalk(), ArmISA::SelfDebug::testWatchPoints(), AtomicSimpleCPU::tick(), X86ISA::TLB::translate(), RiscvISA::TLB::translate(), EmulationPageTable::translate(), X86ISA::GpuTLB::translate(), ArmISA::TLB::translateComplete(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFs(), Iris::TLB::translateFunctional(), RiscvISA::TLB::translateFunctional(), X86ISA::TLB::translateFunctional(), SparcISA::TLB::translateFunctional(), SparcISA::TLB::translateInst(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), ArmISA::TLB::translateMmuOn(), TimingSimpleCPU::translationFault(), MiscRegOp64::trap(), ArmISA::trapPACUse(), ArmISA::ArmStaticInst::trapWFx(), TranslatingPortProxy::tryTLBsOnce(), Minor::Execute::tryToBranch(), Minor::Fetch1::tryToSendToTransfers(), Minor::LSQ::tryToSendToTransfers(), Minor::LSQ::LSQRequest::tryToSuppressFault(), tryTranslate(), ArmISA::ArmStaticInst::undefinedFault64(), Checker< O3CPUImpl >::validateState(), ArmISA::ArmFault::vectorCatch(), Checker< O3CPUImpl >::verify(), ArmISA::TableWalker::walk(), WholeTranslationState::WholeTranslationState(), LSQUnit< Impl >::write(), LSQUnit< Impl >::writeback(), DefaultIEW< Impl >::writebackInsts(), AtomicSimpleCPU::writeMem(), TimingSimpleCPU::writeMem(), CheckerCPU::writeMem(), writeMemAtomic(), X86ISA::writeMemAtomic(), and BaseDynInst< Impl >::~BaseDynInst().