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43 #include "debug/Decode.hh"
50 const MinorCPUParams ¶ms,
58 nextStageReserve(next_stage_input_buffer),
59 outputWidth(params.executeInputWidth),
60 processMoreThanOneInput(params.decodeCycleInput),
61 decodeInfo(params.numThreads),
67 if (params.decodeInputBufferSize < 1) {
68 fatal(
"%s: decodeInputBufferSize must be >= 1 (%d)\n",
name,
69 params.decodeInputBufferSize);
73 for (
ThreadID tid = 0; tid < params.numThreads; tid++) {
77 params.decodeInputBufferSize));
127 if (!
inp.outputWire->isBubble())
143 unsigned int output_index = 0;
153 if (inst->isBubble()) {
163 if (inst->isFault()) {
165 inst->fault->name());
193 output_inst->predictedTaken = inst->predictedTaken;
194 output_inst->predictedTarget = inst->predictedTarget;
198 " %d output_index: %d lastMicroop: %s microopPC:"
209 parent_static_inst = static_inst;
221 " %d output_index: %d\n",
222 *output_inst, decode_info.
inputIndex, output_index);
224 parent_static_inst = static_inst;
232 output_inst->id.execSeqNum = decode_info.
execSeqNum;
235 dynInstAddTracing(output_inst, parent_static_inst,
cpu);
244 insts_out.
insts[output_index] = output_inst;
292 if (!
inp.outputWire->isBubble())
303 case Enums::SingleThreaded:
304 priority_list.push_back(0);
306 case Enums::RoundRobin:
313 panic(
"Unknown fetch policy");
316 for (
auto tid : priority_list) {
334 return (*
inp.outputWire).isBubble();
340 std::ostringstream
data;
345 (*
out.inputWire).reportData(
data);
const ThreadID InvalidThreadID
bool inMacroop
True when we're in the process of decomposing a micro-op and microopPC will be valid.
#define fatal(...)
This implements a cprintf based fatal() function.
ThreadID threadId
Thread associated with these instructions.
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
unsigned int inputIndex
Index into the inputBuffer's head marking the start of unhandled instructions.
virtual void advancePC(TheISA::PCState &pcState) const =0
int16_t ThreadID
Thread index/ID type.
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
void setFetchSeq(InstSeqNum seq)
void evaluate()
Pass on input/buffer data to the output if you can.
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
const std::string to_string(sc_enc enc)
InstSeqNum execSeqNum
'Execute' sequence number.
Enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
#define MINORTRACE(...)
DPRINTFN for MinorTrace reporting.
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Data members after this line are cycle-to-cycle state.
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst=NULL)=0
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Dynamic instruction for Minor.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Decode(const std::string &name, MinorCPU &cpu_, const MinorCPUParams ¶ms, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
unsigned int width() const
Number of instructions carried by this object.
Trace::InstRecord * traceData
Trace information for this instruction's execution.
bool isBubble() const
BubbleIF interface.
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
const StaticInstPtr staticInst
bool isDrained()
Is this stage drained? For Decoed, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
MinorDynInstPtr insts[MAX_FORWARD_INSTS]
Array of carried insts, ref counted.
TheISA::PCState microopPC
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
ThreadID threadId
The thread to which this line/instruction belongs.
MinorCPU & cpu
Pointer back to the containing CPU.
constexpr decltype(nullptr) NoFault
const std::string & name()
bool isLastMicroop() const
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
void activity()
Records that there is activity this cycle.
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Trace::InstTracer * getTracer()
Provide access to the tracer pointer.
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
TheISA::PCState pc
The fetch address of this instruction.
std::vector< InputBuffer< ForwardInstData > > inputBuffer
void activateStage(const int idx)
Marks a stage as active.
std::vector< ThreadID > randomPriority()
Tick curTick()
The universal simulation clock.
void resize(unsigned int width)
Resize a bubble/empty ForwardInstData and fill with bubbles.
const std::string & name() const
std::vector< DecodeThreadInfo > decodeInfo
#define panic(...)
This implements a cprintf based panic() function.
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