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isa.cc
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28 
29 #include "arch/sparc/isa.hh"
30 
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/decoder.hh"
33 #include "arch/sparc/interrupts.hh"
34 #include "arch/sparc/regs/float.hh"
35 #include "arch/sparc/regs/int.hh"
36 #include "arch/sparc/regs/misc.hh"
37 #include "arch/sparc/sparc_traits.hh"
38 #include "base/bitfield.hh"
39 #include "base/trace.hh"
40 #include "cpu/base.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/MiscRegs.hh"
43 #include "debug/Timer.hh"
44 #include "params/SparcISA.hh"
45 
46 namespace gem5
47 {
48 
49 namespace SparcISA
50 {
51 
52 static PSTATE
53 buildPstateMask()
54 {
55  PSTATE mask = 0;
56  mask.ie = 1;
57  mask.priv = 1;
58  mask.am = 1;
59  mask.pef = 1;
60  mask.mm = 3;
61  mask.tle = 1;
62  mask.cle = 1;
63  mask.pid1 = 1;
64  return mask;
65 }
66 
67 static const PSTATE PstateMask = buildPstateMask();
68 
69 ISA::ISA(const Params &p) : BaseISA(p)
70 {
71  _regClasses.emplace_back(NumIntRegs, 0);
72  _regClasses.emplace_back(NumFloatRegs);
73  _regClasses.emplace_back(1); // Not applicable for SPARC
74  _regClasses.emplace_back(2); // Not applicable for SPARC
75  _regClasses.emplace_back(1); // Not applicable for SPARC
76  _regClasses.emplace_back(0); // Not applicable for SPARC
77  _regClasses.emplace_back(NumMiscRegs);
78  clear();
79 }
80 
81 static void
82 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
83 {
84  uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
85 
86  // Read all the trap level dependent registers and save them off
87  for (int i = 1; i <= MaxTL; i++) {
88  src->setMiscRegNoEffect(MISCREG_TL, i);
89  dest->setMiscRegNoEffect(MISCREG_TL, i);
90 
91  dest->setMiscRegNoEffect(MISCREG_TT,
92  src->readMiscRegNoEffect(MISCREG_TT));
93  dest->setMiscRegNoEffect(MISCREG_TPC,
94  src->readMiscRegNoEffect(MISCREG_TPC));
95  dest->setMiscRegNoEffect(MISCREG_TNPC,
96  src->readMiscRegNoEffect(MISCREG_TNPC));
97  dest->setMiscRegNoEffect(MISCREG_TSTATE,
98  src->readMiscRegNoEffect(MISCREG_TSTATE));
99  }
100 
101  // Save off the traplevel
102  dest->setMiscRegNoEffect(MISCREG_TL, tl);
103  src->setMiscRegNoEffect(MISCREG_TL, tl);
104 
105 
106  // ASRs
107 // dest->setMiscRegNoEffect(MISCREG_Y,
108 // src->readMiscRegNoEffect(MISCREG_Y));
109 // dest->setMiscRegNoEffect(MISCREG_CCR,
110 // src->readMiscRegNoEffect(MISCREG_CCR));
111  dest->setMiscReg(MISCREG_ASI,
112  src->readMiscRegNoEffect(MISCREG_ASI));
113  dest->setMiscRegNoEffect(MISCREG_TICK,
114  src->readMiscRegNoEffect(MISCREG_TICK));
115  dest->setMiscRegNoEffect(MISCREG_FPRS,
116  src->readMiscRegNoEffect(MISCREG_FPRS));
117  dest->setMiscRegNoEffect(MISCREG_SOFTINT,
118  src->readMiscRegNoEffect(MISCREG_SOFTINT));
119  dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
120  src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
121  dest->setMiscRegNoEffect(MISCREG_STICK,
122  src->readMiscRegNoEffect(MISCREG_STICK));
123  dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
124  src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
125 
126  // Priv Registers
127  dest->setMiscRegNoEffect(MISCREG_TICK,
128  src->readMiscRegNoEffect(MISCREG_TICK));
129  dest->setMiscRegNoEffect(MISCREG_TBA,
130  src->readMiscRegNoEffect(MISCREG_TBA));
131  dest->setMiscRegNoEffect(MISCREG_PSTATE,
132  src->readMiscRegNoEffect(MISCREG_PSTATE));
133  dest->setMiscRegNoEffect(MISCREG_PIL,
134  src->readMiscRegNoEffect(MISCREG_PIL));
135  dest->setMiscReg(MISCREG_CWP,
136  src->readMiscRegNoEffect(MISCREG_CWP));
137 // dest->setMiscRegNoEffect(MISCREG_CANSAVE,
138 // src->readMiscRegNoEffect(MISCREG_CANSAVE));
139 // dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
140 // src->readMiscRegNoEffect(MISCREG_CANRESTORE));
141 // dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
142 // src->readMiscRegNoEffect(MISCREG_OTHERWIN));
143 // dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
144 // src->readMiscRegNoEffect(MISCREG_CLEANWIN));
145 // dest->setMiscRegNoEffect(MISCREG_WSTATE,
146 // src->readMiscRegNoEffect(MISCREG_WSTATE));
147  dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
148 
149  // Hyperprivilged registers
150  dest->setMiscRegNoEffect(MISCREG_HPSTATE,
151  src->readMiscRegNoEffect(MISCREG_HPSTATE));
152  dest->setMiscRegNoEffect(MISCREG_HINTP,
153  src->readMiscRegNoEffect(MISCREG_HINTP));
154  dest->setMiscRegNoEffect(MISCREG_HTBA,
155  src->readMiscRegNoEffect(MISCREG_HTBA));
156  dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
157  src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
158  dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
159  src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
160 
161  // FSR
162  dest->setMiscRegNoEffect(MISCREG_FSR,
163  src->readMiscRegNoEffect(MISCREG_FSR));
164 
165  // Strand Status Register
166  dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
167  src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
168 
169  // MMU Registers
170  dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
171  src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
172  dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
173  src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
174  dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
175  src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
176  dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
177  src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
178 
179  // Scratchpad Registers
180  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
181  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
182  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
183  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
184  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
185  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
186  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
187  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
188  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
189  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
190  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
191  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
192  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
193  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
194  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
195  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
196 
197  // Queue Registers
198  dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
199  src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
200  dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
201  src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
202  dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
203  src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
204  dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
205  src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
206  dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
207  src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
208  dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
209  src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
210  dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
211  src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
212  dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
213  src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
214 }
215 
216 void
217 ISA::copyRegsFrom(ThreadContext *src)
218 {
219  // First loop through the integer registers.
220  int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
221  int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
222  // Globals
223  for (int x = 0; x < MaxGL; ++x) {
224  src->setMiscReg(MISCREG_GL, x);
225  tc->setMiscReg(MISCREG_GL, x);
226  // Skip %g0 which is always zero.
227  for (int y = 1; y < 8; y++)
228  tc->setIntReg(y, src->readIntReg(y));
229  }
230  // Locals and ins. Outs are all also ins.
231  for (int x = 0; x < NWindows; ++x) {
232  src->setMiscReg(MISCREG_CWP, x);
233  tc->setMiscReg(MISCREG_CWP, x);
234  for (int y = 16; y < 32; y++)
235  tc->setIntReg(y, src->readIntReg(y));
236  }
237  // Microcode reg and pseudo int regs (misc regs in the integer regfile).
238  for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
239  tc->setIntReg(y, src->readIntReg(y));
240 
241  // Restore src's GL, CWP
242  src->setMiscReg(MISCREG_GL, old_gl);
243  src->setMiscReg(MISCREG_CWP, old_cwp);
244 
245 
246  // Then loop through the floating point registers.
247  for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
248  tc->setFloatReg(i, src->readFloatReg(i));
249  }
250 
251  // Copy misc. registers
252  copyMiscRegs(src, tc);
253 
254  // Lastly copy PC/NPC
255  tc->pcState(src->pcState());
256 }
257 
258 void
259 ISA::reloadRegMap()
260 {
261  installGlobals(gl, CurrentGlobalsOffset);
262  installWindow(cwp, CurrentWindowOffset);
263  // Microcode registers.
264  for (int i = 0; i < NumMicroIntRegs; i++)
265  intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16;
266  installGlobals(gl, NextGlobalsOffset);
267  installWindow(cwp - 1, NextWindowOffset);
268  installGlobals(gl, PreviousGlobalsOffset);
269  installWindow(cwp + 1, PreviousWindowOffset);
270 }
271 
272 void
273 ISA::installWindow(int cwp, int offset)
274 {
275  assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs);
276  RegIndex *mapChunk = intRegMap + offset;
277  for (int i = 0; i < NumWindowedRegs; i++)
278  mapChunk[i] = TotalGlobals +
279  ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed));
280 }
281 
282 void
283 ISA::installGlobals(int gl, int offset)
284 {
285  assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs);
286  RegIndex *mapChunk = intRegMap + offset;
287  mapChunk[0] = 0;
288  for (int i = 1; i < NumGlobalRegs; i++)
289  mapChunk[i] = i + gl * NumGlobalRegs;
290 }
291 
292 void
293 ISA::clear()
294 {
295  cwp = 0;
296  gl = 0;
297  reloadRegMap();
298 
299  // y = 0;
300  // ccr = 0;
301  asi = 0;
302  tick = 1ULL << 63;
303  fprs = 0;
304  gsr = 0;
305  softint = 0;
306  tick_cmpr = 0;
307  stick = 0;
308  stick_cmpr = 0;
309  memset(tpc, 0, sizeof(tpc));
310  memset(tnpc, 0, sizeof(tnpc));
311  memset(tstate, 0, sizeof(tstate));
312  memset(tt, 0, sizeof(tt));
313  tba = 0;
314  pstate = 0;
315  tl = 0;
316  pil = 0;
317  // cansave = 0;
318  // canrestore = 0;
319  // cleanwin = 0;
320  // otherwin = 0;
321  // wstate = 0;
322  // In a T1, bit 11 is apparently always 1
323  hpstate = 0;
324  hpstate.id = 1;
325  memset(htstate, 0, sizeof(htstate));
326  hintp = 0;
327  htba = 0;
328  hstick_cmpr = 0;
329  // This is set this way in Legion for some reason
330  strandStatusReg = 0x50000;
331  fsr = 0;
332 
333  priContext = 0;
334  secContext = 0;
335  partId = 0;
336  lsuCtrlReg = 0;
337 
338  memset(scratchPad, 0, sizeof(scratchPad));
339 
340  cpu_mondo_head = 0;
341  cpu_mondo_tail = 0;
342  dev_mondo_head = 0;
343  dev_mondo_tail = 0;
344  res_error_head = 0;
345  res_error_tail = 0;
346  nres_error_head = 0;
347  nres_error_tail = 0;
348 
349  // If one of these events is active, it's not obvious to me how to get
350  // rid of it cleanly. For now we'll just assert that they're not.
351  if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
352  panic("Tick comparison event active when clearing the ISA object.\n");
353 }
354 
355 RegVal
356 ISA::readMiscRegNoEffect(int miscReg) const
357 {
358 
359  // The three miscRegs are moved up from the switch statement
360  // due to more frequent calls.
361 
362  if (miscReg == MISCREG_GL)
363  return gl;
364  if (miscReg == MISCREG_CWP)
365  return cwp;
366  if (miscReg == MISCREG_TLB_DATA) {
367  /* Package up all the data for the tlb:
368  * 6666555555555544444444443333333333222222222211111111110000000000
369  * 3210987654321098765432109876543210987654321098765432109876543210
370  * secContext | priContext | |tl|partid| |||||^hpriv
371  * ||||^red
372  * |||^priv
373  * ||^am
374  * |^lsuim
375  * ^lsudm
376  */
377  return (uint64_t)hpstate.hpriv |
378  (uint64_t)hpstate.red << 1 |
379  (uint64_t)pstate.priv << 2 |
380  (uint64_t)pstate.am << 3 |
381  bits((uint64_t)lsuCtrlReg,3,2) << 4 |
382  bits((uint64_t)partId,7,0) << 8 |
383  bits((uint64_t)tl,2,0) << 16 |
384  (uint64_t)priContext << 32 |
385  (uint64_t)secContext << 48;
386  }
387 
388  switch (miscReg) {
389  // case MISCREG_TLB_DATA:
390  // [original contents see above]
391  // case MISCREG_Y:
392  // return y;
393  // case MISCREG_CCR:
394  // return ccr;
395  case MISCREG_ASI:
396  return asi;
397  case MISCREG_FPRS:
398  return fprs;
399  case MISCREG_TICK:
400  return tick;
401  case MISCREG_PCR:
402  panic("PCR not implemented\n");
403  case MISCREG_PIC:
404  panic("PIC not implemented\n");
405  case MISCREG_GSR:
406  return gsr;
407  case MISCREG_SOFTINT:
408  return softint;
409  case MISCREG_TICK_CMPR:
410  return tick_cmpr;
411  case MISCREG_STICK:
412  return stick;
413  case MISCREG_STICK_CMPR:
414  return stick_cmpr;
415 
417  case MISCREG_TPC:
418  return tpc[tl-1];
419  case MISCREG_TNPC:
420  return tnpc[tl-1];
421  case MISCREG_TSTATE:
422  return tstate[tl-1];
423  case MISCREG_TT:
424  return tt[tl-1];
425  case MISCREG_PRIVTICK:
426  panic("Priviliged access to tick registers not implemented\n");
427  case MISCREG_TBA:
428  return tba;
429  case MISCREG_PSTATE:
430  return (RegVal)pstate;
431  case MISCREG_TL:
432  return tl;
433  case MISCREG_PIL:
434  return pil;
435  // CWP, GL moved
436  // case MISCREG_CWP:
437  // return cwp;
438  // case MISCREG_CANSAVE:
439  // return cansave;
440  // case MISCREG_CANRESTORE:
441  // return canrestore;
442  // case MISCREG_CLEANWIN:
443  // return cleanwin;
444  // case MISCREG_OTHERWIN:
445  // return otherwin;
446  // case MISCREG_WSTATE:
447  // return wstate;
448  // case MISCREG_GL:
449  // return gl;
450 
452  case MISCREG_HPSTATE:
453  return (RegVal)hpstate;
454  case MISCREG_HTSTATE:
455  return htstate[tl-1];
456  case MISCREG_HINTP:
457  return hintp;
458  case MISCREG_HTBA:
459  return htba;
460  case MISCREG_STRAND_STS_REG:
461  return strandStatusReg;
462  case MISCREG_HSTICK_CMPR:
463  return hstick_cmpr;
464 
466  case MISCREG_FSR:
467  DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
468  return fsr;
469 
470  case MISCREG_MMU_P_CONTEXT:
471  return priContext;
472  case MISCREG_MMU_S_CONTEXT:
473  return secContext;
474  case MISCREG_MMU_PART_ID:
475  return partId;
476  case MISCREG_MMU_LSU_CTRL:
477  return lsuCtrlReg;
478 
479  case MISCREG_SCRATCHPAD_R0:
480  return scratchPad[0];
481  case MISCREG_SCRATCHPAD_R1:
482  return scratchPad[1];
483  case MISCREG_SCRATCHPAD_R2:
484  return scratchPad[2];
485  case MISCREG_SCRATCHPAD_R3:
486  return scratchPad[3];
487  case MISCREG_SCRATCHPAD_R4:
488  return scratchPad[4];
489  case MISCREG_SCRATCHPAD_R5:
490  return scratchPad[5];
491  case MISCREG_SCRATCHPAD_R6:
492  return scratchPad[6];
493  case MISCREG_SCRATCHPAD_R7:
494  return scratchPad[7];
495  case MISCREG_QUEUE_CPU_MONDO_HEAD:
496  return cpu_mondo_head;
497  case MISCREG_QUEUE_CPU_MONDO_TAIL:
498  return cpu_mondo_tail;
499  case MISCREG_QUEUE_DEV_MONDO_HEAD:
500  return dev_mondo_head;
501  case MISCREG_QUEUE_DEV_MONDO_TAIL:
502  return dev_mondo_tail;
503  case MISCREG_QUEUE_RES_ERROR_HEAD:
504  return res_error_head;
505  case MISCREG_QUEUE_RES_ERROR_TAIL:
506  return res_error_tail;
507  case MISCREG_QUEUE_NRES_ERROR_HEAD:
508  return nres_error_head;
509  case MISCREG_QUEUE_NRES_ERROR_TAIL:
510  return nres_error_tail;
511  default:
512  panic("Miscellaneous register %d not implemented\n", miscReg);
513  }
514 }
515 
516 RegVal
517 ISA::readMiscReg(int miscReg)
518 {
519  switch (miscReg) {
520  // tick and stick are aliased to each other in niagra
521  // well store the tick data in stick and the interrupt bit in tick
522  case MISCREG_STICK:
523  case MISCREG_TICK:
524  case MISCREG_PRIVTICK:
525  // I'm not sure why legion ignores the lowest two bits, but we'll go
526  // with it
527  // change from curCycle() to instCount() until we're done with legion
528  DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
529  tc->getCpuPtr()->instCount(), stick);
530  return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
531  mbits(tick,63,63);
532  case MISCREG_FPRS:
533  // in legion if fp is enabled du and dl are set
534  return fprs | 0x3;
535  case MISCREG_PCR:
536  case MISCREG_PIC:
537  panic("Performance Instrumentation not impl\n");
538  case MISCREG_SOFTINT_CLR:
539  case MISCREG_SOFTINT_SET:
540  panic("Can read from softint clr/set\n");
541  case MISCREG_SOFTINT:
542  case MISCREG_TICK_CMPR:
543  case MISCREG_STICK_CMPR:
544  case MISCREG_HINTP:
545  case MISCREG_HTSTATE:
546  case MISCREG_HTBA:
547  case MISCREG_HVER:
548  case MISCREG_STRAND_STS_REG:
549  case MISCREG_HSTICK_CMPR:
550  case MISCREG_QUEUE_CPU_MONDO_HEAD:
551  case MISCREG_QUEUE_CPU_MONDO_TAIL:
552  case MISCREG_QUEUE_DEV_MONDO_HEAD:
553  case MISCREG_QUEUE_DEV_MONDO_TAIL:
554  case MISCREG_QUEUE_RES_ERROR_HEAD:
555  case MISCREG_QUEUE_RES_ERROR_TAIL:
556  case MISCREG_QUEUE_NRES_ERROR_HEAD:
557  case MISCREG_QUEUE_NRES_ERROR_TAIL:
558  case MISCREG_HPSTATE:
559  return readFSReg(miscReg);
560  }
561  return readMiscRegNoEffect(miscReg);
562 }
563 
564 void
565 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
566 {
567  switch (miscReg) {
568 // case MISCREG_Y:
569 // y = val;
570 // break;
571 // case MISCREG_CCR:
572 // ccr = val;
573 // break;
574  case MISCREG_ASI:
575  asi = val;
576  break;
577  case MISCREG_FPRS:
578  fprs = val;
579  break;
580  case MISCREG_TICK:
581  tick = val;
582  break;
583  case MISCREG_PCR:
584  panic("PCR not implemented\n");
585  case MISCREG_PIC:
586  panic("PIC not implemented\n");
587  case MISCREG_GSR:
588  gsr = val;
589  break;
590  case MISCREG_SOFTINT:
591  softint = val;
592  break;
593  case MISCREG_TICK_CMPR:
594  tick_cmpr = val;
595  break;
596  case MISCREG_STICK:
597  stick = val;
598  break;
599  case MISCREG_STICK_CMPR:
600  stick_cmpr = val;
601  break;
602 
604  case MISCREG_TPC:
605  tpc[tl-1] = val;
606  break;
607  case MISCREG_TNPC:
608  tnpc[tl-1] = val;
609  break;
610  case MISCREG_TSTATE:
611  tstate[tl-1] = val;
612  break;
613  case MISCREG_TT:
614  tt[tl-1] = val;
615  break;
616  case MISCREG_PRIVTICK:
617  panic("Priviliged access to tick regesiters not implemented\n");
618  case MISCREG_TBA:
619  // clear lower 7 bits on writes.
620  tba = val & ~0x7FFFULL;
621  break;
622  case MISCREG_PSTATE:
623  pstate = (val & PstateMask);
624  break;
625  case MISCREG_TL:
626  tl = val;
627  break;
628  case MISCREG_PIL:
629  pil = val;
630  break;
631  case MISCREG_CWP:
632  cwp = val;
633  break;
634 // case MISCREG_CANSAVE:
635 // cansave = val;
636 // break;
637 // case MISCREG_CANRESTORE:
638 // canrestore = val;
639 // break;
640 // case MISCREG_CLEANWIN:
641 // cleanwin = val;
642 // break;
643 // case MISCREG_OTHERWIN:
644 // otherwin = val;
645 // break;
646 // case MISCREG_WSTATE:
647 // wstate = val;
648 // break;
649  case MISCREG_GL:
650  gl = val;
651  break;
652 
654  case MISCREG_HPSTATE:
655  hpstate = val;
656  break;
657  case MISCREG_HTSTATE:
658  htstate[tl-1] = val;
659  break;
660  case MISCREG_HINTP:
661  hintp = val;
662  break;
663  case MISCREG_HTBA:
664  htba = val;
665  break;
666  case MISCREG_STRAND_STS_REG:
667  strandStatusReg = val;
668  break;
669  case MISCREG_HSTICK_CMPR:
670  hstick_cmpr = val;
671  break;
672 
674  case MISCREG_FSR:
675  fsr = val;
676  DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
677  break;
678 
679  case MISCREG_MMU_P_CONTEXT:
680  priContext = val;
681  break;
682  case MISCREG_MMU_S_CONTEXT:
683  secContext = val;
684  break;
685  case MISCREG_MMU_PART_ID:
686  partId = val;
687  break;
688  case MISCREG_MMU_LSU_CTRL:
689  lsuCtrlReg = val;
690  break;
691 
692  case MISCREG_SCRATCHPAD_R0:
693  scratchPad[0] = val;
694  break;
695  case MISCREG_SCRATCHPAD_R1:
696  scratchPad[1] = val;
697  break;
698  case MISCREG_SCRATCHPAD_R2:
699  scratchPad[2] = val;
700  break;
701  case MISCREG_SCRATCHPAD_R3:
702  scratchPad[3] = val;
703  break;
704  case MISCREG_SCRATCHPAD_R4:
705  scratchPad[4] = val;
706  break;
707  case MISCREG_SCRATCHPAD_R5:
708  scratchPad[5] = val;
709  break;
710  case MISCREG_SCRATCHPAD_R6:
711  scratchPad[6] = val;
712  break;
713  case MISCREG_SCRATCHPAD_R7:
714  scratchPad[7] = val;
715  break;
716  case MISCREG_QUEUE_CPU_MONDO_HEAD:
717  cpu_mondo_head = val;
718  break;
719  case MISCREG_QUEUE_CPU_MONDO_TAIL:
720  cpu_mondo_tail = val;
721  break;
722  case MISCREG_QUEUE_DEV_MONDO_HEAD:
723  dev_mondo_head = val;
724  break;
725  case MISCREG_QUEUE_DEV_MONDO_TAIL:
726  dev_mondo_tail = val;
727  break;
728  case MISCREG_QUEUE_RES_ERROR_HEAD:
729  res_error_head = val;
730  break;
731  case MISCREG_QUEUE_RES_ERROR_TAIL:
732  res_error_tail = val;
733  break;
734  case MISCREG_QUEUE_NRES_ERROR_HEAD:
735  nres_error_head = val;
736  break;
737  case MISCREG_QUEUE_NRES_ERROR_TAIL:
738  nres_error_tail = val;
739  break;
740  default:
741  panic("Miscellaneous register %d not implemented\n", miscReg);
742  }
743 }
744 
745 void
746 ISA::setMiscReg(int miscReg, RegVal val)
747 {
748  RegVal new_val = val;
749 
750  switch (miscReg) {
751  case MISCREG_ASI:
752  tc->getDecoderPtr()->setContext(val);
753  break;
754  case MISCREG_STICK:
755  case MISCREG_TICK:
756  // stick and tick are same thing on niagra
757  // use stick for offset and tick for holding intrrupt bit
758  stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
759  tick = mbits(val,63,63);
760  DPRINTF(Timer, "Writing TICK=%#X\n", val);
761  break;
762  case MISCREG_FPRS:
763  // Configure the fpu based on the fprs
764  break;
765  case MISCREG_PCR:
766  // Set up performance counting based on pcr value
767  break;
768  case MISCREG_PSTATE:
769  pstate = val & PstateMask;
770  return;
771  case MISCREG_TL:
772  {
773  tl = val;
774  if (hpstate.tlz && tl == 0 && !hpstate.hpriv)
775  tc->getCpuPtr()->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
776  else
777  tc->getCpuPtr()->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
778  return;
779  }
780  case MISCREG_CWP:
781  new_val = val >= NWindows ? NWindows - 1 : val;
782  if (val >= NWindows)
783  new_val = NWindows - 1;
784 
785  installWindow(new_val, CurrentWindowOffset);
786  installWindow(new_val - 1, NextWindowOffset);
787  installWindow(new_val + 1, PreviousWindowOffset);
788  break;
789  case MISCREG_GL:
790  installGlobals(val, CurrentGlobalsOffset);
791  installGlobals(val, NextGlobalsOffset);
792  installGlobals(val, PreviousGlobalsOffset);
793  break;
794  case MISCREG_PIL:
795  case MISCREG_SOFTINT:
796  case MISCREG_SOFTINT_SET:
797  case MISCREG_SOFTINT_CLR:
798  case MISCREG_TICK_CMPR:
799  case MISCREG_STICK_CMPR:
800  case MISCREG_HINTP:
801  case MISCREG_HTSTATE:
802  case MISCREG_HTBA:
803  case MISCREG_HVER:
804  case MISCREG_STRAND_STS_REG:
805  case MISCREG_HSTICK_CMPR:
806  case MISCREG_QUEUE_CPU_MONDO_HEAD:
807  case MISCREG_QUEUE_CPU_MONDO_TAIL:
808  case MISCREG_QUEUE_DEV_MONDO_HEAD:
809  case MISCREG_QUEUE_DEV_MONDO_TAIL:
810  case MISCREG_QUEUE_RES_ERROR_HEAD:
811  case MISCREG_QUEUE_RES_ERROR_TAIL:
812  case MISCREG_QUEUE_NRES_ERROR_HEAD:
813  case MISCREG_QUEUE_NRES_ERROR_TAIL:
814  case MISCREG_HPSTATE:
815  setFSReg(miscReg, val);
816  return;
817  }
818  setMiscRegNoEffect(miscReg, new_val);
819 }
820 
821 void
822 ISA::serialize(CheckpointOut &cp) const
823 {
824  SERIALIZE_SCALAR(asi);
825  SERIALIZE_SCALAR(tick);
826  SERIALIZE_SCALAR(fprs);
827  SERIALIZE_SCALAR(gsr);
828  SERIALIZE_SCALAR(softint);
829  SERIALIZE_SCALAR(tick_cmpr);
830  SERIALIZE_SCALAR(stick);
831  SERIALIZE_SCALAR(stick_cmpr);
832  SERIALIZE_ARRAY(tpc,MaxTL);
833  SERIALIZE_ARRAY(tnpc,MaxTL);
834  SERIALIZE_ARRAY(tstate,MaxTL);
835  SERIALIZE_ARRAY(tt,MaxTL);
836  SERIALIZE_SCALAR(tba);
837  SERIALIZE_SCALAR(pstate);
838  SERIALIZE_SCALAR(tl);
839  SERIALIZE_SCALAR(pil);
840  SERIALIZE_SCALAR(cwp);
841  SERIALIZE_SCALAR(gl);
842  SERIALIZE_SCALAR(hpstate);
843  SERIALIZE_ARRAY(htstate,MaxTL);
844  SERIALIZE_SCALAR(hintp);
845  SERIALIZE_SCALAR(htba);
846  SERIALIZE_SCALAR(hstick_cmpr);
847  SERIALIZE_SCALAR(strandStatusReg);
848  SERIALIZE_SCALAR(fsr);
849  SERIALIZE_SCALAR(priContext);
850  SERIALIZE_SCALAR(secContext);
851  SERIALIZE_SCALAR(partId);
852  SERIALIZE_SCALAR(lsuCtrlReg);
853  SERIALIZE_ARRAY(scratchPad,8);
854  SERIALIZE_SCALAR(cpu_mondo_head);
855  SERIALIZE_SCALAR(cpu_mondo_tail);
856  SERIALIZE_SCALAR(dev_mondo_head);
857  SERIALIZE_SCALAR(dev_mondo_tail);
858  SERIALIZE_SCALAR(res_error_head);
859  SERIALIZE_SCALAR(res_error_tail);
860  SERIALIZE_SCALAR(nres_error_head);
861  SERIALIZE_SCALAR(nres_error_tail);
862 
863  Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
864  if (tickCompare && tickCompare->scheduled())
865  tick_cmp = tickCompare->when();
866  if (sTickCompare && sTickCompare->scheduled())
867  stick_cmp = sTickCompare->when();
868  if (hSTickCompare && hSTickCompare->scheduled())
869  hstick_cmp = hSTickCompare->when();
870 
871  SERIALIZE_SCALAR(tick_cmp);
872  SERIALIZE_SCALAR(stick_cmp);
873  SERIALIZE_SCALAR(hstick_cmp);
874 }
875 
876 void
877 ISA::unserialize(CheckpointIn &cp)
878 {
879  UNSERIALIZE_SCALAR(asi);
880  UNSERIALIZE_SCALAR(tick);
881  UNSERIALIZE_SCALAR(fprs);
882  UNSERIALIZE_SCALAR(gsr);
883  UNSERIALIZE_SCALAR(softint);
884  UNSERIALIZE_SCALAR(tick_cmpr);
885  UNSERIALIZE_SCALAR(stick);
886  UNSERIALIZE_SCALAR(stick_cmpr);
887  UNSERIALIZE_ARRAY(tpc,MaxTL);
888  UNSERIALIZE_ARRAY(tnpc,MaxTL);
889  UNSERIALIZE_ARRAY(tstate,MaxTL);
890  UNSERIALIZE_ARRAY(tt,MaxTL);
891  UNSERIALIZE_SCALAR(tba);
892  {
893  uint16_t pstate;
894  UNSERIALIZE_SCALAR(pstate);
895  this->pstate = pstate;
896  }
897  UNSERIALIZE_SCALAR(tl);
898  UNSERIALIZE_SCALAR(pil);
899  UNSERIALIZE_SCALAR(cwp);
900  UNSERIALIZE_SCALAR(gl);
901  reloadRegMap();
902  {
903  uint64_t hpstate;
904  UNSERIALIZE_SCALAR(hpstate);
905  this->hpstate = hpstate;
906  }
907  UNSERIALIZE_ARRAY(htstate,MaxTL);
908  UNSERIALIZE_SCALAR(hintp);
909  UNSERIALIZE_SCALAR(htba);
910  UNSERIALIZE_SCALAR(hstick_cmpr);
911  UNSERIALIZE_SCALAR(strandStatusReg);
912  UNSERIALIZE_SCALAR(fsr);
913  UNSERIALIZE_SCALAR(priContext);
914  UNSERIALIZE_SCALAR(secContext);
915  UNSERIALIZE_SCALAR(partId);
916  UNSERIALIZE_SCALAR(lsuCtrlReg);
917  UNSERIALIZE_ARRAY(scratchPad,8);
918  UNSERIALIZE_SCALAR(cpu_mondo_head);
919  UNSERIALIZE_SCALAR(cpu_mondo_tail);
920  UNSERIALIZE_SCALAR(dev_mondo_head);
921  UNSERIALIZE_SCALAR(dev_mondo_tail);
922  UNSERIALIZE_SCALAR(res_error_head);
923  UNSERIALIZE_SCALAR(res_error_tail);
924  UNSERIALIZE_SCALAR(nres_error_head);
925  UNSERIALIZE_SCALAR(nres_error_tail);
926 
927  Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
928  UNSERIALIZE_SCALAR(tick_cmp);
929  UNSERIALIZE_SCALAR(stick_cmp);
930  UNSERIALIZE_SCALAR(hstick_cmp);
931 
932  if (tick_cmp) {
933  tickCompare = new TickCompareEvent(this);
934  schedule(tickCompare, tick_cmp);
935  }
936  if (stick_cmp) {
937  sTickCompare = new STickCompareEvent(this);
938  schedule(sTickCompare, stick_cmp);
939  }
940  if (hstick_cmp) {
941  hSTickCompare = new HSTickCompareEvent(this);
942  schedule(hSTickCompare, hstick_cmp);
943  }
944 }
945 
946 } // namespace SparcISA
947 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::SparcISA::MISCREG_TICK_CMPR
@ MISCREG_TICK_CMPR
Definition: misc.hh:54
gem5::SparcISA::ISA::TotalWindowed
static const int TotalWindowed
Definition: isa.hh:149
gem5::SparcISA::ISA::fsr
uint64_t fsr
Floating point misc registers.
Definition: isa.hh:101
gem5::SparcISA::ISA::CurrentWindowOffset
@ CurrentWindowOffset
Definition: isa.hh:154
gem5::Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:508
misc.hh
gem5::SparcISA::ISA::HSTickCompareEvent
EventWrapper< ISA, &ISA::processHSTickCompare > HSTickCompareEvent
Definition: isa.hh:140
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SparcISA::ISA::nres_error_head
uint64_t nres_error_head
Definition: isa.hh:117
gem5::SparcISA::ISA::installWindow
void installWindow(int cwp, int offset)
Definition: isa.cc:273
gem5::SparcISA::ISA::strandStatusReg
uint64_t strandStatusReg
Definition: isa.hh:98
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::SparcISA::NumIntArchRegs
@ NumIntArchRegs
Definition: int.hh:55
gem5::SparcISA::ISA::asi
uint8_t asi
Definition: isa.hh:60
gem5::SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: misc.hh:62
gem5::SparcISA::IT_TRAP_LEVEL_ZERO
@ IT_TRAP_LEVEL_ZERO
Definition: interrupts.hh:48
gem5::SparcISA::ISA::setFSReg
void setFSReg(int miscReg, RegVal val)
Definition: ua2005.cc:92
gem5::SparcISA::ISA::tnpc
uint64_t tnpc[MaxTL]
Definition: isa.hh:73
gem5::SparcISA::NumFloatArchRegs
const int NumFloatArchRegs
Definition: float.hh:39
gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD
@ MISCREG_QUEUE_DEV_MONDO_HEAD
Definition: misc.hh:107
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SparcISA::ISA::stick
uint64_t stick
Definition: isa.hh:66
gem5::SparcISA::ISA::hSTickCompare
HSTickCompareEvent * hSTickCompare
Definition: isa.hh:141
gem5::SparcISA::MISCREG_STICK
@ MISCREG_STICK
Definition: misc.hh:55
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD
@ MISCREG_QUEUE_NRES_ERROR_HEAD
Definition: misc.hh:111
gem5::SparcISA::ISA::NextGlobalsOffset
@ NextGlobalsOffset
Definition: isa.hh:156
gem5::SparcISA::ISA::readFSReg
RegVal readFSReg(int miscReg)
Definition: ua2005.cc:248
gem5::SparcISA::MISCREG_SOFTINT_SET
@ MISCREG_SOFTINT_SET
Definition: misc.hh:51
gem5::SparcISA::ISA::tl
uint8_t tl
Definition: isa.hh:81
gem5::SparcISA::ISA::PreviousGlobalsOffset
@ PreviousGlobalsOffset
Definition: isa.hh:158
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::SparcISA::ISA::cwp
uint8_t cwp
Definition: isa.hh:83
gem5::SparcISA::ISA::tt
uint16_t tt[MaxTL]
Definition: isa.hh:76
gem5::SparcISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:822
gem5::SparcISA::ISA::CurrentGlobalsOffset
@ CurrentGlobalsOffset
Definition: isa.hh:153
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::SparcISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:217
gem5::SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:39
gem5::SparcISA::ISA::tpc
uint64_t tpc[MaxTL]
Definition: isa.hh:71
gem5::SparcISA::ISA::hstick_cmpr
uint64_t hstick_cmpr
Definition: isa.hh:96
gem5::BaseCPU::instCount
Tick instCount()
Definition: base.hh:222
gem5::SparcISA::MISCREG_HVER
@ MISCREG_HVER
Definition: misc.hh:81
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::ISA::res_error_head
uint64_t res_error_head
Definition: isa.hh:115
gem5::SparcISA::ISA::installGlobals
void installGlobals(int gl, int offset)
Definition: isa.cc:283
gem5::SparcISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:79
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::SparcISA::ISA::clear
void clear()
Definition: isa.cc:293
gem5::SparcISA::MISCREG_FPRS
@ MISCREG_FPRS
Definition: misc.hh:47
gem5::SparcISA::MISCREG_HINTP
@ MISCREG_HINTP
Definition: misc.hh:79
gem5::ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
gem5::SparcISA::ISA::lsuCtrlReg
uint64_t lsuCtrlReg
Definition: isa.hh:107
gem5::SparcISA::ISA::scratchPad
uint64_t scratchPad[8]
Definition: isa.hh:109
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::SparcISA::ISA::NumGlobalRegs
static const int NumGlobalRegs
Definition: isa.hh:143
gem5::SparcISA::MISCREG_SCRATCHPAD_R4
@ MISCREG_SCRATCHPAD_R4
Definition: misc.hh:99
gem5::SparcISA::ISA::res_error_tail
uint64_t res_error_tail
Definition: isa.hh:116
gem5::SparcISA::ISA::tstate
uint64_t tstate[MaxTL]
Definition: isa.hh:75
gem5::SparcISA::ISA::htba
uint64_t htba
Definition: isa.hh:95
gem5::SparcISA::ISA::nres_error_tail
uint64_t nres_error_tail
Definition: isa.hh:118
gem5::SparcISA::MISCREG_HSTICK_CMPR
@ MISCREG_HSTICK_CMPR
Definition: misc.hh:83
gem5::SparcISA::NumMicroIntRegs
@ NumMicroIntRegs
Definition: int.hh:67
gem5::SparcISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:877
gem5::SparcISA::ISA::fprs
uint8_t fprs
Definition: isa.hh:62
gem5::SparcISA::ISA::STickCompareEvent
EventWrapper< ISA, &ISA::processSTickCompare > STickCompareEvent
Definition: isa.hh:137
gem5::SparcISA::ISA::TickCompareEvent
EventWrapper< ISA, &ISA::processTickCompare > TickCompareEvent
Definition: isa.hh:134
gem5::SparcISA::ISA::PreviousWindowOffset
@ PreviousWindowOffset
Definition: isa.hh:159
gem5::SparcISA::MISCREG_SCRATCHPAD_R1
@ MISCREG_SCRATCHPAD_R1
Definition: misc.hh:96
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:64
gem5::SparcISA::ISA::gsr
uint64_t gsr
Definition: isa.hh:63
gem5::SparcISA::MISCREG_MMU_PART_ID
@ MISCREG_MMU_PART_ID
Definition: misc.hh:91
gem5::SparcISA::MISCREG_PRIVTICK
@ MISCREG_PRIVTICK
Definition: misc.hh:63
gem5::SparcISA::ISA::gl
uint8_t gl
Definition: isa.hh:89
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SparcISA::NumMiscRegs
const int NumMiscRegs
Definition: misc.hh:173
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SparcISA::ISA::RegsPerWindow
static const int RegsPerWindow
Definition: isa.hh:148
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
asi.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SparcISA::MISCREG_MMU_S_CONTEXT
@ MISCREG_MMU_S_CONTEXT
Definition: misc.hh:90
gem5::SparcISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int miscReg, RegVal val)
Definition: isa.cc:565
gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL
@ MISCREG_QUEUE_DEV_MONDO_TAIL
Definition: misc.hh:108
gem5::BaseCPU::clearInterrupt
void clearInterrupt(ThreadID tid, int int_num, int index)
Definition: base.hh:244
gem5::SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: misc.hh:61
gem5::SparcISA::MISCREG_SCRATCHPAD_R7
@ MISCREG_SCRATCHPAD_R7
Definition: misc.hh:102
gem5::SparcISA::copyMiscRegs
static void copyMiscRegs(ThreadContext *src, ThreadContext *dest)
Definition: isa.cc:82
float.hh
gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL
@ MISCREG_QUEUE_CPU_MONDO_TAIL
Definition: misc.hh:106
gem5::SparcISA::ISA::tickCompare
TickCompareEvent * tickCompare
Definition: isa.hh:135
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
int.hh
gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD
@ MISCREG_QUEUE_RES_ERROR_HEAD
Definition: misc.hh:109
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::SparcISA::ISA::hpstate
HPSTATE hpstate
Hyperprivileged Registers.
Definition: isa.hh:92
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:194
gem5::SparcISA::ISA::dev_mondo_head
uint64_t dev_mondo_head
Definition: isa.hh:113
gem5::SparcISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:69
gem5::SparcISA::ISA::tba
uint64_t tba
Definition: isa.hh:78
gem5::SparcISA::MISCREG_PCR
@ MISCREG_PCR
Definition: misc.hh:48
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::SparcISA::ISA::secContext
uint16_t secContext
Definition: isa.hh:105
gem5::SparcISA::ISA::softint
uint64_t softint
Definition: isa.hh:64
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::SparcISA::ISA::priContext
uint16_t priContext
MMU Internal Registers.
Definition: isa.hh:104
gem5::SparcISA::MISCREG_SCRATCHPAD_R5
@ MISCREG_SCRATCHPAD_R5
Definition: misc.hh:100
gem5::SparcISA::ISA::TotalGlobals
static const int TotalGlobals
Definition: isa.hh:147
gem5::SparcISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int miscReg) const
Definition: isa.cc:356
gem5::SparcISA::ISA::hintp
uint64_t hintp
Definition: isa.hh:94
gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD
@ MISCREG_QUEUE_CPU_MONDO_HEAD
Definition: misc.hh:105
gem5::SparcISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:38
gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL
@ MISCREG_QUEUE_NRES_ERROR_TAIL
Definition: misc.hh:112
gem5::SparcISA::ISA::NextWindowOffset
@ NextWindowOffset
Definition: isa.hh:157
gem5::SparcISA::MISCREG_GSR
@ MISCREG_GSR
Definition: misc.hh:50
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: misc.hh:80
gem5::SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: misc.hh:60
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::SparcISA::ISA::reloadRegMap
void reloadRegMap()
Definition: isa.cc:259
gem5::SparcISA::ISA::pil
uint8_t pil
Definition: isa.hh:82
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: misc.hh:64
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: misc.hh:86
gem5::SparcISA::ISA::setMiscReg
void setMiscReg(int miscReg, RegVal val)
Definition: isa.cc:746
decoder.hh
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:40
gem5::MipsISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:254
interrupts.hh
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::ISA::tick_cmpr
uint64_t tick_cmpr
Definition: isa.hh:65
gem5::SparcISA::MISCREG_SCRATCHPAD_R3
@ MISCREG_SCRATCHPAD_R3
Definition: misc.hh:98
gem5::SparcISA::ISA::dev_mondo_tail
uint64_t dev_mondo_tail
Definition: isa.hh:114
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::ISA::partId
uint16_t partId
Definition: isa.hh:106
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::SparcISA::ISA::NumWindowedRegs
static const int NumWindowedRegs
Definition: isa.hh:144
gem5::SparcISA::MISCREG_TLB_DATA
@ MISCREG_TLB_DATA
Definition: misc.hh:115
gem5::SparcISA::MISCREG_SOFTINT_CLR
@ MISCREG_SOFTINT_CLR
Definition: misc.hh:52
trace.hh
gem5::SparcISA::ISA::readMiscReg
RegVal readMiscReg(int miscReg)
Definition: isa.cc:517
gem5::SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: misc.hh:78
gem5::SparcISA::ISA::stick_cmpr
uint64_t stick_cmpr
Definition: isa.hh:67
gem5::SparcISA::MISCREG_PIL
@ MISCREG_PIL
Definition: misc.hh:67
gem5::SparcISA::MISCREG_STRAND_STS_REG
@ MISCREG_STRAND_STS_REG
Definition: misc.hh:82
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::SparcISA::ISA::intRegMap
RegIndex intRegMap[TotalInstIntRegs]
Definition: isa.hh:163
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::SparcISA::ISA::tick
uint64_t tick
Definition: isa.hh:61
gem5::SparcISA::MISCREG_SCRATCHPAD_R6
@ MISCREG_SCRATCHPAD_R6
Definition: misc.hh:101
gem5::SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: misc.hh:74
gem5::SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: misc.hh:59
gem5::SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: misc.hh:92
gem5::SparcISA::MISCREG_PIC
@ MISCREG_PIC
Definition: misc.hh:49
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::ISA::MicroIntOffset
@ MicroIntOffset
Definition: isa.hh:155
gem5::SparcISA::ISA::sTickCompare
STickCompareEvent * sTickCompare
Definition: isa.hh:138
gem5::SparcISA::ISA::cpu_mondo_head
uint64_t cpu_mondo_head
Definition: isa.hh:111
gem5::SparcISA::PstateMask
static const PSTATE PstateMask
Definition: isa.cc:67
gem5::SparcISA::buildPstateMask
static PSTATE buildPstateMask()
Definition: isa.cc:53
sparc_traits.hh
gem5::SparcISA::MISCREG_STICK_CMPR
@ MISCREG_STICK_CMPR
Definition: misc.hh:56
gem5::SparcISA::ISA::pstate
PSTATE pstate
Definition: isa.hh:80
gem5::SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: misc.hh:89
gem5::SparcISA::ISA::cpu_mondo_tail
uint64_t cpu_mondo_tail
Definition: isa.hh:112
isa.hh
thread_context.hh
gem5::SparcISA::MISCREG_SOFTINT
@ MISCREG_SOFTINT
Definition: misc.hh:53
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::SparcISA::MISCREG_SCRATCHPAD_R0
@ MISCREG_SCRATCHPAD_R0
Scratchpad regiscers.
Definition: misc.hh:95
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::SparcISA::MISCREG_SCRATCHPAD_R2
@ MISCREG_SCRATCHPAD_R2
Definition: misc.hh:97
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::SparcISA::ISA::htstate
uint64_t htstate[MaxTL]
Definition: isa.hh:93
gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL
@ MISCREG_QUEUE_RES_ERROR_TAIL
Definition: misc.hh:110
gem5::SparcISA::ISA::Params
SparcISAParams Params
Definition: isa.hh:230
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