#include <exec_context.hh>

Inheritance diagram for gem5::SimpleExecContext:

Classes
struct	ExecContextStats

Public Member Functions
	SimpleExecContext (BaseSimpleCPU _cpu, SimpleThread _thread)
	Constructor. More...

RegVal	readIntRegOperand (const StaticInst *si, int idx) override
	Reads an integer register. More...

void	setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
	Sets an integer register to a value. More...

RegVal	readFloatRegOperandBits (const StaticInst *si, int idx) override
	Reads a floating point register in its binary format, instead of by value. More...

void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
	Sets the bits of a floating point register of single width to a binary value. More...

const TheISA::VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const override
	Reads a vector register. More...

TheISA::VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx) override
	Reads a vector register for modification. More...

void	setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
	Sets a vector register to a value. More...

TheISA::VecElem	readVecElemOperand (const StaticInst *si, int idx) const override
	Reads an element of a vector register. More...

void	setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
	Sets an element of a vector register to a value. More...

const TheISA::VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const override
	Predicate registers interface. More...

TheISA::VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx) override
	Gets destination predicate register operand for modification. More...

void	setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
	Sets a destination predicate register operand to a value. More...

RegVal	readCCRegOperand (const StaticInst *si, int idx) override

void	setCCRegOperand (const StaticInst *si, int idx, RegVal val) override

RegVal	readMiscRegOperand (const StaticInst *si, int idx) override

void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override

RegVal	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

void	setMiscReg (int misc_reg, RegVal val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

TheISA::PCState	pcState () const override

void	pcState (const TheISA::PCState &val) override

Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
	Perform an atomic memory read operation. More...

Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
	Initiate a timing memory read operation. More...

Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable) override
	For atomic-mode contexts, perform an atomic memory write operation. More...

Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

Fault	initiateHtmCmd (Request::Flags flags) override
	Initiate an HTM command, e.g. More...

void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures. More...

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...

ThreadContext *	tcBase () const override
	Returns a pointer to the ThreadContext. More...

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

uint64_t	getHtmTransactionUid () const override

uint64_t	newHtmTransactionUid () const override

bool	inHtmTransactionalState () const override

uint64_t	getHtmTransactionalDepth () const override

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override

Integer Register Interfaces
Floating Point Register Interfaces



Condition Code Registers
Misc Register Interfaces
PC Control
Memory Interface
ARM-Specific Interfaces
X86-Specific Interfaces

Public Attributes
BaseSimpleCPU *	cpu

SimpleThread *	thread

Addr	fetchOffset

bool	stayAtPC

TheISA::PCState	predPC

Counter	numInst
	PER-THREAD STATS. More...

Counter	numOp

Counter	numLoad

Counter	lastIcacheStall

Counter	lastDcacheStall

gem5::SimpleExecContext::ExecContextStats	execContextStats

Detailed Description

Definition at line 60 of file exec_context.hh.

Constructor & Destructor Documentation

◆ SimpleExecContext()

gem5::SimpleExecContext::SimpleExecContext	(	BaseSimpleCPU *	_cpu,
		SimpleThread *	_thread
	)

inline

Constructor.

Definition at line 277 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

Fault gem5::SimpleExecContext::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverridevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented from gem5::ExecContext.

Definition at line 506 of file exec_context.hh.

References gem5::X86ISA::addr, gem5::BaseSimpleCPU::amoMem(), cpu, and data.

◆ armMonitor()

void gem5::SimpleExecContext::armMonitor ( Addr address )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 608 of file exec_context.hh.

References gem5::BaseCPU::armMonitor(), cpu, thread, and gem5::SimpleThread::threadId().

◆ demapPage()

void gem5::SimpleExecContext::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements gem5::ExecContext.

Definition at line 602 of file exec_context.hh.

References gem5::SimpleThread::demapPage(), thread, and gem5::MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor* gem5::SimpleExecContext::getAddrMonitor ( )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 626 of file exec_context.hh.

References cpu, gem5::BaseCPU::getCpuAddrMonitor(), thread, and gem5::SimpleThread::threadId().

◆ getHtmTransactionalDepth()

uint64_t gem5::SimpleExecContext::getHtmTransactionalDepth ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 592 of file exec_context.hh.

References gem5::SimpleThread::htmTransactionStarts, gem5::SimpleThread::htmTransactionStops, and thread.

Referenced by inHtmTransactionalState().

◆ getHtmTransactionUid()

uint64_t gem5::SimpleExecContext::getHtmTransactionUid ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 574 of file exec_context.hh.

References gem5::ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::initiateHtmCmd(), gem5::TimingSimpleCPU::sendData(), and gem5::TimingSimpleCPU::sendSplitData().

◆ getWritableVecPredRegOperand()

TheISA::VecPredRegContainer& gem5::SimpleExecContext::getWritableVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements gem5::ExecContext.

Definition at line 387 of file exec_context.hh.

References execContextStats, gem5::SimpleThread::getWritableVecPredReg(), gem5::SimpleExecContext::ExecContextStats::numVecPredRegWrites, gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ getWritableVecRegOperand()

TheISA::VecRegContainer& gem5::SimpleExecContext::getWritableVecRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads a vector register for modification.

Implements gem5::ExecContext.

Definition at line 337 of file exec_context.hh.

References execContextStats, gem5::SimpleThread::getWritableVecReg(), gem5::SimpleExecContext::ExecContextStats::numVecRegWrites, gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ inHtmTransactionalState()

bool gem5::SimpleExecContext::inHtmTransactionalState ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 586 of file exec_context.hh.

References getHtmTransactionalDepth().

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::TimingSimpleCPU::sendData(), gem5::TimingSimpleCPU::sendSplitData(), and gem5::TimingSimpleCPU::switchOut().

◆ initiateHtmCmd()

Fault gem5::SimpleExecContext::initiateHtmCmd ( Request::Flags flags )

inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements gem5::ExecContext.

Definition at line 519 of file exec_context.hh.

References cpu, and gem5::BaseSimpleCPU::initiateHtmCmd().

◆ initiateMemAMO()

Fault gem5::SimpleExecContext::initiateMemAMO	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from gem5::ExecContext.

Definition at line 512 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, and gem5::BaseSimpleCPU::initiateMemAMO().

◆ initiateMemRead()

Fault gem5::SimpleExecContext::initiateMemRead	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 486 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, and gem5::BaseSimpleCPU::initiateMemRead().

◆ mwait()

bool gem5::SimpleExecContext::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 614 of file exec_context.hh.

References cpu, gem5::BaseCPU::mwait(), thread, and gem5::SimpleThread::threadId().

◆ mwaitAtomic()

void gem5::SimpleExecContext::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 620 of file exec_context.hh.

References cpu, gem5::SimpleThread::mmu, gem5::BaseCPU::mwaitAtomic(), thread, and gem5::SimpleThread::threadId().

◆ newHtmTransactionUid()

uint64_t gem5::SimpleExecContext::newHtmTransactionUid ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 580 of file exec_context.hh.

References gem5::ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by gem5::TimingSimpleCPU::completeIfetch().

◆ pcState() [1/2]

TheISA::PCState gem5::SimpleExecContext::pcState ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 464 of file exec_context.hh.

References gem5::SimpleThread::pcState(), and thread.

◆ pcState() [2/2]

void gem5::SimpleExecContext::pcState ( const TheISA::PCState & val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 470 of file exec_context.hh.

References gem5::SimpleThread::pcState(), thread, and gem5::X86ISA::val.

◆ readCCRegOperand()

RegVal gem5::SimpleExecContext::readCCRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 406 of file exec_context.hh.

References gem5::CCRegClass, execContextStats, gem5::SimpleExecContext::ExecContextStats::numCCRegReads, gem5::SimpleThread::readCCReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readFloatRegOperandBits()

RegVal gem5::SimpleExecContext::readFloatRegOperandBits	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements gem5::ExecContext.

Definition at line 306 of file exec_context.hh.

References execContextStats, gem5::FloatRegClass, gem5::SimpleExecContext::ExecContextStats::numFpRegReads, gem5::SimpleThread::readFloatReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal gem5::SimpleExecContext::readIntRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads an integer register.

Implements gem5::ExecContext.

Definition at line 285 of file exec_context.hh.

References execContextStats, gem5::IntRegClass, gem5::SimpleExecContext::ExecContextStats::numIntRegReads, gem5::SimpleThread::readIntReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readMem()

Fault gem5::SimpleExecContext::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

inlineoverridevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented from gem5::ExecContext.

Definition at line 476 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, data, and gem5::BaseSimpleCPU::readMem().

◆ readMemAccPredicate()

bool gem5::SimpleExecContext::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 562 of file exec_context.hh.

References gem5::SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal gem5::SimpleExecContext::readMiscReg ( int misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements gem5::ExecContext.

Definition at line 446 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numIntRegReads, gem5::SimpleThread::readMiscReg(), and thread.

◆ readMiscRegOperand()

RegVal gem5::SimpleExecContext::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 424 of file exec_context.hh.

References execContextStats, gem5::MiscRegClass, gem5::SimpleExecContext::ExecContextStats::numIntRegReads, gem5::SimpleThread::readMiscReg(), gem5::X86ISA::reg, gem5::ArmISA::si, and thread.

◆ readPredicate()

bool gem5::SimpleExecContext::readPredicate ( ) const

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 546 of file exec_context.hh.

References gem5::SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int gem5::SimpleExecContext::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 537 of file exec_context.hh.

References gem5::SimpleThread::readStCondFailures(), and thread.

◆ readVecElemOperand()

TheISA::VecElem gem5::SimpleExecContext::readVecElemOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads an element of a vector register.

Implements gem5::ExecContext.

Definition at line 358 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numVecRegReads, gem5::SimpleThread::readVecElem(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecElemClass.

◆ readVecPredRegOperand()

const TheISA::VecPredRegContainer& gem5::SimpleExecContext::readVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements gem5::ExecContext.

Definition at line 378 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numVecPredRegReads, gem5::SimpleThread::readVecPredReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecPredRegClass.

◆ readVecRegOperand()

const TheISA::VecRegContainer& gem5::SimpleExecContext::readVecRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads a vector register.

Implements gem5::ExecContext.

Definition at line 327 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numVecRegReads, gem5::SimpleThread::readVecReg(), gem5::X86ISA::reg, gem5::ArmISA::si, thread, and gem5::VecRegClass.

◆ setCCRegOperand()

void gem5::SimpleExecContext::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 415 of file exec_context.hh.

References gem5::CCRegClass, execContextStats, gem5::SimpleExecContext::ExecContextStats::numCCRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setCCReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setFloatRegOperandBits()

void gem5::SimpleExecContext::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements gem5::ExecContext.

Definition at line 317 of file exec_context.hh.

References execContextStats, gem5::FloatRegClass, gem5::SimpleExecContext::ExecContextStats::numFpRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setFloatReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setIntRegOperand()

void gem5::SimpleExecContext::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets an integer register to a value.

Implements gem5::ExecContext.

Definition at line 295 of file exec_context.hh.

References execContextStats, gem5::IntRegClass, gem5::SimpleExecContext::ExecContextStats::numIntRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setIntReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setMemAccPredicate()

void gem5::SimpleExecContext::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 568 of file exec_context.hh.

References gem5::SimpleThread::setMemAccPredicate(), thread, and gem5::X86ISA::val.

Referenced by gem5::BaseSimpleCPU::preExecute().

◆ setMiscReg()

void gem5::SimpleExecContext::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements gem5::ExecContext.

Definition at line 457 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numIntRegWrites, gem5::SimpleThread::setMiscReg(), thread, and gem5::X86ISA::val.

◆ setMiscRegOperand()

void gem5::SimpleExecContext::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 433 of file exec_context.hh.

References execContextStats, gem5::MiscRegClass, gem5::SimpleExecContext::ExecContextStats::numIntRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setMiscReg(), gem5::ArmISA::si, thread, and gem5::X86ISA::val.

◆ setPredicate()

void gem5::SimpleExecContext::setPredicate ( bool val )

inlineoverridevirtual

Implements gem5::ExecContext.

Definition at line 552 of file exec_context.hh.

References cpu, gem5::Trace::InstRecord::setPredicate(), gem5::SimpleThread::setPredicate(), thread, gem5::BaseSimpleCPU::traceData, and gem5::X86ISA::val.

Referenced by gem5::BaseSimpleCPU::preExecute().

◆ setStCondFailures()

void gem5::SimpleExecContext::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ExecContext.

Definition at line 528 of file exec_context.hh.

References gem5::SimpleThread::setStCondFailures(), and thread.

◆ setVecElemOperand()

void gem5::SimpleExecContext::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecElem	val
	)

inlineoverridevirtual

Sets an element of a vector register to a value.

Implements gem5::ExecContext.

Definition at line 368 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numVecRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setVecElem(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecElemClass.

◆ setVecPredRegOperand()

void gem5::SimpleExecContext::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecPredRegContainer &	val
	)

inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements gem5::ExecContext.

Definition at line 396 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numVecPredRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setVecPredReg(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecPredRegClass.

◆ setVecRegOperand()

void gem5::SimpleExecContext::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecRegContainer &	val
	)

inlineoverridevirtual

Sets a vector register to a value.

Implements gem5::ExecContext.

Definition at line 347 of file exec_context.hh.

References execContextStats, gem5::SimpleExecContext::ExecContextStats::numVecRegWrites, gem5::X86ISA::reg, gem5::SimpleThread::setVecReg(), gem5::ArmISA::si, thread, gem5::X86ISA::val, and gem5::VecRegClass.

◆ tcBase()

ThreadContext* gem5::SimpleExecContext::tcBase ( ) const

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements gem5::ExecContext.

Definition at line 543 of file exec_context.hh.

References gem5::SimpleThread::getTC(), and thread.

Referenced by getHtmTransactionUid(), and newHtmTransactionUid().

◆ writeMem()

Fault gem5::SimpleExecContext::writeMem	(	uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable
	)

inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements gem5::ExecContext.

Definition at line 496 of file exec_context.hh.

References gem5::X86ISA::addr, cpu, data, and gem5::BaseSimpleCPU::writeMem().

Member Data Documentation

◆ cpu

BaseSimpleCPU* gem5::SimpleExecContext::cpu

Definition at line 63 of file exec_context.hh.

Referenced by amoMem(), armMonitor(), gem5::SimpleExecContext::ExecContextStats::ExecContextStats(), getAddrMonitor(), initiateHtmCmd(), initiateMemAMO(), initiateMemRead(), mwait(), mwaitAtomic(), readMem(), setPredicate(), and writeMem().

◆ execContextStats

◆ fetchOffset

Addr gem5::SimpleExecContext::fetchOffset

Definition at line 67 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::advancePC(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::BaseSimpleCPU::preExecute(), and gem5::BaseSimpleCPU::setupFetchRequest().

◆ lastDcacheStall

Counter gem5::SimpleExecContext::lastDcacheStall

Definition at line 83 of file exec_context.hh.

◆ lastIcacheStall

Counter gem5::SimpleExecContext::lastIcacheStall

Definition at line 81 of file exec_context.hh.

◆ numInst

Counter gem5::SimpleExecContext::numInst

PER-THREAD STATS.

Definition at line 76 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::countInst(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateHtmCmd(), and gem5::BaseSimpleCPU::serviceInstCountEvents().

◆ numLoad

Counter gem5::SimpleExecContext::numLoad

Definition at line 79 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::postExecute().

◆ numOp

Counter gem5::SimpleExecContext::numOp

Definition at line 77 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::countInst().

◆ predPC

TheISA::PCState gem5::SimpleExecContext::predPC

Definition at line 73 of file exec_context.hh.

Referenced by gem5::BaseSimpleCPU::advancePC(), and gem5::BaseSimpleCPU::preExecute().

◆ stayAtPC

bool gem5::SimpleExecContext::stayAtPC

Definition at line 70 of file exec_context.hh.

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::AtomicSimpleCPU::isCpuDrained(), gem5::TimingSimpleCPU::isCpuDrained(), gem5::BaseSimpleCPU::preExecute(), gem5::TimingSimpleCPU::switchOut(), and gem5::AtomicSimpleCPU::tick().

◆ thread

SimpleThread* gem5::SimpleExecContext::thread

Definition at line 64 of file exec_context.hh.

The documentation for this class was generated from the following file:

cpu/simple/exec_context.hh

Classes

Public Member Functions

Public Attributes

Detailed Description

Constructor & Destructor Documentation

◆ SimpleExecContext()

Member Function Documentation

◆ amoMem()

◆ armMonitor()

◆ demapPage()

◆ getAddrMonitor()

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getWritableVecPredRegOperand()

◆ getWritableVecRegOperand()

◆ inHtmTransactionalState()

◆ initiateHtmCmd()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ mwait()

◆ mwaitAtomic()

◆ newHtmTransactionUid()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readCCRegOperand()

◆ readFloatRegOperandBits()

◆ readIntRegOperand()

◆ readMem()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ readVecElemOperand()

◆ readVecPredRegOperand()

◆ readVecRegOperand()

◆ setCCRegOperand()

◆ setFloatRegOperandBits()

◆ setIntRegOperand()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setStCondFailures()

◆ setVecElemOperand()

◆ setVecPredRegOperand()

◆ setVecRegOperand()

◆ tcBase()

◆ writeMem()

Member Data Documentation

◆ cpu

◆ execContextStats

◆ fetchOffset

◆ lastDcacheStall

◆ lastIcacheStall

◆ numInst

◆ numLoad

◆ numOp

◆ predPC

◆ stayAtPC

◆ thread