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v21.1.0.1
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gpu-compute
gpu_exec_context.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
8
* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
11
* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
14
* this list of conditions and the following disclaimer in the documentation
15
* and/or other materials provided with the distribution.
16
*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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34
#include "
gpu-compute/gpu_exec_context.hh
"
35
#include "
gpu-compute/wavefront.hh
"
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37
namespace
gem5
38
{
39
40
GPUExecContext::GPUExecContext
(
ComputeUnit
*_cu,
Wavefront
*_wf)
41
: cu(_cu), wf(_wf), gpuISA(_wf ? &_wf->gpuISA() : nullptr)
42
{
43
}
44
45
ComputeUnit
*
46
GPUExecContext::computeUnit
()
47
{
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return
cu
;
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}
50
51
Wavefront
*
52
GPUExecContext::wavefront
()
53
{
54
return
wf
;
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}
56
57
RegVal
58
GPUExecContext::readMiscReg
(
int
opIdx)
const
59
{
60
assert(
gpuISA
);
61
return
gpuISA
->readMiscReg(opIdx);
62
}
63
64
void
65
GPUExecContext::writeMiscReg
(
int
opIdx,
RegVal
val
)
66
{
67
assert(
gpuISA
);
68
gpuISA
->writeMiscReg(opIdx,
val
);
69
}
70
71
}
// namespace gem5
gem5::RegVal
uint64_t RegVal
Definition:
types.hh:173
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition:
gpu_exec_context.cc:65
gem5::Wavefront
Definition:
wavefront.hh:62
gem5::X86ISA::val
Bitfield< 63 > val
Definition:
misc.hh:775
gem5::GPUExecContext::wf
Wavefront * wf
Definition:
gpu_exec_context.hh:65
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition:
gpu_exec_context.hh:66
wavefront.hh
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition:
gpu_exec_context.cc:46
gem5::ComputeUnit
Definition:
compute_unit.hh:203
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition:
gpu_exec_context.cc:40
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition:
gpu_exec_context.cc:58
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition:
gpu_exec_context.cc:52
gpu_exec_context.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
decoder.cc:40
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition:
gpu_exec_context.hh:64
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