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gpu_exec_context.hh
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33 
34 #ifndef __GPU_EXEC_CONTEXT_HH__
35 #define __GPU_EXEC_CONTEXT_HH__
36 
37 #include "arch/gpu_isa.hh"
38 #include "base/types.hh"
39 #include "config/the_gpu_isa.hh"
40 
41 namespace gem5
42 {
43 
44 class ComputeUnit;
45 class Wavefront;
46 
48 {
49  public:
53 
54  template<typename T> T
55  readConstVal(int opIdx) const
56  {
57  return gpuISA->readConstVal<T>(opIdx);
58  }
59 
60  RegVal readMiscReg(int opIdx) const;
61  void writeMiscReg(int opIdx, RegVal operandVal);
62 
63  protected:
66  TheGpuISA::GPUISA *gpuISA;
67 };
68 
69 } // namespace gem5
70 
71 #endif // __GPU_EXEC_CONTEXT_HH__
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::GPUExecContext::readConstVal
T readConstVal(int opIdx) const
Definition: gpu_exec_context.hh:55
gem5::GPUExecContext::writeMiscReg
void writeMiscReg(int opIdx, RegVal operandVal)
Definition: gpu_exec_context.cc:65
gem5::Wavefront
Definition: wavefront.hh:62
gem5::GPUExecContext::wf
Wavefront * wf
Definition: gpu_exec_context.hh:65
gem5::GPUExecContext::gpuISA
TheGpuISA::GPUISA * gpuISA
Definition: gpu_exec_context.hh:66
gem5::GPUExecContext::computeUnit
ComputeUnit * computeUnit()
Definition: gpu_exec_context.cc:46
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::GPUExecContext::GPUExecContext
GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
Definition: gpu_exec_context.cc:40
gem5::GPUExecContext::readMiscReg
RegVal readMiscReg(int opIdx) const
Definition: gpu_exec_context.cc:58
gem5::GPUExecContext::wavefront
Wavefront * wavefront()
Definition: gpu_exec_context.cc:52
gem5::GPUExecContext
Definition: gpu_exec_context.hh:47
types.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::GPUExecContext::cu
ComputeUnit * cu
Definition: gpu_exec_context.hh:64

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