lsq.hh

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/*
 * Copyright (c) 2013-2014, 2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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#ifndef __CPU_MINOR_NEW_LSQ_HH__
#define __CPU_MINOR_NEW_LSQ_HH__
 
#include <string>
#include <vector>
 
#include "base/named.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/minor/trace.hh"
#include "mem/packet.hh"
 
namespace gem5
{
 
GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
 
/* Forward declaration */
class Execute;
 
class LSQ : public Named
{
  protected:
    MinorCPU &cpu;
    Execute &execute;
 
    const RegIndex zeroReg;
 
  protected:
    enum MemoryState
    {
        MemoryRunning, /* Default. Step dcache queues when possible. */
        MemoryNeedsRetry /* Request rejected, will be asked to retry */
    };
 
    friend std::ostream &operator <<(std::ostream &os,
        MemoryState state);
 
    enum AddrRangeCoverage
    {
        PartialAddrRangeCoverage, /* Two ranges partly overlap */
        FullAddrRangeCoverage, /* One range fully covers another */
        NoAddrRangeCoverage /* Two ranges are disjoint */
    };
 
    class DcachePort : public MinorCPU::MinorCPUPort
    {
      protected:
        LSQ &lsq;
 
      public:
        DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
            MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
        { }
 
      protected:
        bool recvTimingResp(PacketPtr pkt) override
        { return lsq.recvTimingResp(pkt); }
 
        void recvReqRetry() override { lsq.recvReqRetry(); }
 
        bool isSnooping() const override { return true; }
 
        void recvTimingSnoopReq(PacketPtr pkt) override
        { return lsq.recvTimingSnoopReq(pkt); }
 
        void recvFunctionalSnoop(PacketPtr pkt) override { }
    };
 
    DcachePort dcachePort;
 
  public:
    class LSQRequest :
        public BaseMMU::Translation, /* For TLB lookups */
        public Packet::SenderState /* For packing into a Packet */
    {
      public:
        LSQ &port;
 
        const RegIndex zeroReg;
 
        MinorDynInstPtr inst;
 
        bool isLoad;
 
        PacketDataPtr data;
 
        /* Requests carry packets on their way to the memory system.
         *  When a Packet returns from the memory system, its
         *  request needs to have its packet updated as this
         *  may have changed in flight */
        PacketPtr packet;
 
        RequestPtr request;
 
        uint64_t *res;
 
        bool skipped;
 
        bool issuedToMemory;
 
        bool isTranslationDelayed;
 
        enum LSQRequestState
        {
            NotIssued, /* Newly created */
            InTranslation, /* TLB accessed, no reply yet */
            Translated, /* Finished address translation */
            Failed, /* The starting start of FailedDataRequests */
            RequestIssuing, /* Load/store issued to memory in the requests
                queue */
            StoreToStoreBuffer, /* Store in transfers on its way to the
                store buffer */
            RequestNeedsRetry, /* Retry needed for load */
            StoreInStoreBuffer, /* Store in the store buffer, before issuing
                a memory transfer */
            StoreBufferIssuing, /* Store in store buffer and has been
                issued */
            StoreBufferNeedsRetry, /* Retry needed for store */
            /* All completed states.  Includes
                completed loads, TLB faults and skipped requests whose
                seqNum's no longer match */
            Complete
        };
 
        LSQRequestState state;
 
      protected:
        void markDelayed() { isTranslationDelayed = true; }
 
        void tryToSuppressFault();
 
        void disableMemAccess();
        void completeDisabledMemAccess();
 
      public:
        LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
                RegIndex zero_reg, PacketDataPtr data_ = NULL,
                uint64_t *res_ = NULL);
 
        virtual ~LSQRequest();
 
      public:
        void makePacket();
 
        bool skippedMemAccess() { return skipped; }
 
        void setSkipped() { skipped = true; }
 
        static AddrRangeCoverage containsAddrRangeOf(
            Addr req1_addr, unsigned int req1_size,
            Addr req2_addr, unsigned int req2_size);
 
        AddrRangeCoverage containsAddrRangeOf(LSQRequest *other_request);
 
        virtual void startAddrTranslation() = 0;
 
        virtual PacketPtr getHeadPacket() = 0;
 
        virtual void stepToNextPacket() = 0;
 
        virtual bool sentAllPackets() = 0;
 
        virtual bool hasPacketsInMemSystem() = 0;
 
        virtual void retireResponse(PacketPtr packet_) = 0;
 
        virtual bool isBarrier();
 
        bool needsToBeSentToStoreBuffer();
 
        void setState(LSQRequestState new_state);
 
        bool isComplete() const;
 
        void reportData(std::ostream &os) const;
    };
 
    typedef LSQRequest *LSQRequestPtr;
 
    friend std::ostream & operator <<(std::ostream &os,
        AddrRangeCoverage state);
 
    friend std::ostream & operator <<(std::ostream &os,
        LSQRequest::LSQRequestState state);
 
  protected:
    class SpecialDataRequest : public LSQRequest
    {
      protected:
        void finish(const Fault &fault_, const RequestPtr &request_,
                    ThreadContext *tc, BaseMMU::Mode mode)
        { }
 
      public:
        void startAddrTranslation() { }
 
        PacketPtr getHeadPacket()
        { fatal("No packets in a SpecialDataRequest"); }
 
        void stepToNextPacket() { }
 
        bool sentAllPackets() { return true; }
 
        bool hasPacketsInMemSystem() { return false; }
 
        void retireResponse(PacketPtr packet_) { }
 
      public:
        SpecialDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
            /* Say this is a load, not actually relevant */
            LSQRequest(port_, inst_, true, port_.zeroReg, NULL, 0)
        { }
    };
 
    class FailedDataRequest : public SpecialDataRequest
    {
      public:
        FailedDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
            SpecialDataRequest(port_, inst_)
        { state = Failed; }
    };
 
    class BarrierDataRequest : public SpecialDataRequest
    {
      public:
        bool isBarrier() { return true; }
 
      public:
        BarrierDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
            SpecialDataRequest(port_, inst_)
        { state = Complete; }
    };
 
    class SingleDataRequest : public LSQRequest
    {
      protected:
        void finish(const Fault &fault_, const RequestPtr &request_,
                    ThreadContext *tc, BaseMMU::Mode mode);
 
        bool packetInFlight;
 
        bool packetSent;
 
      public:
        void startAddrTranslation();
 
        PacketPtr getHeadPacket() { return packet; }
 
        void stepToNextPacket() { packetInFlight = true; packetSent = true; }
 
        bool hasPacketsInMemSystem() { return packetInFlight; }
 
        bool sentAllPackets() { return packetSent; }
 
        void retireResponse(PacketPtr packet_);
 
      public:
        SingleDataRequest(LSQ &port_, MinorDynInstPtr inst_,
            bool isLoad_, PacketDataPtr data_ = NULL, uint64_t *res_ = NULL) :
            LSQRequest(port_, inst_, isLoad_, port_.zeroReg, data_, res_),
            packetInFlight(false),
            packetSent(false)
        { }
    };
 
    class SplitDataRequest : public LSQRequest
    {
      protected:
        EventFunctionWrapper translationEvent;
      protected:
        unsigned int numFragments;
 
        unsigned int numInTranslationFragments;
 
        unsigned int numTranslatedFragments;
 
        unsigned int numIssuedFragments;
 
        unsigned int numRetiredFragments;
 
        std::vector<RequestPtr> fragmentRequests;
 
        std::vector<Packet *> fragmentPackets;
 
      protected:
        void finish(const Fault &fault_, const RequestPtr &request_,
                    ThreadContext *tc, BaseMMU::Mode mode);
 
      public:
        SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
            bool isLoad_, PacketDataPtr data_ = NULL,
            uint64_t *res_ = NULL);
 
        ~SplitDataRequest();
 
      public:
        void makeFragmentRequests();
 
        void makeFragmentPackets();
 
        void startAddrTranslation();
 
        PacketPtr getHeadPacket();
 
        void stepToNextPacket();
 
        bool hasPacketsInMemSystem()
        { return numIssuedFragments != numRetiredFragments; }
 
        bool sentAllPackets()
        { return numIssuedFragments == numTranslatedFragments; }
 
        void retireResponse(PacketPtr packet_);
 
        void sendNextFragmentToTranslation();
    };
 
    class StoreBuffer : public Named
    {
      public:
        LSQ &lsq;
 
        const unsigned int numSlots;
 
        const unsigned int storeLimitPerCycle;
 
      public:
        std::deque<LSQRequestPtr> slots;
 
        unsigned int numUnissuedAccesses;
 
      public:
        StoreBuffer(std::string name_, LSQ &lsq_,
            unsigned int store_buffer_size,
            unsigned int store_limit_per_cycle);
 
      public:
        bool canInsert() const;
 
        void deleteRequest(LSQRequestPtr request);
 
        void insert(LSQRequestPtr request);
 
        AddrRangeCoverage canForwardDataToLoad(LSQRequestPtr request,
            unsigned int &found_slot);
 
        void forwardStoreData(LSQRequestPtr load, unsigned int slot_number);
 
        unsigned int numUnissuedStores() { return numUnissuedAccesses; }
 
        void countIssuedStore(LSQRequestPtr request);
 
        bool isDrained() const { return slots.empty(); }
 
        void step();
 
        void minorTrace() const;
    };
 
  protected:
    std::vector<InstSeqNum> lastMemBarrier;
 
  public:
    MemoryState state;
 
    const unsigned int inMemorySystemLimit;
 
    const unsigned int lineWidth;
 
  public:
    typedef Queue<LSQRequestPtr,
        ReportTraitsPtrAdaptor<LSQRequestPtr>,
        NoBubbleTraits<LSQRequestPtr> >
        LSQQueue;
 
    LSQQueue requests;
 
    LSQQueue transfers;
 
    /* The store buffer contains committed cacheable stores on
     * their way to memory decoupled from subsequence instruction execution.
     * Before trying to issue a cacheable read from 'requests' to memory,
     * the store buffer is checked to see if a previous store contains the
     * needed data (StoreBuffer::canForwardDataToLoad) which can be
     * forwarded in lieu of a memory access.  If there are outstanding
     * stores in the transfers queue, they must be promoted to the store
     * buffer (and so be commited) before they can be correctly checked
     * for forwarding. */
    StoreBuffer storeBuffer;
 
  protected:
    unsigned int numAccessesInMemorySystem;
 
    unsigned int numAccessesInDTLB;
 
    unsigned int numStoresInTransfers;
 
    unsigned int numAccessesIssuedToMemory;
 
    LSQRequestPtr retryRequest;
 
    Addr cacheBlockMask;
 
  protected:
    void tryToSendToTransfers(LSQRequestPtr request);
 
    bool tryToSend(LSQRequestPtr request);
 
    void clearMemBarrier(MinorDynInstPtr inst);
 
    void moveFromRequestsToTransfers(LSQRequestPtr request);
 
    bool canSendToMemorySystem();
 
    void threadSnoop(LSQRequestPtr request);
 
  public:
    LSQ(std::string name_, std::string dcache_port_name_,
        MinorCPU &cpu_, Execute &execute_,
        unsigned int max_accesses_in_memory_system, unsigned int line_width,
        unsigned int requests_queue_size, unsigned int transfers_queue_size,
        unsigned int store_buffer_size,
        unsigned int store_buffer_cycle_store_limit,
        RegIndex zero_reg);
 
    virtual ~LSQ();
 
  public:
    void step();
 
    bool canRequest() { return requests.unreservedRemainingSpace() != 0; }
 
    LSQRequestPtr findResponse(MinorDynInstPtr inst);
 
    void popResponse(LSQRequestPtr response);
 
    bool canPushIntoStoreBuffer() const { return storeBuffer.canInsert(); }
 
    void sendStoreToStoreBuffer(LSQRequestPtr request);
 
    bool accessesInFlight() const
    { return numAccessesIssuedToMemory != 0; }
 
    void issuedMemBarrierInst(MinorDynInstPtr inst);
 
    InstSeqNum getLastMemBarrier(ThreadID thread_id) const
    { return lastMemBarrier[thread_id]; }
 
    bool isDrained();
 
    bool needsToTick();
 
    void completeMemBarrierInst(MinorDynInstPtr inst,
        bool committed);
 
    Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
                      unsigned int size, Addr addr, Request::Flags flags,
                      uint64_t *res, AtomicOpFunctorPtr amo_op,
                      const std::vector<bool>& byte_enable =
                          std::vector<bool>());
 
    void pushFailedRequest(MinorDynInstPtr inst);
 
    bool recvTimingResp(PacketPtr pkt);
    void recvReqRetry();
    void recvTimingSnoopReq(PacketPtr pkt);
 
    MinorCPU::MinorCPUPort &getDcachePort() { return dcachePort; }
 
    void minorTrace() const;
};
 
PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad,
    Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL);
 
} // namespace minor
} // namespace gem5
 
#endif /* __CPU_MINOR_NEW_LSQ_HH__ */