misc64.hh

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#ifndef __ARCH_ARM_INSTS_MISC64_HH__
#define __ARCH_ARM_INSTS_MISC64_HH__
 
#include "arch/arm/insts/static_inst.hh"
 
namespace gem5
{
 
class ImmOp64 : public ArmISA::ArmStaticInst
{
  protected:
    uint64_t imm;
 
    ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
            OpClass __opClass, uint64_t _imm) :
        ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
{
  protected:
    ArmISA::IntRegIndex dest;
    ArmISA::IntRegIndex op1;
    uint64_t imm1;
    uint64_t imm2;
 
    RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                     OpClass __opClass, ArmISA::IntRegIndex _dest,
                     ArmISA::IntRegIndex _op1, uint64_t _imm1,
                     int64_t _imm2) :
        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
{
  protected:
    ArmISA::IntRegIndex dest;
    ArmISA::IntRegIndex op1;
    ArmISA::IntRegIndex op2;
    uint64_t imm;
 
    RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                     OpClass __opClass, ArmISA::IntRegIndex _dest,
                     ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
                     uint64_t _imm) :
        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class UnknownOp64 : public ArmISA::ArmStaticInst
{
  protected:
 
    UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
            OpClass __opClass) :
        ArmISA::ArmStaticInst(mnem, _machInst, __opClass)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MiscRegOp64 : public ArmISA::ArmStaticInst
{
  protected:
    bool miscRead;
 
    MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                OpClass __opClass, bool misc_read) :
        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
        miscRead(misc_read)
    {}
 
    Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg,
               ArmISA::ExceptionLevel el, uint32_t immediate) const;
  private:
    bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
                      ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
                      uint32_t &immediate) const;
 
    bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
                      ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
                      uint32_t &immediate) const;
 
    bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
                      ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
                      uint32_t &immediate) const;
 
};
 
class MiscRegImmOp64 : public MiscRegOp64
{
  protected:
    ArmISA::MiscRegIndex dest;
    uint32_t imm;
 
    MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                   OpClass __opClass, ArmISA::MiscRegIndex _dest,
                   uint32_t _imm) :
        MiscRegOp64(mnem, _machInst, __opClass, false),
        dest(_dest), imm(_imm)
    {}
 
    RegVal miscRegImm() const;
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MiscRegRegImmOp64 : public MiscRegOp64
{
  protected:
    ArmISA::MiscRegIndex dest;
    ArmISA::IntRegIndex op1;
    uint32_t imm;
 
    MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                      OpClass __opClass, ArmISA::MiscRegIndex _dest,
                      ArmISA::IntRegIndex _op1, uint32_t _imm) :
        MiscRegOp64(mnem, _machInst, __opClass, false),
        dest(_dest), op1(_op1), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class RegMiscRegImmOp64 : public MiscRegOp64
{
  protected:
    ArmISA::IntRegIndex dest;
    ArmISA::MiscRegIndex op1;
    uint32_t imm;
 
    RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
                      OpClass __opClass, ArmISA::IntRegIndex _dest,
                      ArmISA::MiscRegIndex _op1, uint32_t _imm) :
        MiscRegOp64(mnem, _machInst, __opClass, true),
        dest(_dest), op1(_op1), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MiscRegImplDefined64 : public MiscRegOp64
{
  protected:
    const std::string fullMnemonic;
    const ArmISA::MiscRegIndex miscReg;
    const uint32_t imm;
    const bool warning;
 
  public:
    MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst,
                         ArmISA::MiscRegIndex misc_reg, bool misc_read,
                         uint32_t _imm, const std::string full_mnem,
                         bool _warning) :
        MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
        fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
        warning(_warning)
    {
        assert(miscReg == ArmISA::MISCREG_IMPDEF_UNIMPL);
    }
 
  protected:
    Fault execute(ExecContext *xc,
                  Trace::InstRecord *traceData) const override;
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class RegNone : public ArmISA::ArmStaticInst
{
  protected:
    ArmISA::IntRegIndex dest;
 
    RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
            OpClass __opClass, ArmISA::IntRegIndex _dest) :
        ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest)
    {}
 
    std::string generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const;
};
 
} // namespace gem5
 
#endif