tarmac_record.hh

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/*
 * Copyright (c) 2017-2019 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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#ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
#define __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
 
#include <memory>
 
#include "arch/arm/regs/misc.hh"
#include "arch/arm/tracers/tarmac_base.hh"
#include "base/printable.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
 
namespace gem5
{
 
namespace Trace {
 
class TarmacContext;
 
class TarmacTracer;
 
std::string
iSetStateToStr(TarmacBaseRecord::ISetState isetstate);
 
std::string
opModeToStr(ArmISA::OperatingMode opMode);
 
class TarmacTracerRecord : public TarmacBaseRecord
{
  public:
    struct TraceInstEntry: public InstEntry, Printable
    {
        TraceInstEntry(const TarmacContext& tarmCtx, bool predicate);
 
        virtual void print(std::ostream& outs,
                           int verbosity = 0,
                           const std::string &prefix = "") const override;
 
      protected:
        static uint64_t instCount;
 
        bool secureMode;
        uint8_t instSize;
    };
 
    struct TraceRegEntry: public RegEntry, Printable
    {
      public:
        TraceRegEntry(const TarmacContext& tarmCtx, const RegId& reg);
 
        void update(const TarmacContext& tarmCtx);
 
        virtual void print(std::ostream& outs,
                           int verbosity = 0,
                           const std::string &prefix = "") const override;
 
      protected:
        virtual void
        updateMisc(const TarmacContext& tarmCtx, RegIndex regRelIdx);
 
        virtual void
        updateCC(const TarmacContext& tarmCtx, RegIndex regRelIdx);
 
        virtual void
        updateFloat(const TarmacContext& tarmCtx, RegIndex regRelIdx);
 
        virtual void
        updateInt(const TarmacContext& tarmCtx, RegIndex regRelIdx);
 
        virtual void
        updateVec(const TarmacContext& tarmCtx, RegIndex regRelIdx) {};
 
        virtual void
        updatePred(const TarmacContext& tarmCtx, RegIndex regRelIdx) {};
 
      public:
        bool regValid;
        RegClass regClass;
        RegIndex regRel;
        std::string regName;
    };
 
    struct TraceMemEntry: public MemEntry, Printable
    {
      public:
        TraceMemEntry(const TarmacContext& tarmCtx,
                      uint8_t _size, Addr _addr, uint64_t _data);
 
        virtual void print(std::ostream& outs,
                           int verbosity = 0,
                           const std::string &prefix = "") const override;
 
      protected:
        bool loadAccess;
    };
 
  public:
    TarmacTracerRecord(Tick _when, ThreadContext *_thread,
                       const StaticInstPtr _staticInst, ArmISA::PCState _pc,
                       TarmacTracer& _tracer,
                       const StaticInstPtr _macroStaticInst = NULL);
 
    virtual void dump() override;
 
    using InstPtr = std::unique_ptr<TraceInstEntry>;
    using MemPtr = std::unique_ptr<TraceMemEntry>;
    using RegPtr = std::unique_ptr<TraceRegEntry>;
 
  protected:
    virtual void addInstEntry(std::vector<InstPtr>& queue,
                              const TarmacContext& ptr);
 
    virtual void addMemEntry(std::vector<MemPtr>& queue,
                             const TarmacContext& ptr);
 
    virtual void addRegEntry(std::vector<RegPtr>& queue,
                             const TarmacContext& ptr);
 
  protected:
    template<typename RegEntry>
    RegEntry
    genRegister(const TarmacContext& tarmCtx, const RegId& reg)
    {
        RegEntry single_reg(tarmCtx, reg);
        single_reg.update(tarmCtx);
 
        return single_reg;
    }
 
    template<typename RegEntry>
    void
    mergeCCEntry(std::vector<RegPtr>& queue, const TarmacContext& tarmCtx)
    {
        // Find all CC Entries and move them at the end of the queue
        auto it = std::remove_if(
            queue.begin(), queue.end(),
            [] (RegPtr& reg) ->bool { return (reg->regClass == CCRegClass); }
        );
 
        if (it != queue.end()) {
            // Remove all CC Entries.
            queue.erase(it, queue.end());
 
            auto is_cpsr = [] (RegPtr& reg) ->bool
            {
                return (reg->regClass == MiscRegClass) &&
                       (reg->regRel == ArmISA::MISCREG_CPSR);
            };
 
            // Looking for the presence of a CPSR register entry.
            auto cpsr_it = std::find_if(
                queue.begin(), queue.end(), is_cpsr
            );
 
            // If CPSR entry not present, generate one
            if (cpsr_it == queue.end()) {
                RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR);
                queue.push_back(
                    std::make_unique<RegEntry>(
                        genRegister<RegEntry>(tarmCtx, reg))
                );
            }
        }
    }
 
    template<typename Queue>
    void flushQueues(Queue& queue);
    template<typename Queue, typename... Args>
    void flushQueues(Queue& queue, Args & ... args);
 
  protected:
    TarmacTracer& tracer;
};
 
} // namespace Trace
} // namespace gem5
 
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__