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decoder.cc
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1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include <vector>
35 
39 
40 namespace gem5
41 {
42 
43 namespace VegaISA
44 {
46  {
47  } // Decoder
48 
50  {
51  } // ~Decoder
52 
53  /*
54  * These will probably have to be updated according to the Vega ISA manual:
55  * https://developer.amd.com/wp-content/resources/
56  * Vega_Shader_ISA_28July2017.pdf
57  */
571  };
572 
1342  };
1343 
1601  };
1602 
1732  };
1733 
1863  };
1864 
1994  };
1995 
2013  };
2014 
2144  };
2145 
2275  };
2276 
2534  };
2535 
2793  };
2794 
2924  };
2925 
3055  };
3056 
3062  };
3063 
3321  };
3322 
3580  };
3581 
3711  };
3712 
3713  GPUStaticInst*
3715  {
3716  InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
3718  return (this->*method)(mach_inst);
3719  } // decode
3720 
3721  GPUStaticInst*
3723  {
3724  InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
3725  IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
3726  return (this->*method)(iFmt);
3727  } // subDecode_OP_VOPC
3728 
3729  GPUStaticInst*
3731  {
3732  InFmt_VOP3P *enc = &iFmt->iFmt_VOP3P;
3734  return (this->*method)(iFmt);
3735  } // subDecode_OP_VOP3P
3736 
3737  GPUStaticInst*
3739  {
3740  InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
3741  IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
3742  return (this->*method)(iFmt);
3743  } // subDecode_OP_VOP1
3744 
3745  GPUStaticInst*
3747  {
3748  InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
3749  IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
3750  return (this->*method)(iFmt);
3751  } // subDecode_OP_SOP1
3752 
3753  GPUStaticInst*
3755  {
3756  InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
3757  IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
3758  return (this->*method)(iFmt);
3759  } // subDecode_OP_SOPC
3760 
3761  GPUStaticInst*
3763  {
3764  InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
3765  IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
3766  return (this->*method)(iFmt);
3767  } // subDecode_OP_SOPP
3768 
3769  GPUStaticInst*
3771  {
3772  InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
3773  IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
3774  return (this->*method)(iFmt);
3775  } // subDecode_OP_SMEM
3776 
3777  GPUStaticInst*
3779  {
3780  InFmt_VOP3A *enc = &iFmt->iFmt_VOP3A;
3782  return (this->*method)(iFmt);
3783  } // subDecode_OPU_VOP3
3784 
3785  GPUStaticInst*
3787  {
3788  InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
3790  return (this->*method)(iFmt);
3791  } // subDecode_OP_VINTRP
3792 
3793  GPUStaticInst*
3795  {
3796  InFmt_DS *enc = &iFmt->iFmt_DS;
3797  IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
3798  return (this->*method)(iFmt);
3799  } // subDecode_OP_DS
3800 
3801  GPUStaticInst*
3803  {
3804  InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
3805  IsaDecodeMethod method;
3806  switch (enc->SEG) {
3807  case 0:
3808  method = tableSubDecode_OP_FLAT[enc->OP];
3809  break;
3810  case 1:
3811  method = tableSubDecode_OP_SCRATCH[enc->OP];
3812  break;
3813  case 2:
3814  method = tableSubDecode_OP_GLOBAL[enc->OP];
3815  break;
3816  default:
3817  fatal("Invalid SEG for FLAT encoding: %d\n", enc->SEG);
3818  }
3819  return (this->*method)(iFmt);
3820  } // subDecode_OP_FLAT
3821 
3822  GPUStaticInst*
3824  {
3825  InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
3827  return (this->*method)(iFmt);
3828  } // subDecode_OP_MUBUF
3829 
3830  GPUStaticInst*
3832  {
3833  InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
3835  return (this->*method)(iFmt);
3836  } // subDecode_OP_MTBUF
3837 
3838  GPUStaticInst*
3840  {
3841  InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
3842  IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
3843  return (this->*method)(iFmt);
3844  } // subDecode_OP_MIMG
3845 
3846  GPUStaticInst*
3848  {
3849  return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
3850  } // decode_OP_VOP2__V_CNDMASK_B32
3851 
3852  GPUStaticInst*
3854  {
3855  return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
3856  } // decode_OP_VOP2__V_ADD_F32
3857 
3858  GPUStaticInst*
3860  {
3861  return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
3862  } // decode_OP_VOP2__V_SUB_F32
3863 
3864  GPUStaticInst*
3866  {
3867  return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
3868  } // decode_OP_VOP2__V_SUBREV_F32
3869 
3870  GPUStaticInst*
3872  {
3873  return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
3874  } // decode_OP_VOP2__V_MUL_LEGACY_F32
3875 
3876  GPUStaticInst*
3878  {
3879  return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
3880  } // decode_OP_VOP2__V_MUL_F32
3881 
3882  GPUStaticInst*
3884  {
3885  return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
3886  } // decode_OP_VOP2__V_MUL_I32_I24
3887 
3888  GPUStaticInst*
3890  {
3891  return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
3892  } // decode_OP_VOP2__V_MUL_HI_I32_I24
3893 
3894  GPUStaticInst*
3896  {
3897  return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
3898  } // decode_OP_VOP2__V_MUL_U32_U24
3899 
3900  GPUStaticInst*
3902  {
3903  return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
3904  } // decode_OP_VOP2__V_MUL_HI_U32_U24
3905 
3906  GPUStaticInst*
3908  {
3909  return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
3910  } // decode_OP_VOP2__V_MIN_F32
3911 
3912  GPUStaticInst*
3914  {
3915  return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
3916  } // decode_OP_VOP2__V_MAX_F32
3917 
3918  GPUStaticInst*
3920  {
3921  return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
3922  } // decode_OP_VOP2__V_MIN_I32
3923 
3924  GPUStaticInst*
3926  {
3927  return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
3928  } // decode_OP_VOP2__V_MAX_I32
3929 
3930  GPUStaticInst*
3932  {
3933  return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
3934  } // decode_OP_VOP2__V_MIN_U32
3935 
3936  GPUStaticInst*
3938  {
3939  return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
3940  } // decode_OP_VOP2__V_MAX_U32
3941 
3942  GPUStaticInst*
3944  {
3945  return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
3946  } // decode_OP_VOP2__V_LSHRREV_B32
3947 
3948  GPUStaticInst*
3950  {
3951  return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
3952  } // decode_OP_VOP2__V_ASHRREV_I32
3953 
3954  GPUStaticInst*
3956  {
3957  return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
3958  } // decode_OP_VOP2__V_LSHLREV_B32
3959 
3960  GPUStaticInst*
3962  {
3963  return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
3964  } // decode_OP_VOP2__V_AND_B32
3965 
3966  GPUStaticInst*
3968  {
3969  return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
3970  } // decode_OP_VOP2__V_OR_B32
3971 
3972  GPUStaticInst*
3974  {
3975  return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
3976  } // decode_OP_VOP2__V_XOR_B32
3977 
3978  GPUStaticInst*
3980  {
3981  return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
3982  } // decode_OP_VOP2__V_MAC_F32
3983 
3984  GPUStaticInst*
3986  {
3987  return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
3988  } // decode_OP_VOP2__V_MADMK_F32
3989 
3990  GPUStaticInst*
3992  {
3993  return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
3994  } // decode_OP_VOP2__V_MADAK_F32
3995 
3996  GPUStaticInst*
3998  {
3999  return new Inst_VOP2__V_ADD_CO_U32(&iFmt->iFmt_VOP2);
4000  } // decode_OP_VOP2__V_ADD_CO_U32
4001 
4002  GPUStaticInst*
4004  {
4005  return new Inst_VOP2__V_SUB_CO_U32(&iFmt->iFmt_VOP2);
4006  } // decode_OP_VOP2__V_SUB_CO_U32
4007 
4008  GPUStaticInst*
4010  {
4011  return new Inst_VOP2__V_SUBREV_CO_U32(&iFmt->iFmt_VOP2);
4012  } // decode_OP_VOP2__V_SUBREV_CO_U32
4013 
4014  GPUStaticInst*
4016  {
4017  return new Inst_VOP2__V_ADDC_CO_U32(&iFmt->iFmt_VOP2);
4018  } // decode_OP_VOP2__V_ADDC_CO_U32
4019 
4020  GPUStaticInst*
4022  {
4023  return new Inst_VOP2__V_SUBB_CO_U32(&iFmt->iFmt_VOP2);
4024  } // decode_OP_VOP2__V_SUBB_CO_U32
4025 
4026  GPUStaticInst*
4028  {
4029  return new Inst_VOP2__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP2);
4030  } // decode_OP_VOP2__V_SUBBREV_CO_U32
4031 
4032  GPUStaticInst*
4034  {
4035  return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
4036  } // decode_OP_VOP2__V_ADD_F16
4037 
4038  GPUStaticInst*
4040  {
4041  return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
4042  } // decode_OP_VOP2__V_SUB_F16
4043 
4044  GPUStaticInst*
4046  {
4047  return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
4048  } // decode_OP_VOP2__V_SUBREV_F16
4049 
4050  GPUStaticInst*
4052  {
4053  return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
4054  } // decode_OP_VOP2__V_MUL_F16
4055 
4056  GPUStaticInst*
4058  {
4059  return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
4060  } // decode_OP_VOP2__V_MAC_F16
4061 
4062  GPUStaticInst*
4064  {
4065  return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
4066  } // decode_OP_VOP2__V_MADMK_F16
4067 
4068  GPUStaticInst*
4070  {
4071  return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
4072  } // decode_OP_VOP2__V_MADAK_F16
4073 
4074  GPUStaticInst*
4076  {
4077  return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
4078  } // decode_OP_VOP2__V_ADD_U16
4079 
4080  GPUStaticInst*
4082  {
4083  return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
4084  } // decode_OP_VOP2__V_SUB_U16
4085 
4086  GPUStaticInst*
4088  {
4089  return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
4090  } // decode_OP_VOP2__V_SUBREV_U16
4091 
4092  GPUStaticInst*
4094  {
4095  return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
4096  } // decode_OP_VOP2__V_MUL_LO_U16
4097 
4098  GPUStaticInst*
4100  {
4101  return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
4102  } // decode_OP_VOP2__V_LSHLREV_B16
4103 
4104  GPUStaticInst*
4106  {
4107  return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
4108  } // decode_OP_VOP2__V_LSHRREV_B16
4109 
4110  GPUStaticInst*
4112  {
4113  return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
4114  } // decode_OP_VOP2__V_ASHRREV_I16
4115 
4116  GPUStaticInst*
4118  {
4119  return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
4120  } // decode_OP_VOP2__V_MAX_F16
4121 
4122  GPUStaticInst*
4124  {
4125  return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
4126  } // decode_OP_VOP2__V_MIN_F16
4127 
4128  GPUStaticInst*
4130  {
4131  return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
4132  } // decode_OP_VOP2__V_MAX_U16
4133 
4134  GPUStaticInst*
4136  {
4137  return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
4138  } // decode_OP_VOP2__V_MAX_I16
4139 
4140  GPUStaticInst*
4142  {
4143  return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
4144  } // decode_OP_VOP2__V_MIN_U16
4145 
4146  GPUStaticInst*
4148  {
4149  return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
4150  } // decode_OP_VOP2__V_MIN_I16
4151 
4152  GPUStaticInst*
4154  {
4155  return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
4156  } // decode_OP_VOP2__V_LDEXP_F16
4157 
4158  GPUStaticInst*
4160  {
4161  return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
4162  }
4163 
4164  GPUStaticInst*
4166  {
4167  return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
4168  }
4169 
4170  GPUStaticInst*
4172  {
4173  return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
4174  }
4175 
4176  GPUStaticInst*
4178  {
4179  return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
4180  } // decode_OP_SOP2__S_ADD_U32
4181 
4182  GPUStaticInst*
4184  {
4185  return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
4186  } // decode_OP_SOP2__S_SUB_U32
4187 
4188  GPUStaticInst*
4190  {
4191  return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
4192  } // decode_OP_SOP2__S_ADD_I32
4193 
4194  GPUStaticInst*
4196  {
4197  return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
4198  } // decode_OP_SOP2__S_SUB_I32
4199 
4200  GPUStaticInst*
4202  {
4203  return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
4204  } // decode_OP_SOP2__S_ADDC_U32
4205 
4206  GPUStaticInst*
4208  {
4209  return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
4210  } // decode_OP_SOP2__S_SUBB_U32
4211 
4212  GPUStaticInst*
4214  {
4215  return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
4216  } // decode_OP_SOP2__S_MIN_I32
4217 
4218  GPUStaticInst*
4220  {
4221  return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
4222  } // decode_OP_SOP2__S_MIN_U32
4223 
4224  GPUStaticInst*
4226  {
4227  return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
4228  } // decode_OP_SOP2__S_MAX_I32
4229 
4230  GPUStaticInst*
4232  {
4233  return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
4234  } // decode_OP_SOP2__S_MAX_U32
4235 
4236  GPUStaticInst*
4238  {
4239  return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
4240  } // decode_OP_SOP2__S_CSELECT_B32
4241 
4242  GPUStaticInst*
4244  {
4245  return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
4246  } // decode_OP_SOP2__S_CSELECT_B64
4247 
4248  GPUStaticInst*
4250  {
4251  return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
4252  } // decode_OP_SOP2__S_AND_B32
4253 
4254  GPUStaticInst*
4256  {
4257  return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
4258  } // decode_OP_SOP2__S_AND_B64
4259 
4260  GPUStaticInst*
4262  {
4263  return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
4264  } // decode_OP_SOP2__S_OR_B32
4265 
4266  GPUStaticInst*
4268  {
4269  return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
4270  } // decode_OP_SOP2__S_OR_B64
4271 
4272  GPUStaticInst*
4274  {
4275  return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
4276  } // decode_OP_SOP2__S_XOR_B32
4277 
4278  GPUStaticInst*
4280  {
4281  return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
4282  } // decode_OP_SOP2__S_XOR_B64
4283 
4284  GPUStaticInst*
4286  {
4287  return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
4288  } // decode_OP_SOP2__S_ANDN2_B32
4289 
4290  GPUStaticInst*
4292  {
4293  return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
4294  } // decode_OP_SOP2__S_ANDN2_B64
4295 
4296  GPUStaticInst*
4298  {
4299  return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
4300  } // decode_OP_SOP2__S_ORN2_B32
4301 
4302  GPUStaticInst*
4304  {
4305  return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
4306  } // decode_OP_SOP2__S_ORN2_B64
4307 
4308  GPUStaticInst*
4310  {
4311  return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
4312  } // decode_OP_SOP2__S_NAND_B32
4313 
4314  GPUStaticInst*
4316  {
4317  return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
4318  } // decode_OP_SOP2__S_NAND_B64
4319 
4320  GPUStaticInst*
4322  {
4323  return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
4324  } // decode_OP_SOP2__S_NOR_B32
4325 
4326  GPUStaticInst*
4328  {
4329  return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
4330  } // decode_OP_SOP2__S_NOR_B64
4331 
4332  GPUStaticInst*
4334  {
4335  return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
4336  } // decode_OP_SOP2__S_XNOR_B32
4337 
4338  GPUStaticInst*
4340  {
4341  return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
4342  } // decode_OP_SOP2__S_XNOR_B64
4343 
4344  GPUStaticInst*
4346  {
4347  return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
4348  } // decode_OP_SOP2__S_LSHL_B32
4349 
4350  GPUStaticInst*
4352  {
4353  return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
4354  } // decode_OP_SOP2__S_LSHL_B64
4355 
4356  GPUStaticInst*
4358  {
4359  return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
4360  } // decode_OP_SOP2__S_LSHR_B32
4361 
4362  GPUStaticInst*
4364  {
4365  return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
4366  } // decode_OP_SOP2__S_LSHR_B64
4367 
4368  GPUStaticInst*
4370  {
4371  return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
4372  } // decode_OP_SOP2__S_ASHR_I32
4373 
4374  GPUStaticInst*
4376  {
4377  return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
4378  } // decode_OP_SOP2__S_ASHR_I64
4379 
4380  GPUStaticInst*
4382  {
4383  return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
4384  } // decode_OP_SOP2__S_BFM_B32
4385 
4386  GPUStaticInst*
4388  {
4389  return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
4390  } // decode_OP_SOP2__S_BFM_B64
4391 
4392  GPUStaticInst*
4394  {
4395  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
4396  } // decode_OP_SOP2__S_MUL_I32
4397 
4398  GPUStaticInst*
4400  {
4401  return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
4402  } // decode_OP_SOP2__S_BFE_U32
4403 
4404  GPUStaticInst*
4406  {
4407  return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
4408  } // decode_OP_SOP2__S_BFE_I32
4409 
4410  GPUStaticInst*
4412  {
4413  return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
4414  } // decode_OP_SOP2__S_BFE_U64
4415 
4416  GPUStaticInst*
4418  {
4419  return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
4420  } // decode_OP_SOP2__S_BFE_I64
4421 
4422  GPUStaticInst*
4424  {
4425  return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
4426  } // decode_OP_SOP2__S_CBRANCH_G_FORK
4427 
4428  GPUStaticInst*
4430  {
4431  return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
4432  } // decode_OP_SOP2__S_ABSDIFF_I32
4433 
4434  GPUStaticInst*
4436  {
4437  return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
4438  } // decode_OP_SOP2__S_RFE_RESTORE_B64
4439 
4440  GPUStaticInst*
4442  {
4443  return nullptr;
4444  }
4445 
4446  GPUStaticInst*
4448  {
4449  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
4450  }
4451 
4452  GPUStaticInst*
4454  {
4455  return nullptr;
4456  }
4457 
4458  GPUStaticInst*
4460  {
4461  return nullptr;
4462  }
4463 
4464  GPUStaticInst*
4466  {
4467  return nullptr;
4468  }
4469 
4470  GPUStaticInst*
4472  {
4473  return nullptr;
4474  }
4475 
4476  GPUStaticInst*
4478  {
4479  return nullptr;
4480  }
4481 
4482  GPUStaticInst*
4484  {
4485  return nullptr;
4486  }
4487 
4488  GPUStaticInst*
4490  {
4491  return nullptr;
4492  }
4493 
4494  GPUStaticInst*
4496  {
4497  return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
4498  } // decode_OP_SOPK__S_MOVK_I32
4499 
4500  GPUStaticInst*
4502  {
4503  return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
4504  } // decode_OP_SOPK__S_CMOVK_I32
4505 
4506  GPUStaticInst*
4508  {
4509  return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
4510  } // decode_OP_SOPK__S_CMPK_EQ_I32
4511 
4512  GPUStaticInst*
4514  {
4515  return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
4516  } // decode_OP_SOPK__S_CMPK_LG_I32
4517 
4518  GPUStaticInst*
4520  {
4521  return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
4522  } // decode_OP_SOPK__S_CMPK_GT_I32
4523 
4524  GPUStaticInst*
4526  {
4527  return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
4528  } // decode_OP_SOPK__S_CMPK_GE_I32
4529 
4530  GPUStaticInst*
4532  {
4533  return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
4534  } // decode_OP_SOPK__S_CMPK_LT_I32
4535 
4536  GPUStaticInst*
4538  {
4539  return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
4540  } // decode_OP_SOPK__S_CMPK_LE_I32
4541 
4542  GPUStaticInst*
4544  {
4545  return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
4546  } // decode_OP_SOPK__S_CMPK_EQ_U32
4547 
4548  GPUStaticInst*
4550  {
4551  return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
4552  } // decode_OP_SOPK__S_CMPK_LG_U32
4553 
4554  GPUStaticInst*
4556  {
4557  return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
4558  } // decode_OP_SOPK__S_CMPK_GT_U32
4559 
4560  GPUStaticInst*
4562  {
4563  return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
4564  } // decode_OP_SOPK__S_CMPK_GE_U32
4565 
4566  GPUStaticInst*
4568  {
4569  return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
4570  } // decode_OP_SOPK__S_CMPK_LT_U32
4571 
4572  GPUStaticInst*
4574  {
4575  return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
4576  } // decode_OP_SOPK__S_CMPK_LE_U32
4577 
4578  GPUStaticInst*
4580  {
4581  return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
4582  } // decode_OP_SOPK__S_ADDK_I32
4583 
4584  GPUStaticInst*
4586  {
4587  return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
4588  } // decode_OP_SOPK__S_MULK_I32
4589 
4590  GPUStaticInst*
4592  {
4593  return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
4594  } // decode_OP_SOPK__S_CBRANCH_I_FORK
4595 
4596  GPUStaticInst*
4598  {
4599  return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
4600  } // decode_OP_SOPK__S_GETREG_B32
4601 
4602  GPUStaticInst*
4604  {
4605  return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
4606  } // decode_OP_SOPK__S_SETREG_B32
4607 
4608  GPUStaticInst*
4610  {
4611  return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
4612  } // decode_OP_SOPK__S_SETREG_IMM32_B32
4613 
4614  GPUStaticInst*
4616  {
4617  return nullptr;
4618  }
4619 
4620  GPUStaticInst*
4622  {
4623  return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
4624  } // decode_OP_EXP
4625 
4626  GPUStaticInst*
4628  {
4629  return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3A);
4630  } // decode_OPU_VOP3__V_CMP_CLASS_F32
4631 
4632  GPUStaticInst*
4634  {
4635  return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3A);
4636  } // decode_OPU_VOP3__V_CMPX_CLASS_F32
4637 
4638  GPUStaticInst*
4640  {
4641  return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3A);
4642  } // decode_OPU_VOP3__V_CMP_CLASS_F64
4643 
4644  GPUStaticInst*
4646  {
4647  return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3A);
4648  } // decode_OPU_VOP3__V_CMPX_CLASS_F64
4649 
4650  GPUStaticInst*
4652  {
4653  return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3A);
4654  } // decode_OPU_VOP3__V_CMP_CLASS_F16
4655 
4656  GPUStaticInst*
4658  {
4659  return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3A);
4660  } // decode_OPU_VOP3__V_CMPX_CLASS_F16
4661 
4662  GPUStaticInst*
4664  {
4665  return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3A);
4666  } // decode_OPU_VOP3__V_CMP_F_F16
4667 
4668  GPUStaticInst*
4670  {
4671  return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3A);
4672  } // decode_OPU_VOP3__V_CMP_LT_F16
4673 
4674  GPUStaticInst*
4676  {
4677  return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3A);
4678  } // decode_OPU_VOP3__V_CMP_EQ_F16
4679 
4680  GPUStaticInst*
4682  {
4683  return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3A);
4684  } // decode_OPU_VOP3__V_CMP_LE_F16
4685 
4686  GPUStaticInst*
4688  {
4689  return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3A);
4690  } // decode_OPU_VOP3__V_CMP_GT_F16
4691 
4692  GPUStaticInst*
4694  {
4695  return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3A);
4696  } // decode_OPU_VOP3__V_CMP_LG_F16
4697 
4698  GPUStaticInst*
4700  {
4701  return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3A);
4702  } // decode_OPU_VOP3__V_CMP_GE_F16
4703 
4704  GPUStaticInst*
4706  {
4707  return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3A);
4708  } // decode_OPU_VOP3__V_CMP_O_F16
4709 
4710  GPUStaticInst*
4712  {
4713  return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3A);
4714  } // decode_OPU_VOP3__V_CMP_U_F16
4715 
4716  GPUStaticInst*
4718  {
4719  return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3A);
4720  } // decode_OPU_VOP3__V_CMP_NGE_F16
4721 
4722  GPUStaticInst*
4724  {
4725  return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3A);
4726  } // decode_OPU_VOP3__V_CMP_NLG_F16
4727 
4728  GPUStaticInst*
4730  {
4731  return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3A);
4732  } // decode_OPU_VOP3__V_CMP_NGT_F16
4733 
4734  GPUStaticInst*
4736  {
4737  return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3A);
4738  } // decode_OPU_VOP3__V_CMP_NLE_F16
4739 
4740  GPUStaticInst*
4742  {
4743  return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3A);
4744  } // decode_OPU_VOP3__V_CMP_NEQ_F16
4745 
4746  GPUStaticInst*
4748  {
4749  return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3A);
4750  } // decode_OPU_VOP3__V_CMP_NLT_F16
4751 
4752  GPUStaticInst*
4754  {
4755  return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3A);
4756  } // decode_OPU_VOP3__V_CMP_TRU_F16
4757 
4758  GPUStaticInst*
4760  {
4761  return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3A);
4762  } // decode_OPU_VOP3__V_CMPX_F_F16
4763 
4764  GPUStaticInst*
4766  {
4767  return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3A);
4768  } // decode_OPU_VOP3__V_CMPX_LT_F16
4769 
4770  GPUStaticInst*
4772  {
4773  return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3A);
4774  } // decode_OPU_VOP3__V_CMPX_EQ_F16
4775 
4776  GPUStaticInst*
4778  {
4779  return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3A);
4780  } // decode_OPU_VOP3__V_CMPX_LE_F16
4781 
4782  GPUStaticInst*
4784  {
4785  return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3A);
4786  } // decode_OPU_VOP3__V_CMPX_GT_F16
4787 
4788  GPUStaticInst*
4790  {
4791  return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3A);
4792  } // decode_OPU_VOP3__V_CMPX_LG_F16
4793 
4794  GPUStaticInst*
4796  {
4797  return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3A);
4798  } // decode_OPU_VOP3__V_CMPX_GE_F16
4799 
4800  GPUStaticInst*
4802  {
4803  return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3A);
4804  } // decode_OPU_VOP3__V_CMPX_O_F16
4805 
4806  GPUStaticInst*
4808  {
4809  return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3A);
4810  } // decode_OPU_VOP3__V_CMPX_U_F16
4811 
4812  GPUStaticInst*
4814  {
4815  return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3A);
4816  } // decode_OPU_VOP3__V_CMPX_NGE_F16
4817 
4818  GPUStaticInst*
4820  {
4821  return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3A);
4822  } // decode_OPU_VOP3__V_CMPX_NLG_F16
4823 
4824  GPUStaticInst*
4826  {
4827  return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3A);
4828  } // decode_OPU_VOP3__V_CMPX_NGT_F16
4829 
4830  GPUStaticInst*
4832  {
4833  return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3A);
4834  } // decode_OPU_VOP3__V_CMPX_NLE_F16
4835 
4836  GPUStaticInst*
4838  {
4839  return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3A);
4840  } // decode_OPU_VOP3__V_CMPX_NEQ_F16
4841 
4842  GPUStaticInst*
4844  {
4845  return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3A);
4846  } // decode_OPU_VOP3__V_CMPX_NLT_F16
4847 
4848  GPUStaticInst*
4850  {
4851  return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3A);
4852  } // decode_OPU_VOP3__V_CMPX_TRU_F16
4853 
4854  GPUStaticInst*
4856  {
4857  return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3A);
4858  } // decode_OPU_VOP3__V_CMP_F_F32
4859 
4860  GPUStaticInst*
4862  {
4863  return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3A);
4864  } // decode_OPU_VOP3__V_CMP_LT_F32
4865 
4866  GPUStaticInst*
4868  {
4869  return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3A);
4870  } // decode_OPU_VOP3__V_CMP_EQ_F32
4871 
4872  GPUStaticInst*
4874  {
4875  return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3A);
4876  } // decode_OPU_VOP3__V_CMP_LE_F32
4877 
4878  GPUStaticInst*
4880  {
4881  return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3A);
4882  } // decode_OPU_VOP3__V_CMP_GT_F32
4883 
4884  GPUStaticInst*
4886  {
4887  return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3A);
4888  } // decode_OPU_VOP3__V_CMP_LG_F32
4889 
4890  GPUStaticInst*
4892  {
4893  return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3A);
4894  } // decode_OPU_VOP3__V_CMP_GE_F32
4895 
4896  GPUStaticInst*
4898  {
4899  return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3A);
4900  } // decode_OPU_VOP3__V_CMP_O_F32
4901 
4902  GPUStaticInst*
4904  {
4905  return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3A);
4906  } // decode_OPU_VOP3__V_CMP_U_F32
4907 
4908  GPUStaticInst*
4910  {
4911  return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3A);
4912  } // decode_OPU_VOP3__V_CMP_NGE_F32
4913 
4914  GPUStaticInst*
4916  {
4917  return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3A);
4918  } // decode_OPU_VOP3__V_CMP_NLG_F32
4919 
4920  GPUStaticInst*
4922  {
4923  return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3A);
4924  } // decode_OPU_VOP3__V_CMP_NGT_F32
4925 
4926  GPUStaticInst*
4928  {
4929  return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3A);
4930  } // decode_OPU_VOP3__V_CMP_NLE_F32
4931 
4932  GPUStaticInst*
4934  {
4935  return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3A);
4936  } // decode_OPU_VOP3__V_CMP_NEQ_F32
4937 
4938  GPUStaticInst*
4940  {
4941  return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3A);
4942  } // decode_OPU_VOP3__V_CMP_NLT_F32
4943 
4944  GPUStaticInst*
4946  {
4947  return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3A);
4948  } // decode_OPU_VOP3__V_CMP_TRU_F32
4949 
4950  GPUStaticInst*
4952  {
4953  return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3A);
4954  } // decode_OPU_VOP3__V_CMPX_F_F32
4955 
4956  GPUStaticInst*
4958  {
4959  return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3A);
4960  } // decode_OPU_VOP3__V_CMPX_LT_F32
4961 
4962  GPUStaticInst*
4964  {
4965  return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3A);
4966  } // decode_OPU_VOP3__V_CMPX_EQ_F32
4967 
4968  GPUStaticInst*
4970  {
4971  return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3A);
4972  } // decode_OPU_VOP3__V_CMPX_LE_F32
4973 
4974  GPUStaticInst*
4976  {
4977  return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3A);
4978  } // decode_OPU_VOP3__V_CMPX_GT_F32
4979 
4980  GPUStaticInst*
4982  {
4983  return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3A);
4984  } // decode_OPU_VOP3__V_CMPX_LG_F32
4985 
4986  GPUStaticInst*
4988  {
4989  return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3A);
4990  } // decode_OPU_VOP3__V_CMPX_GE_F32
4991 
4992  GPUStaticInst*
4994  {
4995  return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3A);
4996  } // decode_OPU_VOP3__V_CMPX_O_F32
4997 
4998  GPUStaticInst*
5000  {
5001  return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3A);
5002  } // decode_OPU_VOP3__V_CMPX_U_F32
5003 
5004  GPUStaticInst*
5006  {
5007  return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3A);
5008  } // decode_OPU_VOP3__V_CMPX_NGE_F32
5009 
5010  GPUStaticInst*
5012  {
5013  return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3A);
5014  } // decode_OPU_VOP3__V_CMPX_NLG_F32
5015 
5016  GPUStaticInst*
5018  {
5019  return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3A);
5020  } // decode_OPU_VOP3__V_CMPX_NGT_F32
5021 
5022  GPUStaticInst*
5024  {
5025  return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3A);
5026  } // decode_OPU_VOP3__V_CMPX_NLE_F32
5027 
5028  GPUStaticInst*
5030  {
5031  return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3A);
5032  } // decode_OPU_VOP3__V_CMPX_NEQ_F32
5033 
5034  GPUStaticInst*
5036  {
5037  return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3A);
5038  } // decode_OPU_VOP3__V_CMPX_NLT_F32
5039 
5040  GPUStaticInst*
5042  {
5043  return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3A);
5044  } // decode_OPU_VOP3__V_CMPX_TRU_F32
5045 
5046  GPUStaticInst*
5048  {
5049  return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3A);
5050  } // decode_OPU_VOP3__V_CMP_F_F64
5051 
5052  GPUStaticInst*
5054  {
5055  return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3A);
5056  } // decode_OPU_VOP3__V_CMP_LT_F64
5057 
5058  GPUStaticInst*
5060  {
5061  return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3A);
5062  } // decode_OPU_VOP3__V_CMP_EQ_F64
5063 
5064  GPUStaticInst*
5066  {
5067  return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3A);
5068  } // decode_OPU_VOP3__V_CMP_LE_F64
5069 
5070  GPUStaticInst*
5072  {
5073  return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3A);
5074  } // decode_OPU_VOP3__V_CMP_GT_F64
5075 
5076  GPUStaticInst*
5078  {
5079  return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3A);
5080  } // decode_OPU_VOP3__V_CMP_LG_F64
5081 
5082  GPUStaticInst*
5084  {
5085  return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3A);
5086  } // decode_OPU_VOP3__V_CMP_GE_F64
5087 
5088  GPUStaticInst*
5090  {
5091  return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3A);
5092  } // decode_OPU_VOP3__V_CMP_O_F64
5093 
5094  GPUStaticInst*
5096  {
5097  return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3A);
5098  } // decode_OPU_VOP3__V_CMP_U_F64
5099 
5100  GPUStaticInst*
5102  {
5103  return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3A);
5104  } // decode_OPU_VOP3__V_CMP_NGE_F64
5105 
5106  GPUStaticInst*
5108  {
5109  return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3A);
5110  } // decode_OPU_VOP3__V_CMP_NLG_F64
5111 
5112  GPUStaticInst*
5114  {
5115  return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3A);
5116  } // decode_OPU_VOP3__V_CMP_NGT_F64
5117 
5118  GPUStaticInst*
5120  {
5121  return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3A);
5122  } // decode_OPU_VOP3__V_CMP_NLE_F64
5123 
5124  GPUStaticInst*
5126  {
5127  return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3A);
5128  } // decode_OPU_VOP3__V_CMP_NEQ_F64
5129 
5130  GPUStaticInst*
5132  {
5133  return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3A);
5134  } // decode_OPU_VOP3__V_CMP_NLT_F64
5135 
5136  GPUStaticInst*
5138  {
5139  return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3A);
5140  } // decode_OPU_VOP3__V_CMP_TRU_F64
5141 
5142  GPUStaticInst*
5144  {
5145  return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3A);
5146  } // decode_OPU_VOP3__V_CMPX_F_F64
5147 
5148  GPUStaticInst*
5150  {
5151  return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3A);
5152  } // decode_OPU_VOP3__V_CMPX_LT_F64
5153 
5154  GPUStaticInst*
5156  {
5157  return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3A);
5158  } // decode_OPU_VOP3__V_CMPX_EQ_F64
5159 
5160  GPUStaticInst*
5162  {
5163  return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3A);
5164  } // decode_OPU_VOP3__V_CMPX_LE_F64
5165 
5166  GPUStaticInst*
5168  {
5169  return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3A);
5170  } // decode_OPU_VOP3__V_CMPX_GT_F64
5171 
5172  GPUStaticInst*
5174  {
5175  return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3A);
5176  } // decode_OPU_VOP3__V_CMPX_LG_F64
5177 
5178  GPUStaticInst*
5180  {
5181  return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3A);
5182  } // decode_OPU_VOP3__V_CMPX_GE_F64
5183 
5184  GPUStaticInst*
5186  {
5187  return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3A);
5188  } // decode_OPU_VOP3__V_CMPX_O_F64
5189 
5190  GPUStaticInst*
5192  {
5193  return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3A);
5194  } // decode_OPU_VOP3__V_CMPX_U_F64
5195 
5196  GPUStaticInst*
5198  {
5199  return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3A);
5200  } // decode_OPU_VOP3__V_CMPX_NGE_F64
5201 
5202  GPUStaticInst*
5204  {
5205  return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3A);
5206  } // decode_OPU_VOP3__V_CMPX_NLG_F64
5207 
5208  GPUStaticInst*
5210  {
5211  return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3A);
5212  } // decode_OPU_VOP3__V_CMPX_NGT_F64
5213 
5214  GPUStaticInst*
5216  {
5217  return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3A);
5218  } // decode_OPU_VOP3__V_CMPX_NLE_F64
5219 
5220  GPUStaticInst*
5222  {
5223  return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3A);
5224  } // decode_OPU_VOP3__V_CMPX_NEQ_F64
5225 
5226  GPUStaticInst*
5228  {
5229  return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3A);
5230  } // decode_OPU_VOP3__V_CMPX_NLT_F64
5231 
5232  GPUStaticInst*
5234  {
5235  return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3A);
5236  } // decode_OPU_VOP3__V_CMPX_TRU_F64
5237 
5238  GPUStaticInst*
5240  {
5241  return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3A);
5242  } // decode_OPU_VOP3__V_CMP_F_I16
5243 
5244  GPUStaticInst*
5246  {
5247  return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3A);
5248  } // decode_OPU_VOP3__V_CMP_LT_I16
5249 
5250  GPUStaticInst*
5252  {
5253  return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3A);
5254  } // decode_OPU_VOP3__V_CMP_EQ_I16
5255 
5256  GPUStaticInst*
5258  {
5259  return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3A);
5260  } // decode_OPU_VOP3__V_CMP_LE_I16
5261 
5262  GPUStaticInst*
5264  {
5265  return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3A);
5266  } // decode_OPU_VOP3__V_CMP_GT_I16
5267 
5268  GPUStaticInst*
5270  {
5271  return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3A);
5272  } // decode_OPU_VOP3__V_CMP_NE_I16
5273 
5274  GPUStaticInst*
5276  {
5277  return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3A);
5278  } // decode_OPU_VOP3__V_CMP_GE_I16
5279 
5280  GPUStaticInst*
5282  {
5283  return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3A);
5284  } // decode_OPU_VOP3__V_CMP_T_I16
5285 
5286  GPUStaticInst*
5288  {
5289  return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3A);
5290  } // decode_OPU_VOP3__V_CMP_F_U16
5291 
5292  GPUStaticInst*
5294  {
5295  return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3A);
5296  } // decode_OPU_VOP3__V_CMP_LT_U16
5297 
5298  GPUStaticInst*
5300  {
5301  return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3A);
5302  } // decode_OPU_VOP3__V_CMP_EQ_U16
5303 
5304  GPUStaticInst*
5306  {
5307  return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3A);
5308  } // decode_OPU_VOP3__V_CMP_LE_U16
5309 
5310  GPUStaticInst*
5312  {
5313  return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3A);
5314  } // decode_OPU_VOP3__V_CMP_GT_U16
5315 
5316  GPUStaticInst*
5318  {
5319  return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3A);
5320  } // decode_OPU_VOP3__V_CMP_NE_U16
5321 
5322  GPUStaticInst*
5324  {
5325  return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3A);
5326  } // decode_OPU_VOP3__V_CMP_GE_U16
5327 
5328  GPUStaticInst*
5330  {
5331  return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3A);
5332  } // decode_OPU_VOP3__V_CMP_T_U16
5333 
5334  GPUStaticInst*
5336  {
5337  return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3A);
5338  } // decode_OPU_VOP3__V_CMPX_F_I16
5339 
5340  GPUStaticInst*
5342  {
5343  return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3A);
5344  } // decode_OPU_VOP3__V_CMPX_LT_I16
5345 
5346  GPUStaticInst*
5348  {
5349  return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3A);
5350  } // decode_OPU_VOP3__V_CMPX_EQ_I16
5351 
5352  GPUStaticInst*
5354  {
5355  return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3A);
5356  } // decode_OPU_VOP3__V_CMPX_LE_I16
5357 
5358  GPUStaticInst*
5360  {
5361  return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3A);
5362  } // decode_OPU_VOP3__V_CMPX_GT_I16
5363 
5364  GPUStaticInst*
5366  {
5367  return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3A);
5368  } // decode_OPU_VOP3__V_CMPX_NE_I16
5369 
5370  GPUStaticInst*
5372  {
5373  return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3A);
5374  } // decode_OPU_VOP3__V_CMPX_GE_I16
5375 
5376  GPUStaticInst*
5378  {
5379  return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3A);
5380  } // decode_OPU_VOP3__V_CMPX_T_I16
5381 
5382  GPUStaticInst*
5384  {
5385  return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3A);
5386  } // decode_OPU_VOP3__V_CMPX_F_U16
5387 
5388  GPUStaticInst*
5390  {
5391  return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3A);
5392  } // decode_OPU_VOP3__V_CMPX_LT_U16
5393 
5394  GPUStaticInst*
5396  {
5397  return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3A);
5398  } // decode_OPU_VOP3__V_CMPX_EQ_U16
5399 
5400  GPUStaticInst*
5402  {
5403  return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3A);
5404  } // decode_OPU_VOP3__V_CMPX_LE_U16
5405 
5406  GPUStaticInst*
5408  {
5409  return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3A);
5410  } // decode_OPU_VOP3__V_CMPX_GT_U16
5411 
5412  GPUStaticInst*
5414  {
5415  return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3A);
5416  } // decode_OPU_VOP3__V_CMPX_NE_U16
5417 
5418  GPUStaticInst*
5420  {
5421  return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3A);
5422  } // decode_OPU_VOP3__V_CMPX_GE_U16
5423 
5424  GPUStaticInst*
5426  {
5427  return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3A);
5428  } // decode_OPU_VOP3__V_CMPX_T_U16
5429 
5430  GPUStaticInst*
5432  {
5433  return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3A);
5434  } // decode_OPU_VOP3__V_CMP_F_I32
5435 
5436  GPUStaticInst*
5438  {
5439  return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3A);
5440  } // decode_OPU_VOP3__V_CMP_LT_I32
5441 
5442  GPUStaticInst*
5444  {
5445  return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3A);
5446  } // decode_OPU_VOP3__V_CMP_EQ_I32
5447 
5448  GPUStaticInst*
5450  {
5451  return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3A);
5452  } // decode_OPU_VOP3__V_CMP_LE_I32
5453 
5454  GPUStaticInst*
5456  {
5457  return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3A);
5458  } // decode_OPU_VOP3__V_CMP_GT_I32
5459 
5460  GPUStaticInst*
5462  {
5463  return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3A);
5464  } // decode_OPU_VOP3__V_CMP_NE_I32
5465 
5466  GPUStaticInst*
5468  {
5469  return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3A);
5470  } // decode_OPU_VOP3__V_CMP_GE_I32
5471 
5472  GPUStaticInst*
5474  {
5475  return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3A);
5476  } // decode_OPU_VOP3__V_CMP_T_I32
5477 
5478  GPUStaticInst*
5480  {
5481  return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3A);
5482  } // decode_OPU_VOP3__V_CMP_F_U32
5483 
5484  GPUStaticInst*
5486  {
5487  return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3A);
5488  } // decode_OPU_VOP3__V_CMP_LT_U32
5489 
5490  GPUStaticInst*
5492  {
5493  return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3A);
5494  } // decode_OPU_VOP3__V_CMP_EQ_U32
5495 
5496  GPUStaticInst*
5498  {
5499  return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3A);
5500  } // decode_OPU_VOP3__V_CMP_LE_U32
5501 
5502  GPUStaticInst*
5504  {
5505  return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3A);
5506  } // decode_OPU_VOP3__V_CMP_GT_U32
5507 
5508  GPUStaticInst*
5510  {
5511  return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3A);
5512  } // decode_OPU_VOP3__V_CMP_NE_U32
5513 
5514  GPUStaticInst*
5516  {
5517  return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3A);
5518  } // decode_OPU_VOP3__V_CMP_GE_U32
5519 
5520  GPUStaticInst*
5522  {
5523  return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3A);
5524  } // decode_OPU_VOP3__V_CMP_T_U32
5525 
5526  GPUStaticInst*
5528  {
5529  return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3A);
5530  } // decode_OPU_VOP3__V_CMPX_F_I32
5531 
5532  GPUStaticInst*
5534  {
5535  return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3A);
5536  } // decode_OPU_VOP3__V_CMPX_LT_I32
5537 
5538  GPUStaticInst*
5540  {
5541  return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3A);
5542  } // decode_OPU_VOP3__V_CMPX_EQ_I32
5543 
5544  GPUStaticInst*
5546  {
5547  return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3A);
5548  } // decode_OPU_VOP3__V_CMPX_LE_I32
5549 
5550  GPUStaticInst*
5552  {
5553  return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3A);
5554  } // decode_OPU_VOP3__V_CMPX_GT_I32
5555 
5556  GPUStaticInst*
5558  {
5559  return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3A);
5560  } // decode_OPU_VOP3__V_CMPX_NE_I32
5561 
5562  GPUStaticInst*
5564  {
5565  return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3A);
5566  } // decode_OPU_VOP3__V_CMPX_GE_I32
5567 
5568  GPUStaticInst*
5570  {
5571  return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3A);
5572  } // decode_OPU_VOP3__V_CMPX_T_I32
5573 
5574  GPUStaticInst*
5576  {
5577  return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3A);
5578  } // decode_OPU_VOP3__V_CMPX_F_U32
5579 
5580  GPUStaticInst*
5582  {
5583  return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3A);
5584  } // decode_OPU_VOP3__V_CMPX_LT_U32
5585 
5586  GPUStaticInst*
5588  {
5589  return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3A);
5590  } // decode_OPU_VOP3__V_CMPX_EQ_U32
5591 
5592  GPUStaticInst*
5594  {
5595  return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3A);
5596  } // decode_OPU_VOP3__V_CMPX_LE_U32
5597 
5598  GPUStaticInst*
5600  {
5601  return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3A);
5602  } // decode_OPU_VOP3__V_CMPX_GT_U32
5603 
5604  GPUStaticInst*
5606  {
5607  return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3A);
5608  } // decode_OPU_VOP3__V_CMPX_NE_U32
5609 
5610  GPUStaticInst*
5612  {
5613  return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3A);
5614  } // decode_OPU_VOP3__V_CMPX_GE_U32
5615 
5616  GPUStaticInst*
5618  {
5619  return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3A);
5620  } // decode_OPU_VOP3__V_CMPX_T_U32
5621 
5622  GPUStaticInst*
5624  {
5625  return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3A);
5626  } // decode_OPU_VOP3__V_CMP_F_I64
5627 
5628  GPUStaticInst*
5630  {
5631  return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3A);
5632  } // decode_OPU_VOP3__V_CMP_LT_I64
5633 
5634  GPUStaticInst*
5636  {
5637  return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3A);
5638  } // decode_OPU_VOP3__V_CMP_EQ_I64
5639 
5640  GPUStaticInst*
5642  {
5643  return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3A);
5644  } // decode_OPU_VOP3__V_CMP_LE_I64
5645 
5646  GPUStaticInst*
5648  {
5649  return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3A);
5650  } // decode_OPU_VOP3__V_CMP_GT_I64
5651 
5652  GPUStaticInst*
5654  {
5655  return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3A);
5656  } // decode_OPU_VOP3__V_CMP_NE_I64
5657 
5658  GPUStaticInst*
5660  {
5661  return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3A);
5662  } // decode_OPU_VOP3__V_CMP_GE_I64
5663 
5664  GPUStaticInst*
5666  {
5667  return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3A);
5668  } // decode_OPU_VOP3__V_CMP_T_I64
5669 
5670  GPUStaticInst*
5672  {
5673  return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3A);
5674  } // decode_OPU_VOP3__V_CMP_F_U64
5675 
5676  GPUStaticInst*
5678  {
5679  return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3A);
5680  } // decode_OPU_VOP3__V_CMP_LT_U64
5681 
5682  GPUStaticInst*
5684  {
5685  return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3A);
5686  } // decode_OPU_VOP3__V_CMP_EQ_U64
5687 
5688  GPUStaticInst*
5690  {
5691  return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3A);
5692  } // decode_OPU_VOP3__V_CMP_LE_U64
5693 
5694  GPUStaticInst*
5696  {
5697  return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3A);
5698  } // decode_OPU_VOP3__V_CMP_GT_U64
5699 
5700  GPUStaticInst*
5702  {
5703  return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3A);
5704  } // decode_OPU_VOP3__V_CMP_NE_U64
5705 
5706  GPUStaticInst*
5708  {
5709  return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3A);
5710  } // decode_OPU_VOP3__V_CMP_GE_U64
5711 
5712  GPUStaticInst*
5714  {
5715  return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3A);
5716  } // decode_OPU_VOP3__V_CMP_T_U64
5717 
5718  GPUStaticInst*
5720  {
5721  return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3A);
5722  } // decode_OPU_VOP3__V_CMPX_F_I64
5723 
5724  GPUStaticInst*
5726  {
5727  return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3A);
5728  } // decode_OPU_VOP3__V_CMPX_LT_I64
5729 
5730  GPUStaticInst*
5732  {
5733  return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3A);
5734  } // decode_OPU_VOP3__V_CMPX_EQ_I64
5735 
5736  GPUStaticInst*
5738  {
5739  return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3A);
5740  } // decode_OPU_VOP3__V_CMPX_LE_I64
5741 
5742  GPUStaticInst*
5744  {
5745  return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3A);
5746  } // decode_OPU_VOP3__V_CMPX_GT_I64
5747 
5748  GPUStaticInst*
5750  {
5751  return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3A);
5752  } // decode_OPU_VOP3__V_CMPX_NE_I64
5753 
5754  GPUStaticInst*
5756  {
5757  return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3A);
5758  } // decode_OPU_VOP3__V_CMPX_GE_I64
5759 
5760  GPUStaticInst*
5762  {
5763  return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3A);
5764  } // decode_OPU_VOP3__V_CMPX_T_I64
5765 
5766  GPUStaticInst*
5768  {
5769  return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3A);
5770  } // decode_OPU_VOP3__V_CMPX_F_U64
5771 
5772  GPUStaticInst*
5774  {
5775  return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3A);
5776  } // decode_OPU_VOP3__V_CMPX_LT_U64
5777 
5778  GPUStaticInst*
5780  {
5781  return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3A);
5782  } // decode_OPU_VOP3__V_CMPX_EQ_U64
5783 
5784  GPUStaticInst*
5786  {
5787  return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3A);
5788  } // decode_OPU_VOP3__V_CMPX_LE_U64
5789 
5790  GPUStaticInst*
5792  {
5793  return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3A);
5794  } // decode_OPU_VOP3__V_CMPX_GT_U64
5795 
5796  GPUStaticInst*
5798  {
5799  return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3A);
5800  } // decode_OPU_VOP3__V_CMPX_NE_U64
5801 
5802  GPUStaticInst*
5804  {
5805  return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3A);
5806  } // decode_OPU_VOP3__V_CMPX_GE_U64
5807 
5808  GPUStaticInst*
5810  {
5811  return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3A);
5812  } // decode_OPU_VOP3__V_CMPX_T_U64
5813 
5814  GPUStaticInst*
5816  {
5817  return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3A);
5818  } // decode_OPU_VOP3__V_CNDMASK_B32
5819 
5820  GPUStaticInst*
5822  {
5823  return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3A);
5824  } // decode_OPU_VOP3__V_ADD_F32
5825 
5826  GPUStaticInst*
5828  {
5829  return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3A);
5830  } // decode_OPU_VOP3__V_SUB_F32
5831 
5832  GPUStaticInst*
5834  {
5835  return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3A);
5836  } // decode_OPU_VOP3__V_SUBREV_F32
5837 
5838  GPUStaticInst*
5840  {
5841  return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3A);
5842  } // decode_OPU_VOP3__V_MUL_LEGACY_F32
5843 
5844  GPUStaticInst*
5846  {
5847  return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3A);
5848  } // decode_OPU_VOP3__V_MUL_F32
5849 
5850  GPUStaticInst*
5852  {
5853  return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3A);
5854  } // decode_OPU_VOP3__V_MUL_I32_I24
5855 
5856  GPUStaticInst*
5858  {
5859  return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3A);
5860  } // decode_OPU_VOP3__V_MUL_HI_I32_I24
5861 
5862  GPUStaticInst*
5864  {
5865  return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3A);
5866  } // decode_OPU_VOP3__V_MUL_U32_U24
5867 
5868  GPUStaticInst*
5870  {
5871  return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3A);
5872  } // decode_OPU_VOP3__V_MUL_HI_U32_U24
5873 
5874  GPUStaticInst*
5876  {
5877  return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3A);
5878  } // decode_OPU_VOP3__V_MIN_F32
5879 
5880  GPUStaticInst*
5882  {
5883  return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3A);
5884  } // decode_OPU_VOP3__V_MAX_F32
5885 
5886  GPUStaticInst*
5888  {
5889  return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3A);
5890  } // decode_OPU_VOP3__V_MIN_I32
5891 
5892  GPUStaticInst*
5894  {
5895  return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3A);
5896  } // decode_OPU_VOP3__V_MAX_I32
5897 
5898  GPUStaticInst*
5900  {
5901  return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3A);
5902  } // decode_OPU_VOP3__V_MIN_U32
5903 
5904  GPUStaticInst*
5906  {
5907  return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3A);
5908  } // decode_OPU_VOP3__V_MAX_U32
5909 
5910  GPUStaticInst*
5912  {
5913  return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3A);
5914  } // decode_OPU_VOP3__V_LSHRREV_B32
5915 
5916  GPUStaticInst*
5918  {
5919  return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3A);
5920  } // decode_OPU_VOP3__V_ASHRREV_I32
5921 
5922  GPUStaticInst*
5924  {
5925  return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3A);
5926  } // decode_OPU_VOP3__V_LSHLREV_B32
5927 
5928  GPUStaticInst*
5930  {
5931  return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3A);
5932  } // decode_OPU_VOP3__V_AND_B32
5933 
5934  GPUStaticInst*
5936  {
5937  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
5938  } // decode_OPU_VOP3__V_OR_B32
5939 
5940  GPUStaticInst*
5942  {
5943  return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3A);
5944  } // decode_OPU_VOP3__V_XOR_B32
5945 
5946  GPUStaticInst*
5948  {
5949  return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3A);
5950  } // decode_OPU_VOP3__V_MAC_F32
5951 
5952  GPUStaticInst*
5954  {
5955  return new Inst_VOP3__V_ADD_CO_U32(&iFmt->iFmt_VOP3B);
5956  } // decode_OPU_VOP3__V_ADD_CO_U32
5957 
5958  GPUStaticInst*
5960  {
5961  return new Inst_VOP3__V_SUB_CO_U32(&iFmt->iFmt_VOP3B);
5962  } // decode_OPU_VOP3__V_SUB_CO_U32
5963 
5964  GPUStaticInst*
5966  {
5967  return new Inst_VOP3__V_SUBREV_CO_U32(&iFmt->iFmt_VOP3B);
5968  } // decode_OPU_VOP3__V_SUBREV_CO_U32
5969 
5970  GPUStaticInst*
5972  {
5973  return new Inst_VOP3__V_ADDC_CO_U32(&iFmt->iFmt_VOP3B);
5974  } // decode_OPU_VOP3__V_ADDC_CO_U32
5975 
5976  GPUStaticInst*
5978  {
5979  return new Inst_VOP3__V_SUBB_CO_U32(&iFmt->iFmt_VOP3B);
5980  } // decode_OPU_VOP3__V_SUBB_CO_U32
5981 
5982  GPUStaticInst*
5984  {
5985  return new Inst_VOP3__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP3B);
5986  } // decode_OPU_VOP3__V_SUBBREV_CO_U32
5987 
5988  GPUStaticInst*
5990  {
5991  return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3A);
5992  } // decode_OPU_VOP3__V_ADD_F16
5993 
5994  GPUStaticInst*
5996  {
5997  return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3A);
5998  } // decode_OPU_VOP3__V_SUB_F16
5999 
6000  GPUStaticInst*
6002  {
6003  return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3A);
6004  } // decode_OPU_VOP3__V_SUBREV_F16
6005 
6006  GPUStaticInst*
6008  {
6009  return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3A);
6010  } // decode_OPU_VOP3__V_MUL_F16
6011 
6012  GPUStaticInst*
6014  {
6015  return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3A);
6016  } // decode_OPU_VOP3__V_MAC_F16
6017 
6018  GPUStaticInst*
6020  {
6021  return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3A);
6022  } // decode_OPU_VOP3__V_ADD_U16
6023 
6024  GPUStaticInst*
6026  {
6027  return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3A);
6028  } // decode_OPU_VOP3__V_SUB_U16
6029 
6030  GPUStaticInst*
6032  {
6033  return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3A);
6034  } // decode_OPU_VOP3__V_SUBREV_U16
6035 
6036  GPUStaticInst*
6038  {
6039  return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3A);
6040  } // decode_OPU_VOP3__V_MUL_LO_U16
6041 
6042  GPUStaticInst*
6044  {
6045  return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3A);
6046  } // decode_OPU_VOP3__V_LSHLREV_B16
6047 
6048  GPUStaticInst*
6050  {
6051  return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3A);
6052  } // decode_OPU_VOP3__V_LSHRREV_B16
6053 
6054  GPUStaticInst*
6056  {
6057  return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3A);
6058  } // decode_OPU_VOP3__V_ASHRREV_I16
6059 
6060  GPUStaticInst*
6062  {
6063  return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3A);
6064  } // decode_OPU_VOP3__V_MAX_F16
6065 
6066  GPUStaticInst*
6068  {
6069  return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3A);
6070  } // decode_OPU_VOP3__V_MIN_F16
6071 
6072  GPUStaticInst*
6074  {
6075  return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3A);
6076  } // decode_OPU_VOP3__V_MAX_U16
6077 
6078  GPUStaticInst*
6080  {
6081  return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3A);
6082  } // decode_OPU_VOP3__V_MAX_I16
6083 
6084  GPUStaticInst*
6086  {
6087  return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3A);
6088  } // decode_OPU_VOP3__V_MIN_U16
6089 
6090  GPUStaticInst*
6092  {
6093  return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3A);
6094  } // decode_OPU_VOP3__V_MIN_I16
6095 
6096  GPUStaticInst*
6098  {
6099  return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3A);
6100  } // decode_OPU_VOP3__V_LDEXP_F16
6101 
6102  GPUStaticInst*
6104  {
6105  return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3A);
6106  } // decode_OPU_VOP3__V_NOP
6107 
6108  GPUStaticInst*
6110  {
6111  return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3A);
6112  } // decode_OPU_VOP3__V_MOV_B32
6113 
6114  GPUStaticInst*
6116  {
6117  return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3A);
6118  } // decode_OPU_VOP3__V_CVT_I32_F64
6119 
6120  GPUStaticInst*
6122  {
6123  return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3A);
6124  } // decode_OPU_VOP3__V_CVT_F64_I32
6125 
6126  GPUStaticInst*
6128  {
6129  return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3A);
6130  } // decode_OPU_VOP3__V_CVT_F32_I32
6131 
6132  GPUStaticInst*
6134  {
6135  return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3A);
6136  } // decode_OPU_VOP3__V_CVT_F32_U32
6137 
6138  GPUStaticInst*
6140  {
6141  return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3A);
6142  } // decode_OPU_VOP3__V_CVT_U32_F32
6143 
6144  GPUStaticInst*
6146  {
6147  return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3A);
6148  } // decode_OPU_VOP3__V_CVT_I32_F32
6149 
6150  GPUStaticInst*
6152  {
6153  return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3A);
6154  } // decode_OPU_VOP3__V_MOV_FED_B32
6155 
6156  GPUStaticInst*
6158  {
6159  return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3A);
6160  } // decode_OPU_VOP3__V_CVT_F16_F32
6161 
6162  GPUStaticInst*
6164  {
6165  return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3A);
6166  } // decode_OPU_VOP3__V_CVT_F32_F16
6167 
6168  GPUStaticInst*
6170  {
6171  return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3A);
6172  } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
6173 
6174  GPUStaticInst*
6176  {
6177  return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3A);
6178  } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
6179 
6180  GPUStaticInst*
6182  {
6183  return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3A);
6184  } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
6185 
6186  GPUStaticInst*
6188  {
6189  return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3A);
6190  } // decode_OPU_VOP3__V_CVT_F32_F64
6191 
6192  GPUStaticInst*
6194  {
6195  return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3A);
6196  } // decode_OPU_VOP3__V_CVT_F64_F32
6197 
6198  GPUStaticInst*
6200  {
6201  return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3A);
6202  } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
6203 
6204  GPUStaticInst*
6206  {
6207  return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3A);
6208  } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
6209 
6210  GPUStaticInst*
6212  {
6213  return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3A);
6214  } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
6215 
6216  GPUStaticInst*
6218  {
6219  return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3A);
6220  } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
6221 
6222  GPUStaticInst*
6224  {
6225  return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3A);
6226  } // decode_OPU_VOP3__V_CVT_U32_F64
6227 
6228  GPUStaticInst*
6230  {
6231  return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3A);
6232  } // decode_OPU_VOP3__V_CVT_F64_U32
6233 
6234  GPUStaticInst*
6236  {
6237  return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3A);
6238  } // decode_OPU_VOP3__V_TRUNC_F64
6239 
6240  GPUStaticInst*
6242  {
6243  return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3A);
6244  } // decode_OPU_VOP3__V_CEIL_F64
6245 
6246  GPUStaticInst*
6248  {
6249  return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3A);
6250  } // decode_OPU_VOP3__V_RNDNE_F64
6251 
6252  GPUStaticInst*
6254  {
6255  return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3A);
6256  } // decode_OPU_VOP3__V_FLOOR_F64
6257 
6258  GPUStaticInst*
6260  {
6261  return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3A);
6262  } // decode_OPU_VOP3__V_FRACT_F32
6263 
6264  GPUStaticInst*
6266  {
6267  return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3A);
6268  } // decode_OPU_VOP3__V_TRUNC_F32
6269 
6270  GPUStaticInst*
6272  {
6273  return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3A);
6274  } // decode_OPU_VOP3__V_CEIL_F32
6275 
6276  GPUStaticInst*
6278  {
6279  return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3A);
6280  } // decode_OPU_VOP3__V_RNDNE_F32
6281 
6282  GPUStaticInst*
6284  {
6285  return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3A);
6286  } // decode_OPU_VOP3__V_FLOOR_F32
6287 
6288  GPUStaticInst*
6290  {
6291  return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3A);
6292  } // decode_OPU_VOP3__V_EXP_F32
6293 
6294  GPUStaticInst*
6296  {
6297  return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3A);
6298  } // decode_OPU_VOP3__V_LOG_F32
6299 
6300  GPUStaticInst*
6302  {
6303  return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3A);
6304  } // decode_OPU_VOP3__V_RCP_F32
6305 
6306  GPUStaticInst*
6308  {
6309  return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3A);
6310  } // decode_OPU_VOP3__V_RCP_IFLAG_F32
6311 
6312  GPUStaticInst*
6314  {
6315  return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3A);
6316  } // decode_OPU_VOP3__V_RSQ_F32
6317 
6318  GPUStaticInst*
6320  {
6321  return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3A);
6322  } // decode_OPU_VOP3__V_RCP_F64
6323 
6324  GPUStaticInst*
6326  {
6327  return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3A);
6328  } // decode_OPU_VOP3__V_RSQ_F64
6329 
6330  GPUStaticInst*
6332  {
6333  return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3A);
6334  } // decode_OPU_VOP3__V_SQRT_F32
6335 
6336  GPUStaticInst*
6338  {
6339  return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3A);
6340  } // decode_OPU_VOP3__V_SQRT_F64
6341 
6342  GPUStaticInst*
6344  {
6345  return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3A);
6346  } // decode_OPU_VOP3__V_SIN_F32
6347 
6348  GPUStaticInst*
6350  {
6351  return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3A);
6352  } // decode_OPU_VOP3__V_COS_F32
6353 
6354  GPUStaticInst*
6356  {
6357  return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3A);
6358  } // decode_OPU_VOP3__V_NOT_B32
6359 
6360  GPUStaticInst*
6362  {
6363  return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3A);
6364  } // decode_OPU_VOP3__V_BFREV_B32
6365 
6366  GPUStaticInst*
6368  {
6369  return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3A);
6370  } // decode_OPU_VOP3__V_FFBH_U32
6371 
6372  GPUStaticInst*
6374  {
6375  return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3A);
6376  } // decode_OPU_VOP3__V_FFBL_B32
6377 
6378  GPUStaticInst*
6380  {
6381  return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3A);
6382  } // decode_OPU_VOP3__V_FFBH_I32
6383 
6384  GPUStaticInst*
6386  {
6387  return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3A);
6388  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
6389 
6390  GPUStaticInst*
6392  {
6393  return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3A);
6394  } // decode_OPU_VOP3__V_FREXP_MANT_F64
6395 
6396  GPUStaticInst*
6398  {
6399  return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3A);
6400  } // decode_OPU_VOP3__V_FRACT_F64
6401 
6402  GPUStaticInst*
6404  {
6405  return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3A);
6406  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
6407 
6408  GPUStaticInst*
6410  {
6411  return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3A);
6412  } // decode_OPU_VOP3__V_FREXP_MANT_F32
6413 
6414  GPUStaticInst*
6416  {
6417  return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3A);
6418  } // decode_OPU_VOP3__V_CLREXCP
6419 
6420  GPUStaticInst*
6422  {
6423  return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3A);
6424  } // decode_OPU_VOP3__V_CVT_F16_U16
6425 
6426  GPUStaticInst*
6428  {
6429  return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3A);
6430  } // decode_OPU_VOP3__V_CVT_F16_I16
6431 
6432  GPUStaticInst*
6434  {
6435  return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3A);
6436  } // decode_OPU_VOP3__V_CVT_U16_F16
6437 
6438  GPUStaticInst*
6440  {
6441  return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3A);
6442  } // decode_OPU_VOP3__V_CVT_I16_F16
6443 
6444  GPUStaticInst*
6446  {
6447  return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3A);
6448  } // decode_OPU_VOP3__V_RCP_F16
6449 
6450  GPUStaticInst*
6452  {
6453  return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3A);
6454  } // decode_OPU_VOP3__V_SQRT_F16
6455 
6456  GPUStaticInst*
6458  {
6459  return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3A);
6460  } // decode_OPU_VOP3__V_RSQ_F16
6461 
6462  GPUStaticInst*
6464  {
6465  return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3A);
6466  } // decode_OPU_VOP3__V_LOG_F16
6467 
6468  GPUStaticInst*
6470  {
6471  return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3A);
6472  } // decode_OPU_VOP3__V_EXP_F16
6473 
6474  GPUStaticInst*
6476  {
6477  return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3A);
6478  } // decode_OPU_VOP3__V_FREXP_MANT_F16
6479 
6480  GPUStaticInst*
6482  {
6483  return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3A);
6484  } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
6485 
6486  GPUStaticInst*
6488  {
6489  return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3A);
6490  } // decode_OPU_VOP3__V_FLOOR_F16
6491 
6492  GPUStaticInst*
6494  {
6495  return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3A);
6496  } // decode_OPU_VOP3__V_CEIL_F16
6497 
6498  GPUStaticInst*
6500  {
6501  return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3A);
6502  } // decode_OPU_VOP3__V_TRUNC_F16
6503 
6504  GPUStaticInst*
6506  {
6507  return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3A);
6508  } // decode_OPU_VOP3__V_RNDNE_F16
6509 
6510  GPUStaticInst*
6512  {
6513  return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3A);
6514  } // decode_OPU_VOP3__V_FRACT_F16
6515 
6516  GPUStaticInst*
6518  {
6519  return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3A);
6520  } // decode_OPU_VOP3__V_SIN_F16
6521 
6522  GPUStaticInst*
6524  {
6525  return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3A);
6526  } // decode_OPU_VOP3__V_COS_F16
6527 
6528  GPUStaticInst*
6530  {
6531  return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3A);
6532  } // decode_OPU_VOP3__V_EXP_LEGACY_F32
6533 
6534  GPUStaticInst*
6536  {
6537  return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3A);
6538  } // decode_OPU_VOP3__V_LOG_LEGACY_F32
6539 
6540  GPUStaticInst*
6542  {
6543  return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3A);
6544  } // decode_OPU_VOP3__V_MAD_LEGACY_F32
6545 
6546  GPUStaticInst*
6548  {
6549  return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3A);
6550  } // decode_OPU_VOP3__V_MAD_F32
6551 
6552  GPUStaticInst*
6554  {
6555  return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3A);
6556  } // decode_OPU_VOP3__V_MAD_I32_I24
6557 
6558  GPUStaticInst*
6560  {
6561  return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3A);
6562  } // decode_OPU_VOP3__V_MAD_U32_U24
6563 
6564  GPUStaticInst*
6566  {
6567  return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3A);
6568  } // decode_OPU_VOP3__V_CUBEID_F32
6569 
6570  GPUStaticInst*
6572  {
6573  return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3A);
6574  } // decode_OPU_VOP3__V_CUBESC_F32
6575 
6576  GPUStaticInst*
6578  {
6579  return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3A);
6580  } // decode_OPU_VOP3__V_CUBETC_F32
6581 
6582  GPUStaticInst*
6584  {
6585  return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3A);
6586  } // decode_OPU_VOP3__V_CUBEMA_F32
6587 
6588  GPUStaticInst*
6590  {
6591  return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3A);
6592  } // decode_OPU_VOP3__V_BFE_U32
6593 
6594  GPUStaticInst*
6596  {
6597  return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3A);
6598  } // decode_OPU_VOP3__V_BFE_I32
6599 
6600  GPUStaticInst*
6602  {
6603  return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3A);
6604  } // decode_OPU_VOP3__V_BFI_B32
6605 
6606  GPUStaticInst*
6608  {
6609  return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3A);
6610  } // decode_OPU_VOP3__V_FMA_F32
6611 
6612  GPUStaticInst*
6614  {
6615  return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3A);
6616  } // decode_OPU_VOP3__V_FMA_F64
6617 
6618  GPUStaticInst*
6620  {
6621  return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3A);
6622  } // decode_OPU_VOP3__V_LERP_U8
6623 
6624  GPUStaticInst*
6626  {
6627  return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3A);
6628  } // decode_OPU_VOP3__V_ALIGNBIT_B32
6629 
6630  GPUStaticInst*
6632  {
6633  return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3A);
6634  } // decode_OPU_VOP3__V_ALIGNBYTE_B32
6635 
6636  GPUStaticInst*
6638  {
6639  return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3A);
6640  } // decode_OPU_VOP3__V_MIN3_F32
6641 
6642  GPUStaticInst*
6644  {
6645  return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3A);
6646  } // decode_OPU_VOP3__V_MIN3_I32
6647 
6648  GPUStaticInst*
6650  {
6651  return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3A);
6652  } // decode_OPU_VOP3__V_MIN3_U32
6653 
6654  GPUStaticInst*
6656  {
6657  return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3A);
6658  } // decode_OPU_VOP3__V_MAX3_F32
6659 
6660  GPUStaticInst*
6662  {
6663  return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3A);
6664  } // decode_OPU_VOP3__V_MAX3_I32
6665 
6666  GPUStaticInst*
6668  {
6669  return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3A);
6670  } // decode_OPU_VOP3__V_MAX3_U32
6671 
6672  GPUStaticInst*
6674  {
6675  return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3A);
6676  } // decode_OPU_VOP3__V_MED3_F32
6677 
6678  GPUStaticInst*
6680  {
6681  return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3A);
6682  } // decode_OPU_VOP3__V_MED3_I32
6683 
6684  GPUStaticInst*
6686  {
6687  return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3A);
6688  } // decode_OPU_VOP3__V_MED3_U32
6689 
6690  GPUStaticInst*
6692  {
6693  return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3A);
6694  } // decode_OPU_VOP3__V_SAD_U8
6695 
6696  GPUStaticInst*
6698  {
6699  return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3A);
6700  } // decode_OPU_VOP3__V_SAD_HI_U8
6701 
6702  GPUStaticInst*
6704  {
6705  return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3A);
6706  } // decode_OPU_VOP3__V_SAD_U16
6707 
6708  GPUStaticInst*
6710  {
6711  return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3A);
6712  } // decode_OPU_VOP3__V_SAD_U32
6713 
6714  GPUStaticInst*
6716  {
6717  return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3A);
6718  } // decode_OPU_VOP3__V_CVT_PK_U8_F32
6719 
6720  GPUStaticInst*
6722  {
6723  return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3A);
6724  } // decode_OPU_VOP3__V_DIV_FIXUP_F32
6725 
6726  GPUStaticInst*
6728  {
6729  return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3A);
6730  } // decode_OPU_VOP3__V_DIV_FIXUP_F64
6731 
6732  GPUStaticInst*
6734  {
6735  return new Inst_VOP3__V_DIV_SCALE_F32(&iFmt->iFmt_VOP3B);
6736  } // decode_OPU_VOP3__V_DIV_SCALE_F32
6737 
6738  GPUStaticInst*
6740  {
6741  return new Inst_VOP3__V_DIV_SCALE_F64(&iFmt->iFmt_VOP3B);
6742  } // decode_OPU_VOP3__V_DIV_SCALE_F64
6743 
6744  GPUStaticInst*
6746  {
6747  return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3A);
6748  } // decode_OPU_VOP3__V_DIV_FMAS_F32
6749 
6750  GPUStaticInst*
6752  {
6753  return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3A);
6754  } // decode_OPU_VOP3__V_DIV_FMAS_F64
6755 
6756  GPUStaticInst*
6758  {
6759  return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3A);
6760  } // decode_OPU_VOP3__V_MSAD_U8
6761 
6762  GPUStaticInst*
6764  {
6765  return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6766  } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
6767 
6768  GPUStaticInst*
6770  {
6771  return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6772  } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
6773 
6774  GPUStaticInst*
6776  {
6777  return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3A);
6778  } // decode_OPU_VOP3__V_MQSAD_U32_U8
6779 
6780  GPUStaticInst*
6782  {
6783  return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3B);
6784  } // decode_OPU_VOP3__V_MAD_U64_U32
6785 
6786  GPUStaticInst*
6788  {
6789  return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3B);
6790  } // decode_OPU_VOP3__V_MAD_I64_I32
6791 
6792  GPUStaticInst*
6794  {
6795  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6796  } // decode_OPU_VOP3__V_MAD_LEGACY_F16
6797 
6798  GPUStaticInst*
6800  {
6801  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6802  } // decode_OPU_VOP3__V_MAD_LEGACY_U16
6803 
6804  GPUStaticInst*
6806  {
6807  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6808  } // decode_OPU_VOP3__V_MAD_LEGACY_I16
6809 
6810  GPUStaticInst*
6812  {
6813  return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3A);
6814  } // decode_OPU_VOP3__V_PERM_B32
6815 
6816  GPUStaticInst*
6818  {
6819  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6820  } // decode_OPU_VOP3__V_FMA_LEGACY_F16
6821 
6822  GPUStaticInst*
6824  {
6825  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6826  } // decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
6827 
6828  GPUStaticInst*
6830  {
6831  return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3A);
6832  } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
6833 
6834  GPUStaticInst*
6836  {
6837  return nullptr;
6838  }
6839 
6840  GPUStaticInst*
6842  {
6843  return nullptr;
6844  }
6845 
6846  GPUStaticInst*
6848  {
6849  return nullptr;
6850  }
6851 
6852  GPUStaticInst*
6854  {
6855  return nullptr;
6856  }
6857 
6858  GPUStaticInst*
6860  {
6861  return nullptr;
6862  }
6863 
6864  GPUStaticInst*
6866  {
6867  return nullptr;
6868  }
6869 
6870  GPUStaticInst*
6872  {
6873  return nullptr;
6874  }
6875 
6876  GPUStaticInst*
6878  {
6879  return nullptr;
6880  }
6881 
6882  GPUStaticInst*
6884  {
6885  return nullptr;
6886  }
6887 
6888  GPUStaticInst*
6890  {
6891  return nullptr;
6892  }
6893 
6894  GPUStaticInst*
6896  {
6897  return nullptr;
6898  }
6899 
6900  GPUStaticInst*
6902  {
6903  return nullptr;
6904  }
6905 
6906  GPUStaticInst*
6908  {
6909  return nullptr;
6910  }
6911 
6912  GPUStaticInst*
6914  {
6915  return nullptr;
6916  }
6917 
6918  GPUStaticInst*
6920  {
6921  return nullptr;
6922  }
6923 
6924  GPUStaticInst*
6926  {
6927  return nullptr;
6928  }
6929 
6930  GPUStaticInst*
6932  {
6933  return nullptr;
6934  }
6935 
6936  GPUStaticInst*
6938  {
6939  return nullptr;
6940  }
6941 
6942  GPUStaticInst*
6944  {
6945  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6946  }
6947 
6948  GPUStaticInst*
6950  {
6951  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6952  }
6953 
6954  GPUStaticInst*
6956  {
6957  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6958  }
6959 
6960  GPUStaticInst*
6962  {
6963  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6964  }
6965 
6966  GPUStaticInst*
6968  {
6969  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6970  }
6971 
6972  GPUStaticInst*
6974  {
6975  return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3A);
6976  } // decode_OPU_VOP3__V_INTERP_P1_F32
6977 
6978  GPUStaticInst*
6980  {
6981  return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3A);
6982  } // decode_OPU_VOP3__V_INTERP_P2_F32
6983 
6984  GPUStaticInst*
6986  {
6987  return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3A);
6988  } // decode_OPU_VOP3__V_INTERP_MOV_F32
6989 
6990  GPUStaticInst*
6992  {
6993  return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3A);
6994  } // decode_OPU_VOP3__V_INTERP_P1LL_F16
6995 
6996  GPUStaticInst*
6998  {
6999  return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3A);
7000  } // decode_OPU_VOP3__V_INTERP_P1LV_F16
7001 
7002  GPUStaticInst*
7004  {
7005  return nullptr;
7006  }
7007 
7008  GPUStaticInst*
7010  {
7011  return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3A);
7012  } // decode_OPU_VOP3__V_INTERP_P2_F16
7013 
7014  GPUStaticInst*
7016  {
7017  return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3A);
7018  } // decode_OPU_VOP3__V_ADD_F64
7019 
7020  GPUStaticInst*
7022  {
7023  return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3A);
7024  } // decode_OPU_VOP3__V_MUL_F64
7025 
7026  GPUStaticInst*
7028  {
7029  return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3A);
7030  } // decode_OPU_VOP3__V_MIN_F64
7031 
7032  GPUStaticInst*
7034  {
7035  return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3A);
7036  } // decode_OPU_VOP3__V_MAX_F64
7037 
7038  GPUStaticInst*
7040  {
7041  return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3A);
7042  } // decode_OPU_VOP3__V_LDEXP_F64
7043 
7044  GPUStaticInst*
7046  {
7047  return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3A);
7048  } // decode_OPU_VOP3__V_MUL_LO_U32
7049 
7050  GPUStaticInst*
7052  {
7053  return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3A);
7054  } // decode_OPU_VOP3__V_MUL_HI_U32
7055 
7056  GPUStaticInst*
7058  {
7059  return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3A);
7060  } // decode_OPU_VOP3__V_MUL_HI_I32
7061 
7062  GPUStaticInst*
7064  {
7065  return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3A);
7066  } // decode_OPU_VOP3__V_LDEXP_F32
7067 
7068  GPUStaticInst*
7070  {
7071  return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3A);
7072  } // decode_OPU_VOP3__V_READLANE_B32
7073 
7074  GPUStaticInst*
7076  {
7077  return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3A);
7078  } // decode_OPU_VOP3__V_WRITELANE_B32
7079 
7080  GPUStaticInst*
7082  {
7083  return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3A);
7084  } // decode_OPU_VOP3__V_BCNT_U32_B32
7085 
7086  GPUStaticInst*
7088  {
7089  return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3A);
7090  } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
7091 
7092  GPUStaticInst*
7094  {
7095  return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3A);
7096  } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
7097 
7098  GPUStaticInst*
7100  {
7101  return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3A);
7102  } // decode_OPU_VOP3__V_LSHLREV_B64
7103 
7104  GPUStaticInst*
7106  {
7107  return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3A);
7108  } // decode_OPU_VOP3__V_LSHRREV_B64
7109 
7110  GPUStaticInst*
7112  {
7113  return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3A);
7114  } // decode_OPU_VOP3__V_ASHRREV_I64
7115 
7116  GPUStaticInst*
7118  {
7119  return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3A);
7120  } // decode_OPU_VOP3__V_TRIG_PREOP_F64
7121 
7122  GPUStaticInst*
7124  {
7125  return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3A);
7126  } // decode_OPU_VOP3__V_BFM_B32
7127 
7128  GPUStaticInst*
7130  {
7131  return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3A);
7132  } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
7133 
7134  GPUStaticInst*
7136  {
7137  return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3A);
7138  } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
7139 
7140  GPUStaticInst*
7142  {
7143  return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3A);
7144  } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
7145 
7146  GPUStaticInst*
7148  {
7149  return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3A);
7150  } // decode_OPU_VOP3__V_CVT_PK_U16_U32
7151 
7152  GPUStaticInst*
7154  {
7155  return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3A);
7156  } // decode_OPU_VOP3__V_CVT_PK_I16_I32
7157 
7158  GPUStaticInst*
7160  {
7161  return nullptr;
7162  }
7163 
7164  GPUStaticInst*
7166  {
7167  return nullptr;
7168  }
7169 
7170  GPUStaticInst*
7172  {
7173  return nullptr;
7174  }
7175 
7176  GPUStaticInst*
7178  {
7179  return nullptr;
7180  }
7181 
7182  GPUStaticInst*
7184  {
7185  return nullptr;
7186  }
7187 
7188  GPUStaticInst*
7190  {
7191  return nullptr;
7192  }
7193 
7194  GPUStaticInst*
7196  {
7197  return nullptr;
7198  }
7199 
7200  GPUStaticInst*
7202  {
7203  return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
7204  } // decode_OP_DS__DS_ADD_U32
7205 
7206  GPUStaticInst*
7208  {
7209  return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
7210  } // decode_OP_DS__DS_SUB_U32
7211 
7212  GPUStaticInst*
7214  {
7215  return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
7216  } // decode_OP_DS__DS_RSUB_U32
7217 
7218  GPUStaticInst*
7220  {
7221  return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
7222  } // decode_OP_DS__DS_INC_U32
7223 
7224  GPUStaticInst*
7226  {
7227  return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
7228  } // decode_OP_DS__DS_DEC_U32
7229 
7230  GPUStaticInst*
7232  {
7233  return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
7234  } // decode_OP_DS__DS_MIN_I32
7235 
7236  GPUStaticInst*
7238  {
7239  return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
7240  } // decode_OP_DS__DS_MAX_I32
7241 
7242  GPUStaticInst*
7244  {
7245  return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
7246  } // decode_OP_DS__DS_MIN_U32
7247 
7248  GPUStaticInst*
7250  {
7251  return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
7252  } // decode_OP_DS__DS_MAX_U32
7253 
7254  GPUStaticInst*
7256  {
7257  return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
7258  } // decode_OP_DS__DS_AND_B32
7259 
7260  GPUStaticInst*
7262  {
7263  return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
7264  } // decode_OP_DS__DS_OR_B32
7265 
7266  GPUStaticInst*
7268  {
7269  return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
7270  } // decode_OP_DS__DS_XOR_B32
7271 
7272  GPUStaticInst*
7274  {
7275  return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
7276  } // decode_OP_DS__DS_MSKOR_B32
7277 
7278  GPUStaticInst*
7280  {
7281  return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
7282  } // decode_OP_DS__DS_WRITE_B32
7283 
7284  GPUStaticInst*
7286  {
7287  return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
7288  } // decode_OP_DS__DS_WRITE2_B32
7289 
7290  GPUStaticInst*
7292  {
7293  return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
7294  } // decode_OP_DS__DS_WRITE2ST64_B32
7295 
7296  GPUStaticInst*
7298  {
7299  return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
7300  } // decode_OP_DS__DS_CMPST_B32
7301 
7302  GPUStaticInst*
7304  {
7305  return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
7306  } // decode_OP_DS__DS_CMPST_F32
7307 
7308  GPUStaticInst*
7310  {
7311  return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
7312  } // decode_OP_DS__DS_MIN_F32
7313 
7314  GPUStaticInst*
7316  {
7317  return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
7318  } // decode_OP_DS__DS_MAX_F32
7319 
7320  GPUStaticInst*
7322  {
7323  return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
7324  } // decode_OP_DS__DS_NOP
7325 
7326  GPUStaticInst*
7328  {
7329  return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
7330  } // decode_OP_DS__DS_ADD_F32
7331 
7332  GPUStaticInst*
7334  {
7335  return nullptr;
7336  }
7337 
7338  GPUStaticInst*
7340  {
7341  return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
7342  } // decode_OP_DS__DS_WRITE_B8
7343 
7344  GPUStaticInst*
7346  {
7347  return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
7348  } // decode_OP_DS__DS_WRITE_B16
7349 
7350  GPUStaticInst*
7352  {
7353  return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
7354  } // decode_OP_DS__DS_ADD_RTN_U32
7355 
7356  GPUStaticInst*
7358  {
7359  return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
7360  } // decode_OP_DS__DS_SUB_RTN_U32
7361 
7362  GPUStaticInst*
7364  {
7365  return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
7366  } // decode_OP_DS__DS_RSUB_RTN_U32
7367 
7368  GPUStaticInst*
7370  {
7371  return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
7372  } // decode_OP_DS__DS_INC_RTN_U32
7373 
7374  GPUStaticInst*
7376  {
7377  return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
7378  } // decode_OP_DS__DS_DEC_RTN_U32
7379 
7380  GPUStaticInst*
7382  {
7383  return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
7384  } // decode_OP_DS__DS_MIN_RTN_I32
7385 
7386  GPUStaticInst*
7388  {
7389  return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
7390  } // decode_OP_DS__DS_MAX_RTN_I32
7391 
7392  GPUStaticInst*
7394  {
7395  return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
7396  } // decode_OP_DS__DS_MIN_RTN_U32
7397 
7398  GPUStaticInst*
7400  {
7401  return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
7402  } // decode_OP_DS__DS_MAX_RTN_U32
7403 
7404  GPUStaticInst*
7406  {
7407  return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
7408  } // decode_OP_DS__DS_AND_RTN_B32
7409 
7410  GPUStaticInst*
7412  {
7413  return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
7414  } // decode_OP_DS__DS_OR_RTN_B32
7415 
7416  GPUStaticInst*
7418  {
7419  return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
7420  } // decode_OP_DS__DS_XOR_RTN_B32
7421 
7422  GPUStaticInst*
7424  {
7425  return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
7426  } // decode_OP_DS__DS_MSKOR_RTN_B32
7427 
7428  GPUStaticInst*
7430  {
7431  return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
7432  } // decode_OP_DS__DS_WRXCHG_RTN_B32
7433 
7434  GPUStaticInst*
7436  {
7437  return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
7438  } // decode_OP_DS__DS_WRXCHG2_RTN_B32
7439 
7440  GPUStaticInst*
7442  {
7443  return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
7444  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
7445 
7446  GPUStaticInst*
7448  {
7449  return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
7450  } // decode_OP_DS__DS_CMPST_RTN_B32
7451 
7452  GPUStaticInst*
7454  {
7455  return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
7456  } // decode_OP_DS__DS_CMPST_RTN_F32
7457 
7458  GPUStaticInst*
7460  {
7461  return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
7462  } // decode_OP_DS__DS_MIN_RTN_F32
7463 
7464  GPUStaticInst*
7466  {
7467  return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
7468  } // decode_OP_DS__DS_MAX_RTN_F32
7469 
7470  GPUStaticInst*
7472  {
7473  return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
7474  } // decode_OP_DS__DS_WRAP_RTN_B32
7475 
7476  GPUStaticInst*
7478  {
7479  return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
7480  } // decode_OP_DS__DS_ADD_RTN_F32
7481 
7482  GPUStaticInst*
7484  {
7485  return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
7486  } // decode_OP_DS__DS_READ_B32
7487 
7488  GPUStaticInst*
7490  {
7491  return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
7492  } // decode_OP_DS__DS_READ2_B32
7493 
7494  GPUStaticInst*
7496  {
7497  return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
7498  } // decode_OP_DS__DS_READ2ST64_B32
7499 
7500  GPUStaticInst*
7502  {
7503  return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
7504  } // decode_OP_DS__DS_READ_I8
7505 
7506  GPUStaticInst*
7508  {
7509  return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
7510  } // decode_OP_DS__DS_READ_U8
7511 
7512  GPUStaticInst*
7514  {
7515  return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
7516  } // decode_OP_DS__DS_READ_I16
7517 
7518  GPUStaticInst*
7520  {
7521  return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
7522  } // decode_OP_DS__DS_READ_U16
7523 
7524  GPUStaticInst*
7526  {
7527  return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
7528  } // decode_OP_DS__DS_SWIZZLE_B32
7529 
7530  GPUStaticInst*
7532  {
7533  return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
7534  } // decode_OP_DS__DS_PERMUTE_B32
7535 
7536  GPUStaticInst*
7538  {
7539  return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
7540  } // decode_OP_DS__DS_BPERMUTE_B32
7541 
7542  GPUStaticInst*
7544  {
7545  return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
7546  } // decode_OP_DS__DS_ADD_U64
7547 
7548  GPUStaticInst*
7550  {
7551  return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
7552  } // decode_OP_DS__DS_SUB_U64
7553 
7554  GPUStaticInst*
7556  {
7557  return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
7558  } // decode_OP_DS__DS_RSUB_U64
7559 
7560  GPUStaticInst*
7562  {
7563  return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
7564  } // decode_OP_DS__DS_INC_U64
7565 
7566  GPUStaticInst*
7568  {
7569  return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
7570  } // decode_OP_DS__DS_DEC_U64
7571 
7572  GPUStaticInst*
7574  {
7575  return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
7576  } // decode_OP_DS__DS_MIN_I64
7577 
7578  GPUStaticInst*
7580  {
7581  return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
7582  } // decode_OP_DS__DS_MAX_I64
7583 
7584  GPUStaticInst*
7586  {
7587  return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
7588  } // decode_OP_DS__DS_MIN_U64
7589 
7590  GPUStaticInst*
7592  {
7593  return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
7594  } // decode_OP_DS__DS_MAX_U64
7595 
7596  GPUStaticInst*
7598  {
7599  return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
7600  } // decode_OP_DS__DS_AND_B64
7601 
7602  GPUStaticInst*
7604  {
7605  return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
7606  } // decode_OP_DS__DS_OR_B64
7607 
7608  GPUStaticInst*
7610  {
7611  return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
7612  } // decode_OP_DS__DS_XOR_B64
7613 
7614  GPUStaticInst*
7616  {
7617  return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
7618  } // decode_OP_DS__DS_MSKOR_B64
7619 
7620  GPUStaticInst*
7622  {
7623  return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
7624  } // decode_OP_DS__DS_WRITE_B64
7625 
7626  GPUStaticInst*
7628  {
7629  return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
7630  } // decode_OP_DS__DS_WRITE2_B64
7631 
7632  GPUStaticInst*
7634  {
7635  return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
7636  } // decode_OP_DS__DS_WRITE2ST64_B64
7637 
7638  GPUStaticInst*
7640  {
7641  return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
7642  } // decode_OP_DS__DS_CMPST_B64
7643 
7644  GPUStaticInst*
7646  {
7647  return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
7648  } // decode_OP_DS__DS_CMPST_F64
7649 
7650  GPUStaticInst*
7652  {
7653  return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
7654  } // decode_OP_DS__DS_MIN_F64
7655 
7656  GPUStaticInst*
7658  {
7659  return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
7660  } // decode_OP_DS__DS_MAX_F64
7661 
7662  GPUStaticInst*
7664  {
7665  return nullptr;
7666  }
7667 
7668  GPUStaticInst*
7670  {
7671  return nullptr;
7672  }
7673 
7674  GPUStaticInst*
7676  {
7677  return nullptr;
7678  }
7679 
7680  GPUStaticInst*
7682  {
7683  return nullptr;
7684  }
7685 
7686  GPUStaticInst*
7688  {
7689  return nullptr;
7690  }
7691 
7692  GPUStaticInst*
7694  {
7695  return nullptr;
7696  }
7697 
7698  GPUStaticInst*
7700  {
7701  return nullptr;
7702  }
7703 
7704  GPUStaticInst*
7706  {
7707  return nullptr;
7708  }
7709 
7710  GPUStaticInst*
7712  {
7713  return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
7714  } // decode_OP_DS__DS_ADD_RTN_U64
7715 
7716  GPUStaticInst*
7718  {
7719  return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
7720  } // decode_OP_DS__DS_SUB_RTN_U64
7721 
7722  GPUStaticInst*
7724  {
7725  return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
7726  } // decode_OP_DS__DS_RSUB_RTN_U64
7727 
7728  GPUStaticInst*
7730  {
7731  return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
7732  } // decode_OP_DS__DS_INC_RTN_U64
7733 
7734  GPUStaticInst*
7736  {
7737  return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
7738  } // decode_OP_DS__DS_DEC_RTN_U64
7739 
7740  GPUStaticInst*
7742  {
7743  return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
7744  } // decode_OP_DS__DS_MIN_RTN_I64
7745 
7746  GPUStaticInst*
7748  {
7749  return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
7750  } // decode_OP_DS__DS_MAX_RTN_I64
7751 
7752  GPUStaticInst*
7754  {
7755  return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
7756  } // decode_OP_DS__DS_MIN_RTN_U64
7757 
7758  GPUStaticInst*
7760  {
7761  return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
7762  } // decode_OP_DS__DS_MAX_RTN_U64
7763 
7764  GPUStaticInst*
7766  {
7767  return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
7768  } // decode_OP_DS__DS_AND_RTN_B64
7769 
7770  GPUStaticInst*
7772  {
7773  return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
7774  } // decode_OP_DS__DS_OR_RTN_B64
7775 
7776  GPUStaticInst*
7778  {
7779  return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
7780  } // decode_OP_DS__DS_XOR_RTN_B64
7781 
7782  GPUStaticInst*
7784  {
7785  return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
7786  } // decode_OP_DS__DS_MSKOR_RTN_B64
7787 
7788  GPUStaticInst*
7790  {
7791  return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
7792  } // decode_OP_DS__DS_WRXCHG_RTN_B64
7793 
7794  GPUStaticInst*
7796  {
7797  return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
7798  } // decode_OP_DS__DS_WRXCHG2_RTN_B64
7799 
7800  GPUStaticInst*
7802  {
7803  return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
7804  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
7805 
7806  GPUStaticInst*
7808  {
7809  return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
7810  } // decode_OP_DS__DS_CMPST_RTN_B64
7811 
7812  GPUStaticInst*
7814  {
7815  return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
7816  } // decode_OP_DS__DS_CMPST_RTN_F64
7817 
7818  GPUStaticInst*
7820  {
7821  return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
7822  } // decode_OP_DS__DS_MIN_RTN_F64
7823 
7824  GPUStaticInst*
7826  {
7827  return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
7828  } // decode_OP_DS__DS_MAX_RTN_F64
7829 
7830  GPUStaticInst*
7832  {
7833  return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
7834  } // decode_OP_DS__DS_READ_B64
7835 
7836  GPUStaticInst*
7838  {
7839  return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
7840  } // decode_OP_DS__DS_READ2_B64
7841 
7842  GPUStaticInst*
7844  {
7845  return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
7846  } // decode_OP_DS__DS_READ2ST64_B64
7847 
7848  GPUStaticInst*
7850  {
7851  return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
7852  } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
7853 
7854  GPUStaticInst*
7856  {
7857  return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
7858  } // decode_OP_DS__DS_ADD_SRC2_U32
7859 
7860  GPUStaticInst*
7862  {
7863  return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
7864  } // decode_OP_DS__DS_SUB_SRC2_U32
7865 
7866  GPUStaticInst*
7868  {
7869  return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
7870  } // decode_OP_DS__DS_RSUB_SRC2_U32
7871 
7872  GPUStaticInst*
7874  {
7875  return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
7876  } // decode_OP_DS__DS_INC_SRC2_U32
7877 
7878  GPUStaticInst*
7880  {
7881  return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
7882  } // decode_OP_DS__DS_DEC_SRC2_U32
7883 
7884  GPUStaticInst*
7886  {
7887  return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
7888  } // decode_OP_DS__DS_MIN_SRC2_I32
7889 
7890  GPUStaticInst*
7892  {
7893  return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
7894  } // decode_OP_DS__DS_MAX_SRC2_I32
7895 
7896  GPUStaticInst*
7898  {
7899  return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
7900  } // decode_OP_DS__DS_MIN_SRC2_U32
7901 
7902  GPUStaticInst*
7904  {
7905  return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
7906  } // decode_OP_DS__DS_MAX_SRC2_U32
7907 
7908  GPUStaticInst*
7910  {
7911  return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
7912  } // decode_OP_DS__DS_AND_SRC2_B32
7913 
7914  GPUStaticInst*
7916  {
7917  return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
7918  } // decode_OP_DS__DS_OR_SRC2_B32
7919 
7920  GPUStaticInst*
7922  {
7923  return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
7924  } // decode_OP_DS__DS_XOR_SRC2_B32
7925 
7926  GPUStaticInst*
7928  {
7929  return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
7930  } // decode_OP_DS__DS_WRITE_SRC2_B32
7931 
7932  GPUStaticInst*
7934  {
7935  return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
7936  } // decode_OP_DS__DS_MIN_SRC2_F32
7937 
7938  GPUStaticInst*
7940  {
7941  return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
7942  } // decode_OP_DS__DS_MAX_SRC2_F32
7943 
7944  GPUStaticInst*
7946  {
7947  return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
7948  } // decode_OP_DS__DS_ADD_SRC2_F32
7949 
7950  GPUStaticInst*
7952  {
7953  return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
7954  } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
7955 
7956  GPUStaticInst*
7958  {
7959  return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
7960  } // decode_OP_DS__DS_GWS_INIT
7961 
7962  GPUStaticInst*
7964  {
7965  return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
7966  } // decode_OP_DS__DS_GWS_SEMA_V
7967 
7968  GPUStaticInst*
7970  {
7971  return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
7972  } // decode_OP_DS__DS_GWS_SEMA_BR
7973 
7974  GPUStaticInst*
7976  {
7977  return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
7978  } // decode_OP_DS__DS_GWS_SEMA_P
7979 
7980  GPUStaticInst*
7982  {
7983  return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
7984  } // decode_OP_DS__DS_GWS_BARRIER
7985 
7986  GPUStaticInst*
7988  {
7989  return nullptr;
7990  }
7991 
7992  GPUStaticInst*
7994  {
7995  return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
7996  } // decode_OP_DS__DS_CONSUME
7997 
7998  GPUStaticInst*
8000  {
8001  return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
8002  } // decode_OP_DS__DS_APPEND
8003 
8004  GPUStaticInst*
8006  {
8007  return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
8008  } // decode_OP_DS__DS_ORDERED_COUNT
8009 
8010  GPUStaticInst*
8012  {
8013  return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
8014  } // decode_OP_DS__DS_ADD_SRC2_U64
8015 
8016  GPUStaticInst*
8018  {
8019  return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
8020  } // decode_OP_DS__DS_SUB_SRC2_U64
8021 
8022  GPUStaticInst*
8024  {
8025  return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
8026  } // decode_OP_DS__DS_RSUB_SRC2_U64
8027 
8028  GPUStaticInst*
8030  {
8031  return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
8032  } // decode_OP_DS__DS_INC_SRC2_U64
8033 
8034  GPUStaticInst*
8036  {
8037  return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
8038  } // decode_OP_DS__DS_DEC_SRC2_U64
8039 
8040  GPUStaticInst*
8042  {
8043  return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
8044  } // decode_OP_DS__DS_MIN_SRC2_I64
8045 
8046  GPUStaticInst*
8048  {
8049  return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
8050  } // decode_OP_DS__DS_MAX_SRC2_I64
8051 
8052  GPUStaticInst*
8054  {
8055  return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
8056  } // decode_OP_DS__DS_MIN_SRC2_U64
8057 
8058  GPUStaticInst*
8060  {
8061  return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
8062  } // decode_OP_DS__DS_MAX_SRC2_U64
8063 
8064  GPUStaticInst*
8066  {
8067  return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
8068  } // decode_OP_DS__DS_AND_SRC2_B64
8069 
8070  GPUStaticInst*
8072  {
8073  return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
8074  } // decode_OP_DS__DS_OR_SRC2_B64
8075 
8076  GPUStaticInst*
8078  {
8079  return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
8080  } // decode_OP_DS__DS_XOR_SRC2_B64
8081 
8082  GPUStaticInst*
8084  {
8085  return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
8086  } // decode_OP_DS__DS_WRITE_SRC2_B64
8087 
8088  GPUStaticInst*
8090  {
8091  return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
8092  } // decode_OP_DS__DS_MIN_SRC2_F64
8093 
8094  GPUStaticInst*
8096  {
8097  return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
8098  } // decode_OP_DS__DS_MAX_SRC2_F64
8099 
8100  GPUStaticInst*
8102  {
8103  return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
8104  } // decode_OP_DS__DS_WRITE_B96
8105 
8106  GPUStaticInst*
8108  {
8109  return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
8110  } // decode_OP_DS__DS_WRITE_B128
8111 
8112  GPUStaticInst*
8114  {
8115  return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
8116  } // decode_OP_DS__DS_READ_B96
8117 
8118  GPUStaticInst*
8120  {
8121  return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
8122  } // decode_OP_DS__DS_READ_B128
8123 
8124  GPUStaticInst*
8126  {
8127  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8128  } // decode_OP_FLAT__FLAT_LOAD_UBYTE
8129 
8130  GPUStaticInst*
8132  {
8133  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8134  } // decode_OP_FLAT__FLAT_LOAD_SBYTE
8135 
8136  GPUStaticInst*
8138  {
8139  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8140  } // decode_OP_FLAT__FLAT_LOAD_USHORT
8141 
8142  GPUStaticInst*
8144  {
8145  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8146  } // decode_OP_FLAT__FLAT_LOAD_SSHORT
8147 
8148  GPUStaticInst*
8150  {
8151  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8152  } // decode_OP_FLAT__FLAT_LOAD_DWORD
8153 
8154  GPUStaticInst*
8156  {
8157  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8158  } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
8159 
8160  GPUStaticInst*
8162  {
8163  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8164  } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
8165 
8166  GPUStaticInst*
8168  {
8169  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8170  } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
8171 
8172  GPUStaticInst*
8174  {
8175  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8176  } // decode_OP_FLAT__FLAT_STORE_BYTE
8177 
8178  GPUStaticInst*
8180  {
8181  return nullptr;
8182  }
8183 
8184  GPUStaticInst*
8186  {
8187  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8188  } // decode_OP_FLAT__FLAT_STORE_SHORT
8189 
8190  GPUStaticInst*
8192  {
8193  return nullptr;
8194  }
8195 
8196  GPUStaticInst*
8198  {
8199  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8200  } // decode_OP_FLAT__FLAT_STORE_DWORD
8201 
8202  GPUStaticInst*
8204  {
8205  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8206  } // decode_OP_FLAT__FLAT_STORE_DWORDX2
8207 
8208  GPUStaticInst*
8210  {
8211  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8212  } // decode_OP_FLAT__FLAT_STORE_DWORDX3
8213 
8214  GPUStaticInst*
8216  {
8217  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8218  } // decode_OP_FLAT__FLAT_STORE_DWORDX4
8219 
8220  GPUStaticInst*
8222  {
8223  return nullptr;
8224  }
8225 
8226  GPUStaticInst*
8228  {
8229  return nullptr;
8230  }
8231 
8232  GPUStaticInst*
8234  {
8235  return nullptr;
8236  }
8237 
8238  GPUStaticInst*
8240  {
8241  return nullptr;
8242  }
8243 
8244  GPUStaticInst*
8246  {
8247  return nullptr;
8248  }
8249 
8250  GPUStaticInst*
8252  {
8253  return nullptr;
8254  }
8255 
8256  GPUStaticInst*
8258  {
8259  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8260  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
8261 
8262  GPUStaticInst*
8264  {
8265  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8266  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
8267 
8268  GPUStaticInst*
8270  {
8271  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8272  } // decode_OP_FLAT__FLAT_ATOMIC_ADD
8273 
8274  GPUStaticInst*
8276  {
8277  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8278  } // decode_OP_FLAT__FLAT_ATOMIC_SUB
8279 
8280  GPUStaticInst*
8282  {
8283  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8284  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
8285 
8286  GPUStaticInst*
8288  {
8289  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8290  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
8291 
8292  GPUStaticInst*
8294  {
8295  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8296  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
8297 
8298  GPUStaticInst*
8300  {
8301  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8302  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
8303 
8304  GPUStaticInst*
8306  {
8307  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8308  } // decode_OP_FLAT__FLAT_ATOMIC_AND
8309 
8310  GPUStaticInst*
8312  {
8313  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8314  } // decode_OP_FLAT__FLAT_ATOMIC_OR
8315 
8316  GPUStaticInst*
8318  {
8319  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8320  } // decode_OP_FLAT__FLAT_ATOMIC_XOR
8321 
8322  GPUStaticInst*
8324  {
8325  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8326  } // decode_OP_FLAT__FLAT_ATOMIC_INC
8327 
8328  GPUStaticInst*
8330  {
8331  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8332  } // decode_OP_FLAT__FLAT_ATOMIC_DEC
8333 
8334  GPUStaticInst*
8336  {
8337  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8338  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
8339 
8340  GPUStaticInst*
8342  {
8343  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8344  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
8345 
8346  GPUStaticInst*
8348  {
8349  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8350  } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
8351 
8352  GPUStaticInst*
8354  {
8355  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8356  } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
8357 
8358  GPUStaticInst*
8360  {
8361  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8362  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
8363 
8364  GPUStaticInst*
8366  {
8367  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8368  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
8369 
8370  GPUStaticInst*
8372  {
8373  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8374  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
8375 
8376  GPUStaticInst*
8378  {
8379  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8380  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
8381 
8382  GPUStaticInst*
8384  {
8385  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8386  } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
8387 
8388  GPUStaticInst*
8390  {
8391  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8392  } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
8393 
8394  GPUStaticInst*
8396  {
8397  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8398  } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
8399 
8400  GPUStaticInst*
8402  {
8403  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8404  } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
8405 
8406  GPUStaticInst*
8408  {
8409  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8410  } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
8411 
8412  GPUStaticInst*
8414  {
8415  return nullptr;
8416  }
8417 
8418  GPUStaticInst*
8420  {
8421  return nullptr;
8422  }
8423 
8424  GPUStaticInst*
8426  {
8427  return nullptr;
8428  }
8429 
8430  GPUStaticInst*
8432  {
8433  return nullptr;
8434  }
8435 
8436  GPUStaticInst*
8438  {
8439  return nullptr;
8440  }
8441 
8442  GPUStaticInst*
8444  {
8445  return nullptr;
8446  }
8447 
8448  GPUStaticInst*
8450  {
8451  return nullptr;
8452  }
8453 
8454  GPUStaticInst*
8456  {
8457  return nullptr;
8458  }
8459 
8460  GPUStaticInst*
8462  {
8463  return nullptr;
8464  }
8465 
8466  GPUStaticInst*
8468  {
8469  return nullptr;
8470  }
8471 
8472  GPUStaticInst*
8474  {
8475  return nullptr;
8476  }
8477 
8478  GPUStaticInst*
8480  {
8481  return nullptr;
8482  }
8483 
8484  GPUStaticInst*
8486  {
8487  return nullptr;
8488  }
8489 
8490  GPUStaticInst*
8492  {
8493  return nullptr;
8494  }
8495 
8496  GPUStaticInst*
8498  {
8499  return nullptr;
8500  }
8501 
8502  GPUStaticInst*
8504  {
8505  return nullptr;
8506  }
8507 
8508  GPUStaticInst*
8510  {
8511  return nullptr;
8512  }
8513 
8514  GPUStaticInst*
8516  {
8517  return nullptr;
8518  }
8519 
8520  GPUStaticInst*
8522  {
8523  return nullptr;
8524  }
8525 
8526  GPUStaticInst*
8528  {
8529  return nullptr;
8530  }
8531 
8532  GPUStaticInst*
8534  {
8535  return nullptr;
8536  }
8537 
8538  GPUStaticInst*
8540  {
8541  return nullptr;
8542  }
8543 
8544  GPUStaticInst*
8546  {
8547  return nullptr;
8548  }
8549 
8550  GPUStaticInst*
8552  {
8553  return nullptr;
8554  }
8555 
8556  GPUStaticInst*
8558  {
8559  return nullptr;
8560  }
8561 
8562  GPUStaticInst*
8564  {
8565  return nullptr;
8566  }
8567 
8568  GPUStaticInst*
8570  {
8571  return nullptr;
8572  }
8573 
8574  GPUStaticInst*
8576  {
8577  return nullptr;
8578  }
8579 
8580  GPUStaticInst*
8582  {
8583  return nullptr;
8584  }
8585 
8586  GPUStaticInst*
8588  {
8589  return nullptr;
8590  }
8591 
8592  GPUStaticInst*
8594  {
8595  return nullptr;
8596  }
8597 
8598  GPUStaticInst*
8600  {
8601  return nullptr;
8602  }
8603 
8604  GPUStaticInst*
8606  {
8607  return nullptr;
8608  }
8609 
8610  GPUStaticInst*
8612  {
8613  return nullptr;
8614  }
8615 
8616  GPUStaticInst*
8618  {
8619  return nullptr;
8620  }
8621 
8622  GPUStaticInst*
8624  {
8625  return nullptr;
8626  }
8627 
8628  GPUStaticInst*
8630  {
8631  return nullptr;
8632  }
8633 
8634  GPUStaticInst*
8636  {
8637  return nullptr;
8638  }
8639 
8640  GPUStaticInst*
8642  {
8643  return nullptr;
8644  }
8645 
8646  GPUStaticInst*
8648  {
8649  return nullptr;
8650  }
8651 
8652  GPUStaticInst*
8654  {
8655  return nullptr;
8656  }
8657 
8658  GPUStaticInst*
8660  {
8661  return nullptr;
8662  }
8663 
8664  GPUStaticInst*
8666  {
8667  return nullptr;
8668  }
8669 
8670  GPUStaticInst*
8672  {
8673  return nullptr;
8674  }
8675 
8676  GPUStaticInst*
8678  {
8679  return nullptr;
8680  }
8681 
8682  GPUStaticInst*
8684  {
8685  return nullptr;
8686  }
8687 
8688  GPUStaticInst*
8690  {
8691  return nullptr;
8692  }
8693 
8694  GPUStaticInst*
8696  {
8697  return nullptr;
8698  }
8699 
8700  GPUStaticInst*
8702  {
8703  return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
8704  } // decode_OP_MIMG__IMAGE_LOAD
8705 
8706  GPUStaticInst*
8708  {
8709  return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
8710  } // decode_OP_MIMG__IMAGE_LOAD_MIP
8711 
8712  GPUStaticInst*
8714  {
8715  return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
8716  } // decode_OP_MIMG__IMAGE_LOAD_PCK
8717 
8718  GPUStaticInst*
8720  {
8721  return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
8722  } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
8723 
8724  GPUStaticInst*
8726  {
8727  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
8728  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
8729 
8730  GPUStaticInst*
8732  {
8733  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
8734  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
8735 
8736  GPUStaticInst*
8738  {
8739  return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
8740  } // decode_OP_MIMG__IMAGE_STORE
8741 
8742  GPUStaticInst*
8744  {
8745  return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
8746  } // decode_OP_MIMG__IMAGE_STORE_MIP
8747 
8748  GPUStaticInst*
8750  {
8751  return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
8752  } // decode_OP_MIMG__IMAGE_STORE_PCK
8753 
8754  GPUStaticInst*
8756  {
8757  return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
8758  } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
8759 
8760  GPUStaticInst*
8762  {
8763  return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
8764  } // decode_OP_MIMG__IMAGE_GET_RESINFO
8765 
8766  GPUStaticInst*
8768  {
8769  return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
8770  } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
8771 
8772  GPUStaticInst*
8774  {
8775  return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
8776  } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
8777 
8778  GPUStaticInst*
8780  {
8781  return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
8782  } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
8783 
8784  GPUStaticInst*
8786  {
8787  return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
8788  } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
8789 
8790  GPUStaticInst*
8792  {
8793  return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
8794  } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
8795 
8796  GPUStaticInst*
8798  {
8799  return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
8800  } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
8801 
8802  GPUStaticInst*
8804  {
8805  return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
8806  } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
8807 
8808  GPUStaticInst*
8810  {
8811  return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
8812  } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
8813 
8814  GPUStaticInst*
8816  {
8817  return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
8818  } // decode_OP_MIMG__IMAGE_ATOMIC_AND
8819 
8820  GPUStaticInst*
8822  {
8823  return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
8824  } // decode_OP_MIMG__IMAGE_ATOMIC_OR
8825 
8826  GPUStaticInst*
8828  {
8829  return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
8830  } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
8831 
8832  GPUStaticInst*
8834  {
8835  return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
8836  } // decode_OP_MIMG__IMAGE_ATOMIC_INC
8837 
8838  GPUStaticInst*
8840  {
8841  return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
8842  } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
8843 
8844  GPUStaticInst*
8846  {
8847  return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
8848  } // decode_OP_MIMG__IMAGE_SAMPLE
8849 
8850  GPUStaticInst*
8852  {
8853  return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
8854  } // decode_OP_MIMG__IMAGE_SAMPLE_CL
8855 
8856  GPUStaticInst*
8858  {
8859  return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
8860  } // decode_OP_MIMG__IMAGE_SAMPLE_D
8861 
8862  GPUStaticInst*
8864  {
8865  return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
8866  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
8867 
8868  GPUStaticInst*
8870  {
8871  return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
8872  } // decode_OP_MIMG__IMAGE_SAMPLE_L
8873 
8874  GPUStaticInst*
8876  {
8877  return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
8878  } // decode_OP_MIMG__IMAGE_SAMPLE_B
8879 
8880  GPUStaticInst*
8882  {
8883  return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
8884  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
8885 
8886  GPUStaticInst*
8888  {
8889  return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
8890  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
8891 
8892  GPUStaticInst*
8894  {
8895  return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
8896  } // decode_OP_MIMG__IMAGE_SAMPLE_C
8897 
8898  GPUStaticInst*
8900  {
8901  return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
8902  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
8903 
8904  GPUStaticInst*
8906  {
8907  return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
8908  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
8909 
8910  GPUStaticInst*
8912  {
8913  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
8914  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
8915 
8916  GPUStaticInst*
8918  {
8919  return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
8920  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
8921 
8922  GPUStaticInst*
8924  {
8925  return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
8926  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
8927 
8928  GPUStaticInst*
8930  {
8931  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
8932  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
8933 
8934  GPUStaticInst*
8936  {
8937  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
8938  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
8939 
8940  GPUStaticInst*
8942  {
8943  return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
8944  } // decode_OP_MIMG__IMAGE_SAMPLE_O
8945 
8946  GPUStaticInst*
8948  {
8949  return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
8950  } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
8951 
8952  GPUStaticInst*
8954  {
8955  return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
8956  } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
8957 
8958  GPUStaticInst*
8960  {
8961  return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
8962  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
8963 
8964  GPUStaticInst*
8966  {
8967  return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
8968  } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
8969 
8970  GPUStaticInst*
8972  {
8973  return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
8974  } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
8975 
8976  GPUStaticInst*
8978  {
8979  return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
8980  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
8981 
8982  GPUStaticInst*
8984  {
8985  return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
8986  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
8987 
8988  GPUStaticInst*
8990  {
8991  return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
8992  } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
8993 
8994  GPUStaticInst*
8996  {
8997  return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
8998  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
8999 
9000  GPUStaticInst*
9002  {
9003  return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
9004  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
9005 
9006  GPUStaticInst*
9008  {
9009  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
9010  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
9011 
9012  GPUStaticInst*
9014  {
9015  return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
9016  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
9017 
9018  GPUStaticInst*
9020  {
9021  return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
9022  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
9023 
9024  GPUStaticInst*
9026  {
9027  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
9028  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
9029 
9030  GPUStaticInst*
9032  {
9033  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
9034  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
9035 
9036  GPUStaticInst*
9038  {
9039  return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
9040  } // decode_OP_MIMG__IMAGE_GATHER4
9041 
9042  GPUStaticInst*
9044  {
9045  return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
9046  } // decode_OP_MIMG__IMAGE_GATHER4_CL
9047 
9048  GPUStaticInst*
9050  {
9051  return nullptr;
9052  }
9053 
9054  GPUStaticInst*
9056  {
9057  return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
9058  } // decode_OP_MIMG__IMAGE_GATHER4_L
9059 
9060  GPUStaticInst*
9062  {
9063  return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
9064  } // decode_OP_MIMG__IMAGE_GATHER4_B
9065 
9066  GPUStaticInst*
9068  {
9069  return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
9070  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
9071 
9072  GPUStaticInst*
9074  {
9075  return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
9076  } // decode_OP_MIMG__IMAGE_GATHER4_LZ
9077 
9078  GPUStaticInst*
9080  {
9081  return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
9082  } // decode_OP_MIMG__IMAGE_GATHER4_C
9083 
9084  GPUStaticInst*
9086  {
9087  return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
9088  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
9089 
9090  GPUStaticInst*
9092  {
9093  return nullptr;
9094  }
9095 
9096  GPUStaticInst*
9098  {
9099  return nullptr;
9100  }
9101 
9102  GPUStaticInst*
9104  {
9105  return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
9106  } // decode_OP_MIMG__IMAGE_GATHER4_C_L
9107 
9108  GPUStaticInst*
9110  {
9111  return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
9112  } // decode_OP_MIMG__IMAGE_GATHER4_C_B
9113 
9114  GPUStaticInst*
9116  {
9117  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
9118  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
9119 
9120  GPUStaticInst*
9122  {
9123  return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
9124  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
9125 
9126  GPUStaticInst*
9128  {
9129  return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
9130  } // decode_OP_MIMG__IMAGE_GATHER4_O
9131 
9132  GPUStaticInst*
9134  {
9135  return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
9136  } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
9137 
9138  GPUStaticInst*
9140  {
9141  return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
9142  } // decode_OP_MIMG__IMAGE_GATHER4_L_O
9143 
9144  GPUStaticInst*
9146  {
9147  return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
9148  } // decode_OP_MIMG__IMAGE_GATHER4_B_O
9149 
9150  GPUStaticInst*
9152  {
9153  return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
9154  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
9155 
9156  GPUStaticInst*
9158  {
9159  return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
9160  } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
9161 
9162  GPUStaticInst*
9164  {
9165  return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
9166  } // decode_OP_MIMG__IMAGE_GATHER4_C_O
9167 
9168  GPUStaticInst*
9170  {
9171  return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
9172  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
9173 
9174  GPUStaticInst*
9176  {
9177  return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
9178  } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
9179 
9180  GPUStaticInst*
9182  {
9183  return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
9184  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
9185 
9186  GPUStaticInst*
9188  {
9189  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
9190  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
9191 
9192  GPUStaticInst*
9194  {
9195  return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
9196  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
9197 
9198  GPUStaticInst*
9200  {
9201  return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
9202  } // decode_OP_MIMG__IMAGE_GET_LOD
9203 
9204  GPUStaticInst*
9206  {
9207  return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
9208  } // decode_OP_MIMG__IMAGE_SAMPLE_CD
9209 
9210  GPUStaticInst*
9212  {
9213  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
9214  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
9215 
9216  GPUStaticInst*
9218  {
9219  return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
9220  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
9221 
9222  GPUStaticInst*
9224  {
9225  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
9226  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
9227 
9228  GPUStaticInst*
9230  {
9231  return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
9232  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
9233 
9234  GPUStaticInst*
9236  {
9237  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
9238  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
9239 
9240  GPUStaticInst*
9242  {
9243  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
9244  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
9245 
9246  GPUStaticInst*
9248  {
9249  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
9250  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
9251 
9252  GPUStaticInst*
9254  {
9255  return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
9256  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
9257 
9258  GPUStaticInst*
9260  {
9262  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
9263 
9264  GPUStaticInst*
9266  {
9268  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
9269 
9270  GPUStaticInst*
9272  {
9274  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
9275 
9276  GPUStaticInst*
9278  {
9280  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
9281 
9282  GPUStaticInst*
9284  {
9286  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
9287 
9288  GPUStaticInst*
9290  {
9292  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
9293 
9294  GPUStaticInst*
9296  {
9298  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
9299 
9300  GPUStaticInst*
9302  {
9304  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
9305 
9306  GPUStaticInst*
9308  {
9310  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
9311 
9312  GPUStaticInst*
9314  {
9316  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
9317 
9318  GPUStaticInst*
9320  {
9322  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
9323 
9324  GPUStaticInst*
9326  {
9328  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
9329 
9330  GPUStaticInst*
9332  {
9334  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
9335 
9336  GPUStaticInst*
9338  {
9340  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
9341 
9342  GPUStaticInst*
9344  {
9345  return new
9347  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
9348 
9349  GPUStaticInst*
9351  {
9352  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
9353  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
9354 
9355  GPUStaticInst*
9357  {
9358  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
9359  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
9360 
9361  GPUStaticInst*
9363  {
9365  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
9366 
9367  GPUStaticInst*
9369  {
9371  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
9372 
9373  GPUStaticInst*
9375  {
9376  return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
9377  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
9378 
9379  GPUStaticInst*
9381  {
9383  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
9384 
9385  GPUStaticInst*
9387  {
9389  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
9390 
9391  GPUStaticInst*
9393  {
9395  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
9396 
9397  GPUStaticInst*
9399  {
9401  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
9402 
9403  GPUStaticInst*
9405  {
9407  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
9408 
9409  GPUStaticInst*
9411  {
9413  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
9414 
9415  GPUStaticInst*
9417  {
9419  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
9420 
9421  GPUStaticInst*
9423  {
9425  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
9426 
9427  GPUStaticInst*
9429  {
9431  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
9432 
9433  GPUStaticInst*
9435  {
9437  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
9438 
9439  GPUStaticInst*
9441  {
9443  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
9444 
9445  GPUStaticInst*
9447  {
9448  return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
9449  } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
9450 
9451  GPUStaticInst*
9453  {
9454  return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
9455  } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
9456 
9457  GPUStaticInst*
9459  {
9460  return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
9461  } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
9462 
9463  GPUStaticInst*
9465  {
9466  return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
9467  } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
9468 
9469  GPUStaticInst*
9471  {
9472  return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
9473  } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
9474 
9475  GPUStaticInst*
9477  {
9478  return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
9479  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
9480 
9481  GPUStaticInst*
9483  {
9484  return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
9485  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
9486 
9487  GPUStaticInst*
9489  {
9490  return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
9491  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
9492 
9493  GPUStaticInst*
9495  {
9496  return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
9497  } // decode_OP_MUBUF__BUFFER_STORE_BYTE
9498 
9499  GPUStaticInst*
9501  {
9502  return nullptr;
9503  }
9504 
9505  GPUStaticInst*
9507  {
9508  return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
9509  } // decode_OP_MUBUF__BUFFER_STORE_SHORT
9510 
9511  GPUStaticInst*
9513  {
9514  return nullptr;
9515  }
9516 
9517  GPUStaticInst*
9519  {
9520  return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
9521  } // decode_OP_MUBUF__BUFFER_STORE_DWORD
9522 
9523  GPUStaticInst*
9525  {
9526  return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
9527  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
9528 
9529  GPUStaticInst*
9531  {
9532  return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
9533  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
9534 
9535  GPUStaticInst*
9537  {
9538  return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
9539  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
9540 
9541  GPUStaticInst*
9543  {
9545  } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
9546 
9547  GPUStaticInst*
9549  {
9550  return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
9551  } // decode_OP_MUBUF__BUFFER_WBINVL1
9552 
9553  GPUStaticInst*
9555  {
9556  return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
9557  } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
9558 
9559  GPUStaticInst*
9561  {
9562  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
9563  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
9564 
9565  GPUStaticInst*
9567  {
9568  return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
9569  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
9570 
9571  GPUStaticInst*
9573  {
9574  return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
9575  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
9576 
9577  GPUStaticInst*
9579  {
9580  return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
9581  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
9582 
9583  GPUStaticInst*
9585  {
9586  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
9587  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
9588 
9589  GPUStaticInst*
9591  {
9592  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
9593  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
9594 
9595  GPUStaticInst*
9597  {
9598  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
9599  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
9600 
9601  GPUStaticInst*
9603  {
9604  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
9605  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
9606 
9607  GPUStaticInst*
9609  {
9610  return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
9611  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
9612 
9613  GPUStaticInst*
9615  {
9616  return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
9617  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
9618 
9619  GPUStaticInst*
9621  {
9622  return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
9623  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
9624 
9625  GPUStaticInst*
9627  {
9628  return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
9629  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
9630 
9631  GPUStaticInst*
9633  {
9634  return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
9635  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
9636 
9637  GPUStaticInst*
9639  {
9640  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
9641  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
9642 
9643  GPUStaticInst*
9645  {
9647  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
9648 
9649  GPUStaticInst*
9651  {
9652  return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
9653  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
9654 
9655  GPUStaticInst*
9657  {
9658  return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
9659  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
9660 
9661  GPUStaticInst*
9663  {
9664  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
9665  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
9666 
9667  GPUStaticInst*
9669  {
9670  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
9671  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
9672 
9673  GPUStaticInst*
9675  {
9676  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
9677  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
9678 
9679  GPUStaticInst*
9681  {
9682  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
9683  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
9684 
9685  GPUStaticInst*
9687  {
9688  return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
9689  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
9690 
9691  GPUStaticInst*
9693  {
9694  return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
9695  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
9696 
9697  GPUStaticInst*
9699  {
9700  return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
9701  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
9702 
9703  GPUStaticInst*
9705  {
9706  return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
9707  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
9708 
9709  GPUStaticInst*
9711  {
9712  return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
9713  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
9714 
9715  GPUStaticInst*
9717  {
9718  return nullptr;
9719  }
9720 
9721  GPUStaticInst*
9723  {
9724  return nullptr;
9725  }
9726 
9727  GPUStaticInst*
9729  {
9730  return nullptr;
9731  }
9732 
9733  GPUStaticInst*
9735  {
9736  return nullptr;
9737  }
9738 
9739  GPUStaticInst*
9741  {
9742  return nullptr;
9743  }
9744 
9745  GPUStaticInst*
9747  {
9748  return nullptr;
9749  }
9750 
9751  GPUStaticInst*
9753  {
9754  return nullptr;
9755  }
9756 
9757  GPUStaticInst*
9759  {
9760  return nullptr;
9761  }
9762 
9763  GPUStaticInst*
9765  {
9766  return nullptr;
9767  }
9768 
9769  GPUStaticInst*
9771  {
9772  return nullptr;
9773  }
9774 
9775  GPUStaticInst*
9777  {
9778  return nullptr;
9779  }
9780 
9781  GPUStaticInst*
9783  {
9784  return nullptr;
9785  }
9786 
9787  GPUStaticInst*
9789  {
9790  return nullptr;
9791  }
9792 
9793  GPUStaticInst*
9795  {
9796  return nullptr;
9797  }
9798 
9799  GPUStaticInst*
9801  {
9802  return nullptr;
9803  }
9804 
9805  GPUStaticInst*
9807  {
9808  return nullptr;
9809  }
9810 
9811  GPUStaticInst*
9813  {
9814  return nullptr;
9815  }
9816 
9817  GPUStaticInst*
9819  {
9820  return nullptr;
9821  }
9822 
9823  GPUStaticInst*
9825  {
9826  return nullptr;
9827  }
9828 
9829  GPUStaticInst*
9831  {
9832  return nullptr;
9833  }
9834 
9835  GPUStaticInst*
9837  {
9838  return nullptr;
9839  }
9840 
9841  GPUStaticInst*
9843  {
9844  return nullptr;
9845  }
9846 
9847  GPUStaticInst*
9849  {
9850  return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
9851  } // decode_OP_SMEM__S_LOAD_DWORD
9852 
9853  GPUStaticInst*
9855  {
9856  return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
9857  } // decode_OP_SMEM__S_LOAD_DWORDX2
9858 
9859  GPUStaticInst*
9861  {
9862  return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
9863  } // decode_OP_SMEM__S_LOAD_DWORDX4
9864 
9865  GPUStaticInst*
9867  {
9868  return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
9869  } // decode_OP_SMEM__S_LOAD_DWORDX8
9870 
9871  GPUStaticInst*
9873  {
9874  return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
9875  } // decode_OP_SMEM__S_LOAD_DWORDX16
9876 
9877  GPUStaticInst*
9879  {
9880  return nullptr;
9881  }
9882 
9883  GPUStaticInst*
9885  {
9886  return nullptr;
9887  }
9888 
9889  GPUStaticInst*
9891  {
9892  return nullptr;
9893  }
9894 
9895  GPUStaticInst*
9897  {
9898  return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
9899  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
9900 
9901  GPUStaticInst*
9903  {
9904  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
9905  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
9906 
9907  GPUStaticInst*
9909  {
9910  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
9911  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
9912 
9913  GPUStaticInst*
9915  {
9916  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
9917  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
9918 
9919  GPUStaticInst*
9921  {
9922  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
9923  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
9924 
9925  GPUStaticInst*
9927  {
9928  return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
9929  } // decode_OP_SMEM__S_STORE_DWORD
9930 
9931  GPUStaticInst*
9933  {
9934  return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
9935  } // decode_OP_SMEM__S_STORE_DWORDX2
9936 
9937  GPUStaticInst*
9939  {
9940  return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
9941  } // decode_OP_SMEM__S_STORE_DWORDX4
9942 
9943  GPUStaticInst*
9945  {
9946  return nullptr;
9947  }
9948 
9949  GPUStaticInst*
9951  {
9952  return nullptr;
9953  }
9954 
9955  GPUStaticInst*
9957  {
9958  return nullptr;
9959  }
9960 
9961  GPUStaticInst*
9963  {
9964  return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
9965  } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
9966 
9967  GPUStaticInst*
9969  {
9970  return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
9971  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
9972 
9973  GPUStaticInst*
9975  {
9976  return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
9977  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
9978 
9979  GPUStaticInst*
9981  {
9982  return nullptr;
9983  }
9984  GPUStaticInst*
9986  {
9987  return nullptr;
9988  }
9989  GPUStaticInst*
9991  {
9992  return nullptr;
9993  }
9994  GPUStaticInst*
9996  {
9997  return nullptr;
9998  }
9999  GPUStaticInst*
10001  {
10002  return nullptr;
10003  }
10004  GPUStaticInst*
10006  {
10007  return nullptr;
10008  }
10009  GPUStaticInst*
10011  {
10012  return nullptr;
10013  }
10014  GPUStaticInst*
10016  {
10017  return nullptr;
10018  }
10019 
10020  GPUStaticInst*
10022  {
10023  return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
10024  } // decode_OP_SMEM__S_DCACHE_INV
10025 
10026  GPUStaticInst*
10028  {
10029  return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
10030  } // decode_OP_SMEM__S_DCACHE_WB
10031 
10032  GPUStaticInst*
10034  {
10035  return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
10036  } // decode_OP_SMEM__S_DCACHE_INV_VOL
10037 
10038  GPUStaticInst*
10040  {
10041  return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
10042  } // decode_OP_SMEM__S_DCACHE_WB_VOL
10043 
10044  GPUStaticInst*
10046  {
10047  return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
10048  } // decode_OP_SMEM__S_MEMTIME
10049 
10050  GPUStaticInst*
10052  {
10053  return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
10054  } // decode_OP_SMEM__S_MEMREALTIME
10055 
10056  GPUStaticInst*
10058  {
10059  return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
10060  } // decode_OP_SMEM__S_ATC_PROBE
10061 
10062  GPUStaticInst*
10064  {
10065  return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
10066  } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
10067 
10068  GPUStaticInst*
10070  {
10071  return nullptr;
10072  }
10073 
10074  GPUStaticInst*
10076  {
10077  return nullptr;
10078  }
10079 
10080  GPUStaticInst*
10082  {
10083  return nullptr;
10084  }
10085 
10086  GPUStaticInst*
10088  {
10089  return nullptr;
10090  }
10091 
10092  GPUStaticInst*
10094  {
10095  return nullptr;
10096  }
10097 
10098  GPUStaticInst*
10100  {
10101  return nullptr;
10102  }
10103 
10104  GPUStaticInst*
10106  {
10107  return nullptr;
10108  }
10109 
10110  GPUStaticInst*
10112  {
10113  return nullptr;
10114  }
10115 
10116  GPUStaticInst*
10118  {
10119  return nullptr;
10120  }
10121 
10122  GPUStaticInst*
10124  {
10125  return nullptr;
10126  }
10127 
10128  GPUStaticInst*
10130  {
10131  return nullptr;
10132  }
10133 
10134  GPUStaticInst*
10136  {
10137  return nullptr;
10138  }
10139 
10140  GPUStaticInst*
10142  {
10143  return nullptr;
10144  }
10145 
10146  GPUStaticInst*
10148  {
10149  return nullptr;
10150  }
10151 
10152  GPUStaticInst*
10154  {
10155  return nullptr;
10156  }
10157 
10158  GPUStaticInst*
10160  {
10161  return nullptr;
10162  }
10163 
10164  GPUStaticInst*
10166  {
10167  return nullptr;
10168  }
10169 
10170  GPUStaticInst*
10172  {
10173  return nullptr;
10174  }
10175 
10176  GPUStaticInst*
10178  {
10179  return nullptr;
10180  }
10181 
10182  GPUStaticInst*
10184  {
10185  return nullptr;
10186  }
10187 
10188  GPUStaticInst*
10190  {
10191  return nullptr;
10192  }
10193 
10194  GPUStaticInst*
10196  {
10197  return nullptr;
10198  }
10199 
10200  GPUStaticInst*
10202  {
10203  return nullptr;
10204  }
10205 
10206  GPUStaticInst*
10208  {
10209  return nullptr;
10210  }
10211 
10212  GPUStaticInst*
10214  {
10215  return nullptr;
10216  }
10217 
10218  GPUStaticInst*
10220  {
10221  return nullptr;
10222  }
10223 
10224  GPUStaticInst*
10226  {
10227  return nullptr;
10228  }
10229 
10230  GPUStaticInst*
10232  {
10233  return nullptr;
10234  }
10235 
10236  GPUStaticInst*
10238  {
10239  return nullptr;
10240  }
10241 
10242  GPUStaticInst*
10244  {
10245  return nullptr;
10246  }
10247 
10248  GPUStaticInst*
10250  {
10251  return nullptr;
10252  }
10253 
10254  GPUStaticInst*
10256  {
10257  return nullptr;
10258  }
10259 
10260  GPUStaticInst*
10262  {
10263  return nullptr;
10264  }
10265 
10266  GPUStaticInst*
10268  {
10269  return nullptr;
10270  }
10271 
10272  GPUStaticInst*
10274  {
10275  return nullptr;
10276  }
10277 
10278  GPUStaticInst*
10280  {
10281  return nullptr;
10282  }
10283 
10284  GPUStaticInst*
10286  {
10287  return nullptr;
10288  }
10289 
10290  GPUStaticInst*
10292  {
10293  return nullptr;
10294  }
10295 
10296  GPUStaticInst*
10298  {
10299  return nullptr;
10300  }
10301 
10302  GPUStaticInst*
10304  {
10305  return nullptr;
10306  }
10307 
10308  GPUStaticInst*
10310  {
10311  return nullptr;
10312  }
10313 
10314  GPUStaticInst*
10316  {
10317  return nullptr;
10318  }
10319 
10320  GPUStaticInst*
10322  {
10323  return nullptr;
10324  }
10325 
10326  GPUStaticInst*
10328  {
10329  return nullptr;
10330  }
10331 
10332  GPUStaticInst*
10334  {
10335  return nullptr;
10336  }
10337 
10338  GPUStaticInst*
10340  {
10341  return nullptr;
10342  }
10343 
10344  GPUStaticInst*
10346  {
10347  return nullptr;
10348  }
10349 
10350  GPUStaticInst*
10352  {
10353  return nullptr;
10354  }
10355 
10356  GPUStaticInst*
10358  {
10359  return nullptr;
10360  }
10361 
10362  GPUStaticInst*
10364  {
10365  return nullptr;
10366  }
10367 
10368  GPUStaticInst*
10370  {
10371  return nullptr;
10372  }
10373 
10374  GPUStaticInst*
10376  {
10377  return nullptr;
10378  }
10379 
10380  GPUStaticInst*
10382  {
10383  return nullptr;
10384  }
10385 
10386  GPUStaticInst*
10388  {
10389  return nullptr;
10390  }
10391 
10392  GPUStaticInst*
10394  {
10395  return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
10396  } // decode_OP_SOP1__S_MOV_B32
10397 
10398  GPUStaticInst*
10400  {
10401  return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
10402  } // decode_OP_SOP1__S_MOV_B64
10403 
10404  GPUStaticInst*
10406  {
10407  return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
10408  } // decode_OP_SOP1__S_CMOV_B32
10409 
10410  GPUStaticInst*
10412  {
10413  return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
10414  } // decode_OP_SOP1__S_CMOV_B64
10415 
10416  GPUStaticInst*
10418  {
10419  return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
10420  } // decode_OP_SOP1__S_NOT_B32
10421 
10422  GPUStaticInst*
10424  {
10425  return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
10426  } // decode_OP_SOP1__S_NOT_B64
10427 
10428  GPUStaticInst*
10430  {
10431  return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
10432  } // decode_OP_SOP1__S_WQM_B32
10433 
10434  GPUStaticInst*
10436  {
10437  return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
10438  } // decode_OP_SOP1__S_WQM_B64
10439 
10440  GPUStaticInst*
10442  {
10443  return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
10444  } // decode_OP_SOP1__S_BREV_B32
10445 
10446  GPUStaticInst*
10448  {
10449  return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
10450  } // decode_OP_SOP1__S_BREV_B64
10451 
10452  GPUStaticInst*
10454  {
10455  return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
10456  } // decode_OP_SOP1__S_BCNT0_I32_B32
10457 
10458  GPUStaticInst*
10460  {
10461  return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
10462  } // decode_OP_SOP1__S_BCNT0_I32_B64
10463 
10464  GPUStaticInst*
10466  {
10467  return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
10468  } // decode_OP_SOP1__S_BCNT1_I32_B32
10469 
10470  GPUStaticInst*
10472  {
10473  return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
10474  } // decode_OP_SOP1__S_BCNT1_I32_B64
10475 
10476  GPUStaticInst*
10478  {
10479  return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
10480  } // decode_OP_SOP1__S_FF0_I32_B32
10481 
10482  GPUStaticInst*
10484  {
10485  return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
10486  } // decode_OP_SOP1__S_FF0_I32_B64
10487 
10488  GPUStaticInst*
10490  {
10491  return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
10492  } // decode_OP_SOP1__S_FF1_I32_B32
10493 
10494  GPUStaticInst*
10496  {
10497  return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
10498  } // decode_OP_SOP1__S_FF1_I32_B64
10499 
10500  GPUStaticInst*
10502  {
10503  return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
10504  } // decode_OP_SOP1__S_FLBIT_I32_B32
10505 
10506  GPUStaticInst*
10508  {
10509  return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
10510  } // decode_OP_SOP1__S_FLBIT_I32_B64
10511 
10512  GPUStaticInst*
10514  {
10515  return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
10516  } // decode_OP_SOP1__S_FLBIT_I32
10517 
10518  GPUStaticInst*
10520  {
10521  return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
10522  } // decode_OP_SOP1__S_FLBIT_I32_I64
10523 
10524  GPUStaticInst*
10526  {
10527  return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
10528  } // decode_OP_SOP1__S_SEXT_I32_I8
10529 
10530  GPUStaticInst*
10532  {
10533  return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
10534  } // decode_OP_SOP1__S_SEXT_I32_I16
10535 
10536  GPUStaticInst*
10538  {
10539  return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
10540  } // decode_OP_SOP1__S_BITSET0_B32
10541 
10542  GPUStaticInst*
10544  {
10545  return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
10546  } // decode_OP_SOP1__S_BITSET0_B64
10547 
10548  GPUStaticInst*
10550  {
10551  return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
10552  } // decode_OP_SOP1__S_BITSET1_B32
10553 
10554  GPUStaticInst*
10556  {
10557  return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
10558  } // decode_OP_SOP1__S_BITSET1_B64
10559 
10560  GPUStaticInst*
10562  {
10563  return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
10564  } // decode_OP_SOP1__S_GETPC_B64
10565 
10566  GPUStaticInst*
10568  {
10569  return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
10570  } // decode_OP_SOP1__S_SETPC_B64
10571 
10572  GPUStaticInst*
10574  {
10575  return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
10576  } // decode_OP_SOP1__S_SWAPPC_B64
10577 
10578  GPUStaticInst*
10580  {
10581  return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
10582  } // decode_OP_SOP1__S_RFE_B64
10583 
10584  GPUStaticInst*
10586  {
10587  return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10588  } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
10589 
10590  GPUStaticInst*
10592  {
10593  return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10594  } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
10595 
10596  GPUStaticInst*
10598  {
10599  return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10600  } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
10601 
10602  GPUStaticInst*
10604  {
10605  return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10606  } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
10607 
10608  GPUStaticInst*
10610  {
10611  return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10612  } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
10613 
10614  GPUStaticInst*
10616  {
10617  return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10618  } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
10619 
10620  GPUStaticInst*
10622  {
10623  return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10624  } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
10625 
10626  GPUStaticInst*
10628  {
10629  return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10630  } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
10631 
10632  GPUStaticInst*
10634  {
10635  return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
10636  } // decode_OP_SOP1__S_QUADMASK_B32
10637 
10638  GPUStaticInst*
10640  {
10641  return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
10642  } // decode_OP_SOP1__S_QUADMASK_B64
10643 
10644  GPUStaticInst*
10646  {
10647  return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
10648  } // decode_OP_SOP1__S_MOVRELS_B32
10649 
10650  GPUStaticInst*
10652  {
10653  return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
10654  } // decode_OP_SOP1__S_MOVRELS_B64
10655 
10656  GPUStaticInst*
10658  {
10659  return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
10660  } // decode_OP_SOP1__S_MOVRELD_B32
10661 
10662  GPUStaticInst*
10664  {
10665  return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
10666  } // decode_OP_SOP1__S_MOVRELD_B64
10667 
10668  GPUStaticInst*
10670  {
10671  return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
10672  } // decode_OP_SOP1__S_CBRANCH_JOIN
10673 
10674  GPUStaticInst*
10676  {
10677  return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
10678  } // decode_OP_SOP1__S_ABS_I32
10679 
10680  GPUStaticInst*
10682  {
10683  return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
10684  } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
10685 
10686  GPUStaticInst*
10688  {
10689  return nullptr;
10690  }
10691 
10692  GPUStaticInst*
10694  {
10695  return nullptr;
10696  }
10697 
10698  GPUStaticInst*
10700  {
10701  return nullptr;
10702  }
10703 
10704  GPUStaticInst*
10706  {
10707  return nullptr;
10708  }
10709 
10710  GPUStaticInst*
10712  {
10713  return nullptr;
10714  }
10715 
10716  GPUStaticInst*
10718  {
10719  return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
10720  } // decode_OP_SOPC__S_CMP_EQ_I32
10721 
10722  GPUStaticInst*
10724  {
10725  return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
10726  } // decode_OP_SOPC__S_CMP_LG_I32
10727 
10728  GPUStaticInst*
10730  {
10731  return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
10732  } // decode_OP_SOPC__S_CMP_GT_I32
10733 
10734  GPUStaticInst*
10736  {
10737  return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
10738  } // decode_OP_SOPC__S_CMP_GE_I32
10739 
10740  GPUStaticInst*
10742  {
10743  return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
10744  } // decode_OP_SOPC__S_CMP_LT_I32
10745 
10746  GPUStaticInst*
10748  {
10749  return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
10750  } // decode_OP_SOPC__S_CMP_LE_I32
10751 
10752  GPUStaticInst*
10754  {
10755  return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
10756  } // decode_OP_SOPC__S_CMP_EQ_U32
10757 
10758  GPUStaticInst*
10760  {
10761  return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
10762  } // decode_OP_SOPC__S_CMP_LG_U32
10763 
10764  GPUStaticInst*
10766  {
10767  return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
10768  } // decode_OP_SOPC__S_CMP_GT_U32
10769 
10770  GPUStaticInst*
10772  {
10773  return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
10774  } // decode_OP_SOPC__S_CMP_GE_U32
10775 
10776  GPUStaticInst*
10778  {
10779  return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
10780  } // decode_OP_SOPC__S_CMP_LT_U32
10781 
10782  GPUStaticInst*
10784  {
10785  return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
10786  } // decode_OP_SOPC__S_CMP_LE_U32
10787 
10788  GPUStaticInst*
10790  {
10791  return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
10792  } // decode_OP_SOPC__S_BITCMP0_B32
10793 
10794  GPUStaticInst*
10796  {
10797  return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
10798  } // decode_OP_SOPC__S_BITCMP1_B32
10799 
10800  GPUStaticInst*
10802  {
10803  return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
10804  } // decode_OP_SOPC__S_BITCMP0_B64
10805 
10806  GPUStaticInst*
10808  {
10809  return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
10810  } // decode_OP_SOPC__S_BITCMP1_B64
10811 
10812  GPUStaticInst*
10814  {
10815  return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
10816  } // decode_OP_SOPC__S_SETVSKIP
10817 
10818  GPUStaticInst*
10820  {
10821  return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
10822  } // decode_OP_SOPC__S_SET_GPR_IDX_ON
10823 
10824  GPUStaticInst*
10826  {
10827  return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
10828  } // decode_OP_SOPC__S_CMP_EQ_U64
10829 
10830  GPUStaticInst*
10832  {
10833  return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
10834  } // decode_OP_SOPC__S_CMP_LG_U64
10835 
10836  GPUStaticInst*
10838  {
10839  return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
10840  } // decode_OP_SOPP__S_NOP
10841 
10842  GPUStaticInst*
10844  {
10845  return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
10846  } // decode_OP_SOPP__S_ENDPGM
10847 
10848  GPUStaticInst*
10850  {
10851  return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
10852  } // decode_OP_SOPP__S_BRANCH
10853 
10854  GPUStaticInst*
10856  {
10857  return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
10858  } // decode_OP_SOPP__S_WAKEUP
10859 
10860  GPUStaticInst*
10862  {
10863  return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
10864  } // decode_OP_SOPP__S_CBRANCH_SCC0
10865 
10866  GPUStaticInst*
10868  {
10869  return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
10870  } // decode_OP_SOPP__S_CBRANCH_SCC1
10871 
10872  GPUStaticInst*
10874  {
10875  return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
10876  } // decode_OP_SOPP__S_CBRANCH_VCCZ
10877 
10878  GPUStaticInst*
10880  {
10881  return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
10882  } // decode_OP_SOPP__S_CBRANCH_VCCNZ
10883 
10884  GPUStaticInst*
10886  {
10887  return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
10888  } // decode_OP_SOPP__S_CBRANCH_EXECZ
10889 
10890  GPUStaticInst*
10892  {
10893  return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
10894  } // decode_OP_SOPP__S_CBRANCH_EXECNZ
10895 
10896  GPUStaticInst*
10898  {
10899  return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
10900  } // decode_OP_SOPP__S_BARRIER
10901 
10902  GPUStaticInst*
10904  {
10905  return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
10906  } // decode_OP_SOPP__S_SETKILL
10907 
10908  GPUStaticInst*
10910  {
10911  return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
10912  } // decode_OP_SOPP__S_WAITCNT
10913 
10914  GPUStaticInst*
10916  {
10917  return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
10918  } // decode_OP_SOPP__S_SETHALT
10919 
10920  GPUStaticInst*
10922  {
10923  return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
10924  } // decode_OP_SOPP__S_SLEEP
10925 
10926  GPUStaticInst*
10928  {
10929  return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
10930  } // decode_OP_SOPP__S_SETPRIO
10931 
10932  GPUStaticInst*
10934  {
10935  return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
10936  } // decode_OP_SOPP__S_SENDMSG
10937 
10938  GPUStaticInst*
10940  {
10941  return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
10942  } // decode_OP_SOPP__S_SENDMSGHALT
10943 
10944  GPUStaticInst*
10946  {
10947  return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
10948  } // decode_OP_SOPP__S_TRAP
10949 
10950  GPUStaticInst*
10952  {
10953  return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
10954  } // decode_OP_SOPP__S_ICACHE_INV
10955 
10956  GPUStaticInst*
10958  {
10959  return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
10960  } // decode_OP_SOPP__S_INCPERFLEVEL
10961 
10962  GPUStaticInst*
10964  {
10965  return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
10966  } // decode_OP_SOPP__S_DECPERFLEVEL
10967 
10968  GPUStaticInst*
10970  {
10971  return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
10972  } // decode_OP_SOPP__S_TTRACEDATA
10973 
10974  GPUStaticInst*
10976  {
10977  return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
10978  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
10979 
10980  GPUStaticInst*
10982  {
10983  return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
10984  } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
10985 
10986  GPUStaticInst*
10988  {
10990  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
10991 
10992  GPUStaticInst*
10994  {
10996  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
10997 
10998  GPUStaticInst*
11000  {
11001  return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
11002  } // decode_OP_SOPP__S_ENDPGM_SAVED
11003 
11004  GPUStaticInst*
11006  {
11007  return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
11008  } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
11009 
11010  GPUStaticInst*
11012  {
11013  return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
11014  } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
11015 
11016  GPUStaticInst*
11018  {
11019  return nullptr;
11020  }
11021 
11022  GPUStaticInst*
11024  {
11025  return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
11026  } // decode_OP_VINTRP__V_INTERP_P1_F32
11027 
11028  GPUStaticInst*
11030  {
11031  return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
11032  } // decode_OP_VINTRP__V_INTERP_P2_F32
11033 
11034  GPUStaticInst*
11036  {
11037  return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
11038  } // decode_OP_VINTRP__V_INTERP_MOV_F32
11039 
11040  GPUStaticInst*
11042  {
11043  return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
11044  } // decode_OP_VOP1__V_NOP
11045 
11046  GPUStaticInst*
11048  {
11049  return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
11050  } // decode_OP_VOP1__V_MOV_B32
11051 
11052  GPUStaticInst*
11054  {
11055  return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
11056  } // decode_OP_VOP1__V_READFIRSTLANE_B32
11057 
11058  GPUStaticInst*
11060  {
11061  return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
11062  } // decode_OP_VOP1__V_CVT_I32_F64
11063 
11064  GPUStaticInst*
11066  {
11067  return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
11068  } // decode_OP_VOP1__V_CVT_F64_I32
11069 
11070  GPUStaticInst*
11072  {
11073  return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
11074  } // decode_OP_VOP1__V_CVT_F32_I32
11075 
11076  GPUStaticInst*
11078  {
11079  return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
11080  } // decode_OP_VOP1__V_CVT_F32_U32
11081 
11082  GPUStaticInst*
11084  {
11085  return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
11086  } // decode_OP_VOP1__V_CVT_U32_F32
11087 
11088  GPUStaticInst*
11090  {
11091  return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
11092  } // decode_OP_VOP1__V_CVT_I32_F32
11093 
11094  GPUStaticInst*
11096  {
11097  return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
11098  } // decode_OP_VOP1__V_CVT_F16_F32
11099 
11100  GPUStaticInst*
11102  {
11103  return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
11104  } // decode_OP_VOP1__V_CVT_F32_F16
11105 
11106  GPUStaticInst*
11108  {
11109  return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
11110  } // decode_OP_VOP1__V_CVT_RPI_I32_F32
11111 
11112  GPUStaticInst*
11114  {
11115  return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
11116  } // decode_OP_VOP1__V_CVT_FLR_I32_F32
11117 
11118  GPUStaticInst*
11120  {
11121  return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
11122  } // decode_OP_VOP1__V_CVT_OFF_F32_I4
11123 
11124  GPUStaticInst*
11126  {
11127  return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
11128  } // decode_OP_VOP1__V_CVT_F32_F64
11129 
11130  GPUStaticInst*
11132  {
11133  return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
11134  } // decode_OP_VOP1__V_CVT_F64_F32
11135 
11136  GPUStaticInst*
11138  {
11139  return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
11140  } // decode_OP_VOP1__V_CVT_F32_UBYTE0
11141 
11142  GPUStaticInst*
11144  {
11145  return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
11146  } // decode_OP_VOP1__V_CVT_F32_UBYTE1
11147 
11148  GPUStaticInst*
11150  {
11151  return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
11152  } // decode_OP_VOP1__V_CVT_F32_UBYTE2
11153 
11154  GPUStaticInst*
11156  {
11157  return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
11158  } // decode_OP_VOP1__V_CVT_F32_UBYTE3
11159 
11160  GPUStaticInst*
11162  {
11163  return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
11164  } // decode_OP_VOP1__V_CVT_U32_F64
11165 
11166  GPUStaticInst*
11168  {
11169  return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
11170  } // decode_OP_VOP1__V_CVT_F64_U32
11171 
11172  GPUStaticInst*
11174  {
11175  return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
11176  } // decode_OP_VOP1__V_TRUNC_F64
11177 
11178  GPUStaticInst*
11180  {
11181  return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
11182  } // decode_OP_VOP1__V_CEIL_F64
11183 
11184  GPUStaticInst*
11186  {
11187  return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
11188  } // decode_OP_VOP1__V_RNDNE_F64
11189 
11190  GPUStaticInst*
11192  {
11193  return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
11194  } // decode_OP_VOP1__V_FLOOR_F64
11195 
11196  GPUStaticInst*
11198  {
11199  return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
11200  } // decode_OP_VOP1__V_FRACT_F32
11201 
11202  GPUStaticInst*
11204  {
11205  return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
11206  } // decode_OP_VOP1__V_TRUNC_F32
11207 
11208  GPUStaticInst*
11210  {
11211  return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
11212  } // decode_OP_VOP1__V_CEIL_F32
11213 
11214  GPUStaticInst*
11216  {
11217  return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
11218  } // decode_OP_VOP1__V_RNDNE_F32
11219 
11220  GPUStaticInst*
11222  {
11223  return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
11224  } // decode_OP_VOP1__V_FLOOR_F32
11225 
11226  GPUStaticInst*
11228  {
11229  return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
11230  } // decode_OP_VOP1__V_EXP_F32
11231 
11232  GPUStaticInst*
11234  {
11235  return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
11236  } // decode_OP_VOP1__V_LOG_F32
11237 
11238  GPUStaticInst*
11240  {
11241  return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
11242  } // decode_OP_VOP1__V_RCP_F32
11243 
11244  GPUStaticInst*
11246  {
11247  return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
11248  } // decode_OP_VOP1__V_RCP_IFLAG_F32
11249 
11250  GPUStaticInst*
11252  {
11253  return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
11254  } // decode_OP_VOP1__V_RSQ_F32
11255 
11256  GPUStaticInst*
11258  {
11259  return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
11260  } // decode_OP_VOP1__V_RCP_F64
11261 
11262  GPUStaticInst*
11264  {
11265  return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
11266  } // decode_OP_VOP1__V_RSQ_F64
11267 
11268  GPUStaticInst*
11270  {
11271  return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
11272  } // decode_OP_VOP1__V_SQRT_F32
11273 
11274  GPUStaticInst*
11276  {
11277  return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
11278  } // decode_OP_VOP1__V_SQRT_F64
11279 
11280  GPUStaticInst*
11282  {
11283  return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
11284  } // decode_OP_VOP1__V_SIN_F32
11285 
11286  GPUStaticInst*
11288  {
11289  return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
11290  } // decode_OP_VOP1__V_COS_F32
11291 
11292  GPUStaticInst*
11294  {
11295  return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
11296  } // decode_OP_VOP1__V_NOT_B32
11297 
11298  GPUStaticInst*
11300  {
11301  return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
11302  } // decode_OP_VOP1__V_BFREV_B32
11303 
11304  GPUStaticInst*
11306  {
11307  return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
11308  } // decode_OP_VOP1__V_FFBH_U32
11309 
11310  GPUStaticInst*
11312  {
11313  return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
11314  } // decode_OP_VOP1__V_FFBL_B32
11315 
11316  GPUStaticInst*
11318  {
11319  return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
11320  } // decode_OP_VOP1__V_FFBH_I32
11321 
11322  GPUStaticInst*
11324  {
11325  return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
11326  } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
11327 
11328  GPUStaticInst*
11330  {
11331  return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
11332  } // decode_OP_VOP1__V_FREXP_MANT_F64
11333 
11334  GPUStaticInst*
11336  {
11337  return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
11338  } // decode_OP_VOP1__V_FRACT_F64
11339 
11340  GPUStaticInst*
11342  {
11343  return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
11344  } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
11345 
11346  GPUStaticInst*
11348  {
11349  return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
11350  } // decode_OP_VOP1__V_FREXP_MANT_F32
11351 
11352  GPUStaticInst*
11354  {
11355  return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
11356  } // decode_OP_VOP1__V_CLREXCP
11357 
11358  GPUStaticInst*
11360  {
11361  return nullptr;
11362  }
11363 
11364  GPUStaticInst*
11366  {
11367  return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
11368  } // decode_OP_VOP1__V_CVT_F16_U16
11369 
11370  GPUStaticInst*
11372  {
11373  return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
11374  } // decode_OP_VOP1__V_CVT_F16_I16
11375 
11376  GPUStaticInst*
11378  {
11379  return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
11380  } // decode_OP_VOP1__V_CVT_U16_F16
11381 
11382  GPUStaticInst*
11384  {
11385  return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
11386  } // decode_OP_VOP1__V_CVT_I16_F16
11387 
11388  GPUStaticInst*
11390  {
11391  return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
11392  } // decode_OP_VOP1__V_RCP_F16
11393 
11394  GPUStaticInst*
11396  {
11397  return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
11398  } // decode_OP_VOP1__V_SQRT_F16
11399 
11400  GPUStaticInst*
11402  {
11403  return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
11404  } // decode_OP_VOP1__V_RSQ_F16
11405 
11406  GPUStaticInst*
11408  {
11409  return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
11410  } // decode_OP_VOP1__V_LOG_F16
11411 
11412  GPUStaticInst*
11414  {
11415  return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
11416  } // decode_OP_VOP1__V_EXP_F16
11417 
11418  GPUStaticInst*
11420  {
11421  return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
11422  } // decode_OP_VOP1__V_FREXP_MANT_F16
11423 
11424  GPUStaticInst*
11426  {
11427  return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
11428  } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
11429 
11430  GPUStaticInst*
11432  {
11433  return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
11434  } // decode_OP_VOP1__V_FLOOR_F16
11435 
11436  GPUStaticInst*
11438  {
11439  return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
11440  } // decode_OP_VOP1__V_CEIL_F16
11441 
11442  GPUStaticInst*
11444  {
11445  return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
11446  } // decode_OP_VOP1__V_TRUNC_F16
11447 
11448  GPUStaticInst*
11450  {
11451  return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
11452  } // decode_OP_VOP1__V_RNDNE_F16
11453 
11454  GPUStaticInst*
11456  {
11457  return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
11458  } // decode_OP_VOP1__V_FRACT_F16
11459 
11460  GPUStaticInst*
11462  {
11463  return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
11464  } // decode_OP_VOP1__V_SIN_F16
11465 
11466  GPUStaticInst*
11468  {
11469  return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
11470  } // decode_OP_VOP1__V_COS_F16
11471 
11472  GPUStaticInst*
11474  {
11475  return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
11476  } // decode_OP_VOP1__V_EXP_LEGACY_F32
11477 
11478  GPUStaticInst*
11480  {
11481  return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
11482  } // decode_OP_VOP1__V_LOG_LEGACY_F32
11483 
11484  GPUStaticInst*
11486  {
11487  return nullptr;
11488  }
11489 
11490  GPUStaticInst*
11492  {
11493  return nullptr;
11494  }
11495 
11496  GPUStaticInst*
11498  {
11499  return nullptr;
11500  }
11501 
11502  GPUStaticInst*
11504  {
11505  return nullptr;
11506  }
11507 
11508  GPUStaticInst*
11510  {
11511  return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
11512  } // decode_OP_VOPC__V_CMP_CLASS_F32
11513 
11514  GPUStaticInst*
11516  {
11517  return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
11518  } // decode_OP_VOPC__V_CMPX_CLASS_F32
11519 
11520  GPUStaticInst*
11522  {
11523  return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
11524  } // decode_OP_VOPC__V_CMP_CLASS_F64
11525 
11526  GPUStaticInst*
11528  {
11529  return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
11530  } // decode_OP_VOPC__V_CMPX_CLASS_F64
11531 
11532  GPUStaticInst*
11534  {
11535  return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
11536  } // decode_OP_VOPC__V_CMP_CLASS_F16
11537 
11538  GPUStaticInst*
11540  {
11541  return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
11542  } // decode_OP_VOPC__V_CMPX_CLASS_F16
11543 
11544  GPUStaticInst*
11546  {
11547  return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
11548  } // decode_OP_VOPC__V_CMP_F_F16
11549 
11550  GPUStaticInst*
11552  {
11553  return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
11554  } // decode_OP_VOPC__V_CMP_LT_F16
11555 
11556  GPUStaticInst*
11558  {
11559  return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
11560  } // decode_OP_VOPC__V_CMP_EQ_F16
11561 
11562  GPUStaticInst*
11564  {
11565  return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
11566  } // decode_OP_VOPC__V_CMP_LE_F16
11567 
11568  GPUStaticInst*
11570  {
11571  return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
11572  } // decode_OP_VOPC__V_CMP_GT_F16
11573 
11574  GPUStaticInst*
11576  {
11577  return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
11578  } // decode_OP_VOPC__V_CMP_LG_F16
11579 
11580  GPUStaticInst*
11582  {
11583  return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
11584  } // decode_OP_VOPC__V_CMP_GE_F16
11585 
11586  GPUStaticInst*
11588  {
11589  return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
11590  } // decode_OP_VOPC__V_CMP_O_F16
11591 
11592  GPUStaticInst*
11594  {
11595  return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
11596  } // decode_OP_VOPC__V_CMP_U_F16
11597 
11598  GPUStaticInst*
11600  {
11601  return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
11602  } // decode_OP_VOPC__V_CMP_NGE_F16
11603 
11604  GPUStaticInst*
11606  {
11607  return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
11608  } // decode_OP_VOPC__V_CMP_NLG_F16
11609 
11610  GPUStaticInst*
11612  {
11613  return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
11614  } // decode_OP_VOPC__V_CMP_NGT_F16
11615 
11616  GPUStaticInst*
11618  {
11619  return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
11620  } // decode_OP_VOPC__V_CMP_NLE_F16
11621 
11622  GPUStaticInst*
11624  {
11625  return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
11626  } // decode_OP_VOPC__V_CMP_NEQ_F16
11627 
11628  GPUStaticInst*
11630  {
11631  return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
11632  } // decode_OP_VOPC__V_CMP_NLT_F16
11633 
11634  GPUStaticInst*
11636  {
11637  return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
11638  } // decode_OP_VOPC__V_CMP_TRU_F16
11639 
11640  GPUStaticInst*
11642  {
11643  return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
11644  } // decode_OP_VOPC__V_CMPX_F_F16
11645 
11646  GPUStaticInst*
11648  {
11649  return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
11650  } // decode_OP_VOPC__V_CMPX_LT_F16
11651 
11652  GPUStaticInst*
11654  {
11655  return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
11656  } // decode_OP_VOPC__V_CMPX_EQ_F16
11657 
11658  GPUStaticInst*
11660  {
11661  return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
11662  } // decode_OP_VOPC__V_CMPX_LE_F16
11663 
11664  GPUStaticInst*
11666  {
11667  return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
11668  } // decode_OP_VOPC__V_CMPX_GT_F16
11669 
11670  GPUStaticInst*
11672  {
11673  return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
11674  } // decode_OP_VOPC__V_CMPX_LG_F16
11675 
11676  GPUStaticInst*
11678  {
11679  return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
11680  } // decode_OP_VOPC__V_CMPX_GE_F16
11681 
11682  GPUStaticInst*
11684  {
11685  return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
11686  } // decode_OP_VOPC__V_CMPX_O_F16
11687 
11688  GPUStaticInst*
11690  {
11691  return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
11692  } // decode_OP_VOPC__V_CMPX_U_F16
11693 
11694  GPUStaticInst*
11696  {
11697  return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
11698  } // decode_OP_VOPC__V_CMPX_NGE_F16
11699 
11700  GPUStaticInst*
11702  {
11703  return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
11704  } // decode_OP_VOPC__V_CMPX_NLG_F16
11705 
11706  GPUStaticInst*
11708  {
11709  return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
11710  } // decode_OP_VOPC__V_CMPX_NGT_F16
11711 
11712  GPUStaticInst*
11714  {
11715  return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
11716  } // decode_OP_VOPC__V_CMPX_NLE_F16
11717 
11718  GPUStaticInst*
11720  {
11721  return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
11722  } // decode_OP_VOPC__V_CMPX_NEQ_F16
11723 
11724  GPUStaticInst*
11726  {
11727  return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
11728  } // decode_OP_VOPC__V_CMPX_NLT_F16
11729 
11730  GPUStaticInst*
11732  {
11733  return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
11734  } // decode_OP_VOPC__V_CMPX_TRU_F16
11735 
11736  GPUStaticInst*
11738  {
11739  return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
11740  } // decode_OP_VOPC__V_CMP_F_F32
11741 
11742  GPUStaticInst*
11744  {
11745  return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
11746  } // decode_OP_VOPC__V_CMP_LT_F32
11747 
11748  GPUStaticInst*
11750  {
11751  return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
11752  } // decode_OP_VOPC__V_CMP_EQ_F32
11753 
11754  GPUStaticInst*
11756  {
11757  return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
11758  } // decode_OP_VOPC__V_CMP_LE_F32
11759 
11760  GPUStaticInst*
11762  {
11763  return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
11764  } // decode_OP_VOPC__V_CMP_GT_F32
11765 
11766  GPUStaticInst*
11768  {
11769  return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
11770  } // decode_OP_VOPC__V_CMP_LG_F32
11771 
11772  GPUStaticInst*
11774  {
11775  return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
11776  } // decode_OP_VOPC__V_CMP_GE_F32
11777 
11778  GPUStaticInst*
11780  {
11781  return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
11782  } // decode_OP_VOPC__V_CMP_O_F32
11783 
11784  GPUStaticInst*
11786  {
11787  return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
11788  } // decode_OP_VOPC__V_CMP_U_F32
11789 
11790  GPUStaticInst*
11792  {
11793  return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
11794  } // decode_OP_VOPC__V_CMP_NGE_F32
11795 
11796  GPUStaticInst*
11798  {
11799  return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
11800  } // decode_OP_VOPC__V_CMP_NLG_F32
11801 
11802  GPUStaticInst*
11804  {
11805  return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
11806  } // decode_OP_VOPC__V_CMP_NGT_F32
11807 
11808  GPUStaticInst*
11810  {
11811  return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
11812  } // decode_OP_VOPC__V_CMP_NLE_F32
11813 
11814  GPUStaticInst*
11816  {
11817  return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
11818  } // decode_OP_VOPC__V_CMP_NEQ_F32
11819 
11820  GPUStaticInst*
11822  {
11823  return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
11824  } // decode_OP_VOPC__V_CMP_NLT_F32
11825 
11826  GPUStaticInst*
11828  {
11829  return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
11830  } // decode_OP_VOPC__V_CMP_TRU_F32
11831 
11832  GPUStaticInst*
11834  {
11835  return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
11836  } // decode_OP_VOPC__V_CMPX_F_F32
11837 
11838  GPUStaticInst*
11840  {
11841  return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
11842  } // decode_OP_VOPC__V_CMPX_LT_F32
11843 
11844  GPUStaticInst*
11846  {
11847  return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
11848  } // decode_OP_VOPC__V_CMPX_EQ_F32
11849 
11850  GPUStaticInst*
11852  {
11853  return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
11854  } // decode_OP_VOPC__V_CMPX_LE_F32
11855 
11856  GPUStaticInst*
11858  {
11859  return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
11860  } // decode_OP_VOPC__V_CMPX_GT_F32
11861 
11862  GPUStaticInst*
11864  {
11865  return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
11866  } // decode_OP_VOPC__V_CMPX_LG_F32
11867 
11868  GPUStaticInst*
11870  {
11871  return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
11872  } // decode_OP_VOPC__V_CMPX_GE_F32
11873 
11874  GPUStaticInst*
11876  {
11877  return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
11878  } // decode_OP_VOPC__V_CMPX_O_F32
11879 
11880  GPUStaticInst*
11882  {
11883  return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
11884  } // decode_OP_VOPC__V_CMPX_U_F32
11885 
11886  GPUStaticInst*
11888  {
11889  return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
11890  } // decode_OP_VOPC__V_CMPX_NGE_F32
11891 
11892  GPUStaticInst*
11894  {
11895  return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
11896  } // decode_OP_VOPC__V_CMPX_NLG_F32
11897 
11898  GPUStaticInst*
11900  {
11901  return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
11902  } // decode_OP_VOPC__V_CMPX_NGT_F32
11903 
11904  GPUStaticInst*
11906  {
11907  return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
11908  } // decode_OP_VOPC__V_CMPX_NLE_F32
11909 
11910  GPUStaticInst*
11912  {
11913  return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
11914  } // decode_OP_VOPC__V_CMPX_NEQ_F32
11915 
11916  GPUStaticInst*
11918  {
11919  return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
11920  } // decode_OP_VOPC__V_CMPX_NLT_F32
11921 
11922  GPUStaticInst*
11924  {
11925  return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
11926  } // decode_OP_VOPC__V_CMPX_TRU_F32
11927 
11928  GPUStaticInst*
11930  {
11931  return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
11932  } // decode_OP_VOPC__V_CMP_F_F64
11933 
11934  GPUStaticInst*
11936  {
11937  return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
11938  } // decode_OP_VOPC__V_CMP_LT_F64
11939 
11940  GPUStaticInst*
11942  {
11943  return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
11944  } // decode_OP_VOPC__V_CMP_EQ_F64
11945 
11946  GPUStaticInst*
11948  {
11949  return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
11950  } // decode_OP_VOPC__V_CMP_LE_F64
11951 
11952  GPUStaticInst*
11954  {
11955  return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
11956  } // decode_OP_VOPC__V_CMP_GT_F64
11957 
11958  GPUStaticInst*
11960  {
11961  return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
11962  } // decode_OP_VOPC__V_CMP_LG_F64
11963 
11964  GPUStaticInst*
11966  {
11967  return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
11968  } // decode_OP_VOPC__V_CMP_GE_F64
11969 
11970  GPUStaticInst*
11972  {
11973  return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
11974  } // decode_OP_VOPC__V_CMP_O_F64
11975 
11976  GPUStaticInst*
11978  {
11979  return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
11980  } // decode_OP_VOPC__V_CMP_U_F64
11981 
11982  GPUStaticInst*
11984  {
11985  return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
11986  } // decode_OP_VOPC__V_CMP_NGE_F64
11987 
11988  GPUStaticInst*
11990  {
11991  return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
11992  } // decode_OP_VOPC__V_CMP_NLG_F64
11993 
11994  GPUStaticInst*
11996  {
11997  return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
11998  } // decode_OP_VOPC__V_CMP_NGT_F64
11999 
12000  GPUStaticInst*
12002  {
12003  return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
12004  } // decode_OP_VOPC__V_CMP_NLE_F64
12005 
12006  GPUStaticInst*
12008  {
12009  return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
12010  } // decode_OP_VOPC__V_CMP_NEQ_F64
12011 
12012  GPUStaticInst*
12014  {
12015  return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
12016  } // decode_OP_VOPC__V_CMP_NLT_F64
12017 
12018  GPUStaticInst*
12020  {
12021  return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
12022  } // decode_OP_VOPC__V_CMP_TRU_F64
12023 
12024  GPUStaticInst*
12026  {
12027  return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
12028  } // decode_OP_VOPC__V_CMPX_F_F64
12029 
12030  GPUStaticInst*
12032  {
12033  return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
12034  } // decode_OP_VOPC__V_CMPX_LT_F64
12035 
12036  GPUStaticInst*
12038  {
12039  return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
12040  } // decode_OP_VOPC__V_CMPX_EQ_F64
12041 
12042  GPUStaticInst*
12044  {
12045  return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
12046  } // decode_OP_VOPC__V_CMPX_LE_F64
12047 
12048  GPUStaticInst*
12050  {
12051  return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
12052  } // decode_OP_VOPC__V_CMPX_GT_F64
12053 
12054  GPUStaticInst*
12056  {
12057  return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
12058  } // decode_OP_VOPC__V_CMPX_LG_F64
12059 
12060  GPUStaticInst*
12062  {
12063  return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
12064  } // decode_OP_VOPC__V_CMPX_GE_F64
12065 
12066  GPUStaticInst*
12068  {
12069  return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
12070  } // decode_OP_VOPC__V_CMPX_O_F64
12071 
12072  GPUStaticInst*
12074  {
12075  return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
12076  } // decode_OP_VOPC__V_CMPX_U_F64
12077 
12078  GPUStaticInst*
12080  {
12081  return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
12082  } // decode_OP_VOPC__V_CMPX_NGE_F64
12083 
12084  GPUStaticInst*
12086  {
12087  return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
12088  } // decode_OP_VOPC__V_CMPX_NLG_F64
12089 
12090  GPUStaticInst*
12092  {
12093  return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
12094  } // decode_OP_VOPC__V_CMPX_NGT_F64
12095 
12096  GPUStaticInst*
12098  {
12099  return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
12100  } // decode_OP_VOPC__V_CMPX_NLE_F64
12101 
12102  GPUStaticInst*
12104  {
12105  return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
12106  } // decode_OP_VOPC__V_CMPX_NEQ_F64
12107 
12108  GPUStaticInst*
12110  {
12111  return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
12112  } // decode_OP_VOPC__V_CMPX_NLT_F64
12113 
12114  GPUStaticInst*
12116  {
12117  return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
12118  } // decode_OP_VOPC__V_CMPX_TRU_F64
12119 
12120  GPUStaticInst*
12122  {
12123  return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
12124  } // decode_OP_VOPC__V_CMP_F_I16
12125 
12126  GPUStaticInst*
12128  {
12129  return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
12130  } // decode_OP_VOPC__V_CMP_LT_I16
12131 
12132  GPUStaticInst*
12134  {
12135  return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
12136  } // decode_OP_VOPC__V_CMP_EQ_I16
12137 
12138  GPUStaticInst*
12140  {
12141  return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
12142  } // decode_OP_VOPC__V_CMP_LE_I16
12143 
12144  GPUStaticInst*
12146  {
12147  return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
12148  } // decode_OP_VOPC__V_CMP_GT_I16
12149 
12150  GPUStaticInst*
12152  {
12153  return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
12154  } // decode_OP_VOPC__V_CMP_NE_I16
12155 
12156  GPUStaticInst*
12158  {
12159  return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
12160  } // decode_OP_VOPC__V_CMP_GE_I16
12161 
12162  GPUStaticInst*
12164  {
12165  return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
12166  } // decode_OP_VOPC__V_CMP_T_I16
12167 
12168  GPUStaticInst*
12170  {
12171  return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
12172  } // decode_OP_VOPC__V_CMP_F_U16
12173 
12174  GPUStaticInst*
12176  {
12177  return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
12178  } // decode_OP_VOPC__V_CMP_LT_U16
12179 
12180  GPUStaticInst*
12182  {
12183  return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
12184  } // decode_OP_VOPC__V_CMP_EQ_U16
12185 
12186  GPUStaticInst*
12188  {
12189  return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
12190  } // decode_OP_VOPC__V_CMP_LE_U16
12191 
12192  GPUStaticInst*
12194  {
12195  return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
12196  } // decode_OP_VOPC__V_CMP_GT_U16
12197 
12198  GPUStaticInst*
12200  {
12201  return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
12202  } // decode_OP_VOPC__V_CMP_NE_U16
12203 
12204  GPUStaticInst*
12206  {
12207  return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
12208  } // decode_OP_VOPC__V_CMP_GE_U16
12209 
12210  GPUStaticInst*
12212  {
12213  return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
12214  } // decode_OP_VOPC__V_CMP_T_U16
12215 
12216  GPUStaticInst*
12218  {
12219  return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
12220  } // decode_OP_VOPC__V_CMPX_F_I16
12221 
12222  GPUStaticInst*
12224  {
12225  return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
12226  } // decode_OP_VOPC__V_CMPX_LT_I16
12227 
12228  GPUStaticInst*
12230  {
12231  return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
12232  } // decode_OP_VOPC__V_CMPX_EQ_I16
12233 
12234  GPUStaticInst*
12236  {
12237  return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
12238  } // decode_OP_VOPC__V_CMPX_LE_I16
12239 
12240  GPUStaticInst*
12242  {
12243  return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
12244  } // decode_OP_VOPC__V_CMPX_GT_I16
12245 
12246  GPUStaticInst*
12248  {
12249  return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
12250  } // decode_OP_VOPC__V_CMPX_NE_I16
12251 
12252  GPUStaticInst*
12254  {
12255  return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
12256  } // decode_OP_VOPC__V_CMPX_GE_I16
12257 
12258  GPUStaticInst*
12260  {
12261  return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
12262  } // decode_OP_VOPC__V_CMPX_T_I16
12263 
12264  GPUStaticInst*
12266  {
12267  return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
12268  } // decode_OP_VOPC__V_CMPX_F_U16
12269 
12270  GPUStaticInst*
12272  {
12273  return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
12274  } // decode_OP_VOPC__V_CMPX_LT_U16
12275 
12276  GPUStaticInst*
12278  {
12279  return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
12280  } // decode_OP_VOPC__V_CMPX_EQ_U16
12281 
12282  GPUStaticInst*
12284  {
12285  return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
12286  } // decode_OP_VOPC__V_CMPX_LE_U16
12287 
12288  GPUStaticInst*
12290  {
12291  return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
12292  } // decode_OP_VOPC__V_CMPX_GT_U16
12293 
12294  GPUStaticInst*
12296  {
12297  return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
12298  } // decode_OP_VOPC__V_CMPX_NE_U16
12299 
12300  GPUStaticInst*
12302  {
12303  return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
12304  } // decode_OP_VOPC__V_CMPX_GE_U16
12305 
12306  GPUStaticInst*
12308  {
12309  return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
12310  } // decode_OP_VOPC__V_CMPX_T_U16
12311 
12312  GPUStaticInst*
12314  {
12315  return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
12316  } // decode_OP_VOPC__V_CMP_F_I32
12317 
12318  GPUStaticInst*
12320  {
12321  return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
12322  } // decode_OP_VOPC__V_CMP_LT_I32
12323 
12324  GPUStaticInst*
12326  {
12327  return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
12328  } // decode_OP_VOPC__V_CMP_EQ_I32
12329 
12330  GPUStaticInst*
12332  {
12333  return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
12334  } // decode_OP_VOPC__V_CMP_LE_I32
12335 
12336  GPUStaticInst*
12338  {
12339  return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
12340  } // decode_OP_VOPC__V_CMP_GT_I32
12341 
12342  GPUStaticInst*
12344  {
12345  return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
12346  } // decode_OP_VOPC__V_CMP_NE_I32
12347 
12348  GPUStaticInst*
12350  {
12351  return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
12352  } // decode_OP_VOPC__V_CMP_GE_I32
12353 
12354  GPUStaticInst*
12356  {
12357  return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
12358  } // decode_OP_VOPC__V_CMP_T_I32
12359 
12360  GPUStaticInst*
12362  {
12363  return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
12364  } // decode_OP_VOPC__V_CMP_F_U32
12365 
12366  GPUStaticInst*
12368  {
12369  return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
12370  } // decode_OP_VOPC__V_CMP_LT_U32
12371 
12372  GPUStaticInst*
12374  {
12375  return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
12376  } // decode_OP_VOPC__V_CMP_EQ_U32
12377 
12378  GPUStaticInst*
12380  {
12381  return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
12382  } // decode_OP_VOPC__V_CMP_LE_U32
12383 
12384  GPUStaticInst*
12386  {
12387  return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
12388  } // decode_OP_VOPC__V_CMP_GT_U32
12389 
12390  GPUStaticInst*
12392  {
12393  return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
12394  } // decode_OP_VOPC__V_CMP_NE_U32
12395 
12396  GPUStaticInst*
12398  {
12399  return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
12400  } // decode_OP_VOPC__V_CMP_GE_U32
12401 
12402  GPUStaticInst*
12404  {
12405  return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
12406  } // decode_OP_VOPC__V_CMP_T_U32
12407 
12408  GPUStaticInst*
12410  {
12411  return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
12412  } // decode_OP_VOPC__V_CMPX_F_I32
12413 
12414  GPUStaticInst*
12416  {
12417  return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
12418  } // decode_OP_VOPC__V_CMPX_LT_I32
12419 
12420  GPUStaticInst*
12422  {
12423  return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
12424  } // decode_OP_VOPC__V_CMPX_EQ_I32
12425 
12426  GPUStaticInst*
12428  {
12429  return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
12430  } // decode_OP_VOPC__V_CMPX_LE_I32
12431 
12432  GPUStaticInst*
12434  {
12435  return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
12436  } // decode_OP_VOPC__V_CMPX_GT_I32
12437 
12438  GPUStaticInst*
12440  {
12441  return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
12442  } // decode_OP_VOPC__V_CMPX_NE_I32
12443 
12444  GPUStaticInst*
12446  {
12447  return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
12448  } // decode_OP_VOPC__V_CMPX_GE_I32
12449 
12450  GPUStaticInst*
12452  {
12453  return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
12454  } // decode_OP_VOPC__V_CMPX_T_I32
12455 
12456  GPUStaticInst*
12458  {
12459  return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
12460  } // decode_OP_VOPC__V_CMPX_F_U32
12461 
12462  GPUStaticInst*
12464  {
12465  return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
12466  } // decode_OP_VOPC__V_CMPX_LT_U32
12467 
12468  GPUStaticInst*
12470  {
12471  return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
12472  } // decode_OP_VOPC__V_CMPX_EQ_U32
12473 
12474  GPUStaticInst*
12476  {
12477  return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
12478  } // decode_OP_VOPC__V_CMPX_LE_U32
12479 
12480  GPUStaticInst*
12482  {
12483  return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
12484  } // decode_OP_VOPC__V_CMPX_GT_U32
12485 
12486  GPUStaticInst*
12488  {
12489  return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
12490  } // decode_OP_VOPC__V_CMPX_NE_U32
12491 
12492  GPUStaticInst*
12494  {
12495  return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
12496  } // decode_OP_VOPC__V_CMPX_GE_U32
12497 
12498  GPUStaticInst*
12500  {
12501  return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
12502  } // decode_OP_VOPC__V_CMPX_T_U32
12503 
12504  GPUStaticInst*
12506  {
12507  return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
12508  } // decode_OP_VOPC__V_CMP_F_I64
12509 
12510  GPUStaticInst*
12512  {
12513  return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
12514  } // decode_OP_VOPC__V_CMP_LT_I64
12515 
12516  GPUStaticInst*
12518  {
12519  return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
12520  } // decode_OP_VOPC__V_CMP_EQ_I64
12521 
12522  GPUStaticInst*
12524  {
12525  return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
12526  } // decode_OP_VOPC__V_CMP_LE_I64
12527 
12528  GPUStaticInst*
12530  {
12531  return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
12532  } // decode_OP_VOPC__V_CMP_GT_I64
12533 
12534  GPUStaticInst*
12536  {
12537  return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
12538  } // decode_OP_VOPC__V_CMP_NE_I64
12539 
12540  GPUStaticInst*
12542  {
12543  return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
12544  } // decode_OP_VOPC__V_CMP_GE_I64
12545 
12546  GPUStaticInst*
12548  {
12549  return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
12550  } // decode_OP_VOPC__V_CMP_T_I64
12551 
12552  GPUStaticInst*
12554  {
12555  return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
12556  } // decode_OP_VOPC__V_CMP_F_U64
12557 
12558  GPUStaticInst*
12560  {
12561  return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
12562  } // decode_OP_VOPC__V_CMP_LT_U64
12563 
12564  GPUStaticInst*
12566  {
12567  return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
12568  } // decode_OP_VOPC__V_CMP_EQ_U64
12569 
12570  GPUStaticInst*
12572  {
12573  return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
12574  } // decode_OP_VOPC__V_CMP_LE_U64
12575 
12576  GPUStaticInst*
12578  {
12579  return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
12580  } // decode_OP_VOPC__V_CMP_GT_U64
12581 
12582  GPUStaticInst*
12584  {
12585  return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
12586  } // decode_OP_VOPC__V_CMP_NE_U64
12587 
12588  GPUStaticInst*
12590  {
12591  return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
12592  } // decode_OP_VOPC__V_CMP_GE_U64
12593 
12594  GPUStaticInst*
12596  {
12597  return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
12598  } // decode_OP_VOPC__V_CMP_T_U64
12599 
12600  GPUStaticInst*
12602  {
12603  return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
12604  } // decode_OP_VOPC__V_CMPX_F_I64
12605 
12606  GPUStaticInst*
12608  {
12609  return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
12610  } // decode_OP_VOPC__V_CMPX_LT_I64
12611 
12612  GPUStaticInst*
12614  {
12615  return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
12616  } // decode_OP_VOPC__V_CMPX_EQ_I64
12617 
12618  GPUStaticInst*
12620  {
12621  return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
12622  } // decode_OP_VOPC__V_CMPX_LE_I64
12623 
12624  GPUStaticInst*
12626  {
12627  return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
12628  } // decode_OP_VOPC__V_CMPX_GT_I64
12629 
12630  GPUStaticInst*
12632  {
12633  return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
12634  } // decode_OP_VOPC__V_CMPX_NE_I64
12635 
12636  GPUStaticInst*
12638  {
12639  return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
12640  } // decode_OP_VOPC__V_CMPX_GE_I64
12641 
12642  GPUStaticInst*
12644  {
12645  return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
12646  } // decode_OP_VOPC__V_CMPX_T_I64
12647 
12648  GPUStaticInst*
12650  {
12651  return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
12652  } // decode_OP_VOPC__V_CMPX_F_U64
12653 
12654  GPUStaticInst*
12656  {
12657  return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
12658  } // decode_OP_VOPC__V_CMPX_LT_U64
12659 
12660  GPUStaticInst*
12662  {
12663  return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
12664  } // decode_OP_VOPC__V_CMPX_EQ_U64
12665 
12666  GPUStaticInst*
12668  {
12669  return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
12670  } // decode_OP_VOPC__V_CMPX_LE_U64
12671 
12672  GPUStaticInst*
12674  {
12675  return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
12676  } // decode_OP_VOPC__V_CMPX_GT_U64
12677 
12678  GPUStaticInst*
12680  {
12681  return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
12682  } // decode_OP_VOPC__V_CMPX_NE_U64
12683 
12684  GPUStaticInst*
12686  {
12687  return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
12688  } // decode_OP_VOPC__V_CMPX_GE_U64
12689 
12690  GPUStaticInst*
12692  {
12693  return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
12694  } // decode_OP_VOPC__V_CMPX_T_U64
12695 
12696  GPUStaticInst*
12698  {
12699  return nullptr;
12700  }
12701 
12702  GPUStaticInst*
12704  {
12705  return nullptr;
12706  }
12707 
12708  GPUStaticInst*
12710  {
12711  return nullptr;
12712  }
12713 
12714  GPUStaticInst*
12716  {
12717  return nullptr;
12718  }
12719 
12720  GPUStaticInst*
12722  {
12723  return nullptr;
12724  }
12725 
12726  GPUStaticInst*
12728  {
12729  return nullptr;
12730  }
12731 
12732  GPUStaticInst*
12734  {
12735  return nullptr;
12736  }
12737 
12738  GPUStaticInst*
12740  {
12741  return nullptr;
12742  }
12743 
12744  GPUStaticInst*
12746  {
12747  return nullptr;
12748  }
12749 
12750  GPUStaticInst*
12752  {
12753  return nullptr;
12754  }
12755 
12756  GPUStaticInst*
12758  {
12759  return nullptr;
12760  }
12761 
12762  GPUStaticInst*
12764  {
12765  return nullptr;
12766  }
12767 
12768  GPUStaticInst*
12770  {
12771  return nullptr;
12772  }
12773 
12774  GPUStaticInst*
12776  {
12777  return nullptr;
12778  }
12779 
12780  GPUStaticInst*
12782  {
12783  return nullptr;
12784  }
12785 
12786  GPUStaticInst*
12788  {
12789  return nullptr;
12790  }
12791 
12792  GPUStaticInst*
12794  {
12795  return nullptr;
12796  }
12797 
12798  GPUStaticInst*
12800  {
12801  return nullptr;
12802  }
12803 
12804  GPUStaticInst*
12806  {
12807  return nullptr;
12808  }
12809 
12810  GPUStaticInst*
12812  {
12813  return nullptr;
12814  }
12815 
12816  GPUStaticInst*
12818  {
12819  return nullptr;
12820  }
12821 
12822  GPUStaticInst*
12824  {
12825  return nullptr;
12826  }
12827 
12828  GPUStaticInst*
12830  {
12831  fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
12832 
12833  return nullptr;
12834  }
12835 } // namespace VegaISA
12836 } // namespace gem5
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8209
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:11599
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F16
GPUStaticInst * decode_OPU_VOP3__V_MUL_F16(MachInst)
Definition: decoder.cc:6007
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:42393
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16(MachInst)
Definition: decoder.cc:7675
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst)
Definition: decoder.cc:7795
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64
Definition: instructions.hh:16719
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8347
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8335
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSGHALT
GPUStaticInst * decode_OP_SOPP__S_SENDMSGHALT(MachInst)
Definition: decoder.cc:10939
gem5::VegaISA::Inst_SOP2__S_ADD_U32
Definition: instructions.hh:47
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_I32(MachInst)
Definition: decoder.cc:10747
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:5179
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F16
GPUStaticInst * decode_OPU_VOP3__V_LOG_F16(MachInst)
Definition: decoder.cc:6463
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC1
Definition: instructions.hh:4571
gem5::VegaISA::Inst_VOP3__V_ADD_F64
Definition: instructions.hh:29949
gem5::VegaISA::Decoder::tableSubDecode_OP_MIMG
static IsaDecodeMethod tableSubDecode_OP_MIMG[128]
Definition: gpu_decoder.hh:68
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_LOD
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_LOD(MachInst)
Definition: decoder.cc:9199
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:5365
gem5::VegaISA::Inst_VOP1__V_RNDNE_F64
Definition: instructions.hh:8831
gem5::VegaISA::Inst_VOP1__V_CLREXCP
Definition: instructions.hh:9727
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:5461
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B64
GPUStaticInst * decode_OP_SOP2__S_BFM_B64(MachInst)
Definition: decoder.cc:4387
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:12037
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_B32(MachInst)
Definition: decoder.cc:4603
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32
Definition: instructions.hh:18691
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:5725
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:12349
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:11875
gem5::VegaISA::Inst_VOP3__V_MED3_I32
Definition: instructions.hh:28769
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64
Definition: instructions.hh:16447
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_P
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_P(MachInst)
Definition: decoder.cc:7975
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16
Definition: instructions.hh:11211
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32
Definition: instructions.hh:12401
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D
Definition: instructions.hh:39417
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B32
GPUStaticInst * decode_OP_SOP1__S_WQM_B32(MachInst)
Definition: decoder.cc:10429
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16
Definition: instructions.hh:11109
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:12535
gem5::VegaISA::Inst_SOP2__S_OR_B64
Definition: instructions.hh:557
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U32(MachInst)
Definition: decoder.cc:10759
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U64(MachInst)
Definition: decoder.cc:8023
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:4951
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64
Definition: instructions.hh:16141
gem5::VegaISA::InFmt_VINTRP::OP
unsigned int OP
Definition: gpu_decoder.hh:1782
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst)
Definition: decoder.cc:8971
gem5::VegaISA::Inst_VOP3__V_BFM_B32
Definition: instructions.hh:30561
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_U16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:6421
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
Definition: instructions.hh:37253
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16
Definition: instructions.hh:14475
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B64
GPUStaticInst * decode_OP_SOP1__S_WQM_B64(MachInst)
Definition: decoder.cc:10435
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SBYTE
Definition: instructions.hh:36083
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_B64(MachInst)
Definition: decoder.cc:7615
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:12007
gem5::VegaISA::Inst_VOP3__V_MED3_F32
Definition: instructions.hh:28733
gem5::VegaISA::Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10591
gem5::VegaISA::Inst_VOP3__V_SQRT_F16
Definition: instructions.hh:27461
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:6475
gem5::VegaISA::Inst_DS__DS_OR_RTN_B64
Definition: instructions.hh:33613
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8383
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
Definition: instructions.hh:37325
gem5::VegaISA::Inst_VOP2__V_SUB_U32
Definition: instructions.hh:7967
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9890
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL_O
Definition: instructions.hh:40677
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10597
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F32
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F32(MachInst)
Definition: decoder.cc:6331
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:4633
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8767
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64
Definition: instructions.hh:12877
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:11839
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64
Definition: instructions.hh:2791
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:37841
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U64
Definition: instructions.hh:34941
gem5::VegaISA::Inst_VOP3__V_CLREXCP
Definition: instructions.hh:27273
gem5::VegaISA::Inst_VOP3__V_CEIL_F64
Definition: instructions.hh:26345
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16
Definition: instructions.hh:18113
gem5::VegaISA::Inst_VOP3__V_MUL_LEGACY_F32
Definition: instructions.hh:24099
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_U32(MachInst)
Definition: decoder.cc:7213
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F64
GPUStaticInst * decode_OP_VOP1__V_CEIL_F64(MachInst)
Definition: decoder.cc:11179
gem5::VegaISA::Inst_VINTRP__V_INTERP_P1_F32
Definition: instructions.hh:17127
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U64
GPUStaticInst * decode_OP_SOP2__S_BFE_U64(MachInst)
Definition: decoder.cc:4411
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:5701
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8443
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX
Definition: instructions.hh:42121
gem5::VegaISA::Inst_SOP2__S_MAX_U32
Definition: instructions.hh:353
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64
Definition: instructions.hh:19949
gem5::VegaISA::Inst_DS__DS_GWS_BARRIER
Definition: instructions.hh:34723
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:12241
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:11725
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16
Definition: instructions.hh:21377
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:5563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B64(MachInst)
Definition: decoder.cc:7105
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32
Definition: instructions.hh:15325
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
Definition: instructions.hh:37361
gem5::VegaISA::InFmt_SMEM
Definition: gpu_decoder.hh:1725
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L_O
Definition: instructions.hh:39777
gem5::VegaISA::Inst_SOP2__S_LSHR_B64
Definition: instructions.hh:1101
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64
Definition: instructions.hh:16855
gem5::VegaISA::Inst_VOP3__V_LERP_U8
Definition: instructions.hh:28409
gem5::VegaISA::Inst_DS__DS_CONSUME
Definition: instructions.hh:34755
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:9578
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst)
Definition: decoder.cc:7093
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9476
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B32(MachInst)
Definition: decoder.cc:10477
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9482
gem5::VegaISA::Inst_VOP3__V_MAD_U16
Definition: instructions.hh:29499
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64
Definition: instructions.hh:2855
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F32
Definition: instructions.hh:8255
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B32(MachInst)
Definition: decoder.cc:10465
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK
GPUStaticInst * decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst)
Definition: decoder.cc:4423
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SETPC_B64
GPUStaticInst * decode_OP_SOP1__S_SETPC_B64(MachInst)
Definition: decoder.cc:10567
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT(MachInst)
Definition: decoder.cc:8473
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9434
gem5::VegaISA::Inst_DS__DS_CMPST_B32
Definition: instructions.hh:31287
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:11035
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
Definition: instructions.hh:41217
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:9680
gem5::VegaISA::Decoder::tableSubDecode_OP_SOP1
static IsaDecodeMethod tableSubDecode_OP_SOP1[256]
Definition: gpu_decoder.hh:73
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64
Definition: instructions.hh:17331
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORD(MachInst)
Definition: decoder.cc:8197
gem5::VegaISA::Inst_VOP1__V_SIN_F16
Definition: instructions.hh:10267
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F64
Definition: instructions.hh:8127
gem5::VegaISA::Inst_DS__DS_READ_B96
Definition: instructions.hh:35365
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16
Definition: instructions.hh:14033
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I32
Definition: instructions.hh:31749
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F32(MachInst)
Definition: decoder.cc:4903
gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32
Definition: instructions.hh:32593
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I64
Definition: instructions.hh:30493
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U32
Definition: instructions.hh:34089
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:4819
gem5::VegaISA::Inst_DS__DS_CMPST_F32
Definition: instructions.hh:31319
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16
Definition: instructions.hh:18147
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:9650
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:11125
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:12343
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F64
GPUStaticInst * decode_OPU_VOP3__V_RCP_F64(MachInst)
Definition: decoder.cc:6319
gem5::VegaISA::Inst_VOP3__V_FLOOR_F64
Definition: instructions.hh:26409
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:9812
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B32(MachInst)
Definition: decoder.cc:10657
gem5::VegaISA::Inst_VOP3__V_MAD_I32_I24
Definition: instructions.hh:28013
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F32
Definition: instructions.hh:32191
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL
Definition: instructions.hh:39381
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B64
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B64(MachInst)
Definition: decoder.cc:7843
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B32
GPUStaticInst * decode_OP_DS__DS_AND_B32(MachInst)
Definition: decoder.cc:7255
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:5149
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8503
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MOVK_I32
GPUStaticInst * decode_OP_SOPK__S_MOVK_I32(MachInst)
Definition: decoder.cc:4495
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F32
GPUStaticInst * decode_OPU_VOP3__V_SUB_F32(MachInst)
Definition: decoder.cc:5827
gem5::VegaISA::Inst_DS__DS_READ2ST64_B64
Definition: instructions.hh:34021
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F64
Definition: instructions.hh:25673
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:10147
gem5::VegaISA::Inst_DS__DS_WRITE_B8
Definition: instructions.hh:31477
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32
Definition: instructions.hh:12299
gem5::VegaISA::Decoder::subDecode_OP_SOP1
GPUStaticInst * subDecode_OP_SOP1(MachInst)
Definition: decoder.cc:3746
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F32
Definition: instructions.hh:25801
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_I16_F16(MachInst)
Definition: decoder.cc:7159
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:3895
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9350
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:11791
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B16
Definition: instructions.hh:7627
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2
Definition: instructions.hh:42669
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_P
Definition: instructions.hh:34693
gem5::VegaISA::Inst_VOP3__V_BFI_B32
Definition: instructions.hh:28301
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8227
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:6163
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE
Definition: instructions.hh:41469
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst)
Definition: decoder.cc:11011
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F64
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F64(MachInst)
Definition: decoder.cc:11191
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCZ
Definition: instructions.hh:4601
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F64
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F64(MachInst)
Definition: decoder.cc:11173
gem5::VegaISA::Inst_VOP3__V_RSQ_F16
Definition: instructions.hh:27493
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8353
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:5215
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32
Definition: instructions.hh:15563
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F16
GPUStaticInst * decode_OP_VOP1__V_CEIL_F16(MachInst)
Definition: decoder.cc:11437
gem5::VegaISA::Inst_VOP3__V_RCP_F16
Definition: instructions.hh:27429
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10183
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U32
Definition: instructions.hh:34299
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BARRIER
GPUStaticInst * decode_OP_SOPP__S_BARRIER(MachInst)
Definition: decoder.cc:10897
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I32
GPUStaticInst * decode_OP_VOP2__V_MAX_I32(MachInst)
Definition: decoder.cc:3925
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F32
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F32(MachInst)
Definition: decoder.cc:6265
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_F16(MachInst)
Definition: decoder.cc:12793
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B64(MachInst)
Definition: decoder.cc:10651
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8257
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F64(MachInst)
Definition: decoder.cc:5047
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst)
Definition: decoder.cc:7663
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:12205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U16(MachInst)
Definition: decoder.cc:6949
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U32(MachInst)
Definition: decoder.cc:7903
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_FED_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:6151
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I64(MachInst)
Definition: decoder.cc:12505
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_ADD_U32(MachInst)
Definition: decoder.cc:6907
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:11881
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9277
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10279
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B16
Definition: instructions.hh:7593
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B32
GPUStaticInst * decode_OP_DS__DS_READ2_B32(MachInst)
Definition: decoder.cc:7489
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B64
Definition: instructions.hh:35121
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:11731
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F32
Definition: instructions.hh:9695
gem5::VegaISA::Inst_SOP2__S_CSELECT_B32
Definition: instructions.hh:387
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:11161
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:12391
gem5::VegaISA::Inst_VOP2__V_MADAK_F32
Definition: instructions.hh:6959
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:11683
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9950
gem5::VegaISA::Inst_VOP3__V_ALIGNBYTE_B32
Definition: instructions.hh:28481
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64
Definition: instructions.hh:20119
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64
Definition: instructions.hh:23689
gem5::VegaISA::InstFormat::iFmt_VOP3P
InFmt_VOP3P iFmt_VOP3P
Definition: gpu_decoder.hh:1934
gem5::VegaISA::InFmt_SOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1745
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F64
Definition: instructions.hh:9599
gem5::VegaISA::Inst_SOP2__S_ASHR_I64
Definition: instructions.hh:1169
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR(MachInst)
Definition: decoder.cc:10291
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_F32(MachInst)
Definition: decoder.cc:7309
gem5::VegaISA::Decoder::decode_OP_DS__DS_PERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_PERMUTE_B32(MachInst)
Definition: decoder.cc:7531
gem5::VegaISA::Inst_VOP1__V_RCP_F64
Definition: instructions.hh:9215
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10231
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst)
Definition: decoder.cc:8833
gem5::VegaISA::Inst_VOP1__V_LOG_F16
Definition: instructions.hh:9979
gem5::VegaISA::Inst_SOPC__S_SETVSKIP
Definition: instructions.hh:4293
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX
Definition: instructions.hh:42155
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64
Definition: instructions.hh:22975
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F64
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F64(MachInst)
Definition: decoder.cc:6325
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F64
GPUStaticInst * decode_OP_DS__DS_MAX_F64(MachInst)
Definition: decoder.cc:7657
gem5::VegaISA::Inst_VOP3__V_NOP
Definition: instructions.hh:25613
gem5::VegaISA::Inst_SOP2__S_BFM_B32
Definition: instructions.hh:1203
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I16
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I16(MachInst)
Definition: decoder.cc:10531
gem5::VegaISA::Inst_VOP1__V_CVT_F64_I32
Definition: instructions.hh:8159
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I64
GPUStaticInst * decode_OP_SOP2__S_BFE_I64(MachInst)
Definition: decoder.cc:4417
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8245
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:12115
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I32(MachInst)
Definition: decoder.cc:7387
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst)
Definition: decoder.cc:7135
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8167
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:11101
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:11749
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64
Definition: instructions.hh:19711
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:5191
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_F32(MachInst)
Definition: decoder.cc:6547
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGUSER
Definition: instructions.hh:5145
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F32
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F32(MachInst)
Definition: decoder.cc:6259
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR_X2
Definition: instructions.hh:37469
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst)
Definition: decoder.cc:8311
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:4915
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:6403
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_INC
Definition: instructions.hh:38989
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD
Definition: instructions.hh:36749
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64
Definition: instructions.hh:16889
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:5977
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F64(MachInst)
Definition: decoder.cc:8095
gem5::VegaISA::Inst_VOP1__V_LOG_LEGACY_F32
Definition: instructions.hh:10363
gem5::VegaISA::InFmt_SOPP::OP
unsigned int OP
Definition: gpu_decoder.hh:1774
gem5::VegaISA::Inst_VOP1__V_CVT_F64_F32
Definition: instructions.hh:8543
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORD(MachInst)
Definition: decoder.cc:9848
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst)
Definition: decoder.cc:8851
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B32
GPUStaticInst * decode_OP_SOP2__S_BFM_B32(MachInst)
Definition: decoder.cc:4381
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8431
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_OR_B32(MachInst)
Definition: decoder.cc:6925
gem5::VegaISA::Inst_VOP3__V_CVT_F64_I32
Definition: instructions.hh:25705
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U16(MachInst)
Definition: decoder.cc:5287
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F16
Definition: instructions.hh:8383
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32
Definition: instructions.hh:22295
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32
Definition: instructions.hh:22057
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16
Definition: instructions.hh:11177
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:37917
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64
Definition: instructions.hh:13217
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:12643
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY
Definition: instructions.hh:35619
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:12067
gem5::VegaISA::Decoder::tableSubDecode_OPU_VOP3
static IsaDecodeMethod tableSubDecode_OPU_VOP3[768]
Definition: gpu_decoder.hh:64
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10363
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32
Definition: instructions.hh:15155
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMREALTIME
GPUStaticInst * decode_OP_SMEM__S_MEMREALTIME(MachInst)
Definition: decoder.cc:10051
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9884
gem5::VegaISA::Inst_SOP2__S_AND_B64
Definition: instructions.hh:489
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_U16(MachInst)
Definition: decoder.cc:12769
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3
Definition: instructions.hh:36509
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:12085
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9289
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U64
Definition: instructions.hh:33409
gem5::VegaISA::Inst_VOP3__V_MQSAD_PK_U16_U8
Definition: instructions.hh:29315
gem5::VegaISA::Inst_VOP3__V_CVT_F64_F32
Definition: instructions.hh:26089
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F64(MachInst)
Definition: decoder.cc:5095
gpu_static_inst.hh
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_I16_F32
Definition: instructions.hh:30595
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F16
Definition: instructions.hh:25929
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:9638
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOP
GPUStaticInst * decode_OP_VOP1__V_NOP(MachInst)
Definition: decoder.cc:11041
gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32
Definition: instructions.hh:6993
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHRREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHRREV_B16(MachInst)
Definition: decoder.cc:12727
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16
Definition: instructions.hh:17909
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16
Definition: instructions.hh:14441
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F64(MachInst)
Definition: decoder.cc:7825
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U64(MachInst)
Definition: decoder.cc:10825
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I32(MachInst)
Definition: decoder.cc:12313
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:5533
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETHALT
GPUStaticInst * decode_OP_SOPP__S_SETHALT(MachInst)
Definition: decoder.cc:10915
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:12103
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:6169
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32
Definition: instructions.hh:11891
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:6481
gem5::VegaISA::Decoder::decode_OP_DS__DS_ORDERED_COUNT
GPUStaticInst * decode_OP_DS__DS_ORDERED_COUNT(MachInst)
Definition: decoder.cc:8005
gem5::VegaISA::Inst_VOP3__V_MAD_I16
Definition: instructions.hh:29535
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8125
gem5::VegaISA::InstFormat::iFmt_VINTRP
InFmt_VINTRP iFmt_VINTRP
Definition: gpu_decoder.hh:1924
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16
Definition: instructions.hh:20867
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B64
GPUStaticInst * decode_OP_SOP2__S_LSHL_B64(MachInst)
Definition: decoder.cc:4351
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9464
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst)
Definition: decoder.cc:8953
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F32
GPUStaticInst * decode_OP_VOP1__V_RSQ_F32(MachInst)
Definition: decoder.cc:11251
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:11131
gem5::VegaISA::Inst_VOP3__V_FLOOR_F32
Definition: instructions.hh:26569
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:11911
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:9990
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64
Definition: instructions.hh:23247
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8251
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9956
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32
Definition: instructions.hh:12333
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:6385
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst)
Definition: decoder.cc:10987
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64
Definition: instructions.hh:23383
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U32
Definition: instructions.hh:34179
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BCNT_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_BCNT_U32_B32(MachInst)
Definition: decoder.cc:7081
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:11659
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TRAP
GPUStaticInst * decode_OP_SOPP__S_TRAP(MachInst)
Definition: decoder.cc:10945
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:9830
gem5::VegaISA::Inst_VOP3__V_MAD_F16
Definition: instructions.hh:29463
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I32(MachInst)
Definition: decoder.cc:7885
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN
Definition: instructions.hh:36857
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F64
Definition: instructions.hh:29057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:5323
gem5::VegaISA::Inst_SOP1__S_BITSET1_B64
Definition: instructions.hh:3047
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:12001
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16
Definition: instructions.hh:17671
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32
Definition: instructions.hh:15597
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U32
Definition: instructions.hh:34329
gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64
Definition: instructions.hh:3429
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16
Definition: instructions.hh:21615
gem5::VegaISA::Inst_VOP2__V_SUBBREV_CO_U32
Definition: instructions.hh:7177
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:12619
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U64(MachInst)
Definition: decoder.cc:5713
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64
Definition: instructions.hh:12945
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U32(MachInst)
Definition: decoder.cc:6667
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:4693
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B64
GPUStaticInst * decode_OP_SOP2__S_XOR_B64(MachInst)
Definition: decoder.cc:4279
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:4987
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B32
GPUStaticInst * decode_OP_SOP2__S_XOR_B32(MachInst)
Definition: decoder.cc:4273
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:38107
gem5::VegaISA::Inst_DS__DS_AND_B64
Definition: instructions.hh:32915
gem5::VegaISA::Decoder::decode_OP_SOPP__S_DECPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_DECPERFLEVEL(MachInst)
Definition: decoder.cc:10963
gem5::VegaISA::Inst_SOP2__S_NOR_B64
Definition: instructions.hh:897
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL
Definition: instructions.hh:39093
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64
Definition: instructions.hh:13659
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2_B32(MachInst)
Definition: decoder.cc:7285
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:6043
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64
Definition: instructions.hh:20017
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I16(MachInst)
Definition: decoder.cc:6859
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F32
Definition: instructions.hh:27209
gem5::VegaISA::Inst_SOP2__S_ADD_I32
Definition: instructions.hh:115
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16
Definition: instructions.hh:14815
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10339
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U32
Definition: instructions.hh:31817
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:9566
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEMA_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEMA_F32(MachInst)
Definition: decoder.cc:6583
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9794
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP
Definition: instructions.hh:36677
gem5::VegaISA::Inst_SOP2__S_CSELECT_B64
Definition: instructions.hh:421
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:5491
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32
Definition: instructions.hh:12163
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8221
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:12337
gem5::VegaISA::Inst_SOP2__S_LSHL_B64
Definition: instructions.hh:1033
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst)
Definition: decoder.cc:8755
gem5::VegaISA::Inst_VOP3__V_COS_F16
Definition: instructions.hh:27845
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:5707
gem5::VegaISA::Inst_DS__DS_WRITE_B64
Definition: instructions.hh:33043
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32
Definition: instructions.hh:15087
gem5::VegaISA::Inst_VOP3__V_RSQ_F64
Definition: instructions.hh:26793
gem5::VegaISA::InstFormat::imm_u32
uint32_t imm_u32
Definition: gpu_decoder.hh:1936
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CNDMASK_B32
GPUStaticInst * decode_OPU_VOP3__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:5815
gem5::VegaISA::Inst_SOP2__S_ADDC_U32
Definition: instructions.hh:183
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:10000
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F32(MachInst)
Definition: decoder.cc:7465
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL3_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL3_ADD_U32(MachInst)
Definition: decoder.cc:4465
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F64
Definition: instructions.hh:35241
gem5::VegaISA::Inst_SOP1__S_NOT_B32
Definition: instructions.hh:2311
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:12601
gem5::VegaISA::Inst_VOP1__V_FFBL_B32
Definition: instructions.hh:9503
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16
Definition: instructions.hh:21139
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:5407
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P1_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:11023
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAITCNT
GPUStaticInst * decode_OP_SOPP__S_WAITCNT(MachInst)
Definition: decoder.cc:10909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F64
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F64(MachInst)
Definition: decoder.cc:6397
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:5503
gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32
Definition: instructions.hh:2151
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN_U16(MachInst)
Definition: decoder.cc:6085
gem5::VegaISA::InstFormat::iFmt_SOPP
InFmt_SOPP iFmt_SOPP
Definition: gpu_decoder.hh:1923
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL_O
Definition: instructions.hh:40893
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9530
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F16(MachInst)
Definition: decoder.cc:7009
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32
Definition: instructions.hh:11823
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8275
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I64
Definition: instructions.hh:35001
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE3
Definition: instructions.hh:26217
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_U16(MachInst)
Definition: decoder.cc:12757
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_F32
GPUStaticInst * decode_OP_DS__DS_ADD_F32(MachInst)
Definition: decoder.cc:7327
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:11671
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:11083
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F16
GPUStaticInst * decode_OPU_VOP3__V_COS_F16(MachInst)
Definition: decoder.cc:6523
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10321
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16
Definition: instructions.hh:18079
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9488
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD(MachInst)
Definition: decoder.cc:10069
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8263
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEID_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEID_F32(MachInst)
Definition: decoder.cc:6565
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:5719
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:5443
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U64
GPUStaticInst * decode_OP_DS__DS_DEC_U64(MachInst)
Definition: decoder.cc:7567
gem5::VegaISA::Inst_SOP2__S_MAX_I32
Definition: instructions.hh:319
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:12151
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I32(MachInst)
Definition: decoder.cc:5431
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F16
GPUStaticInst * decode_OP_VOP1__V_SIN_F16(MachInst)
Definition: decoder.cc:11461
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst)
Definition: decoder.cc:4609
gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64
Definition: instructions.hh:3333
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2
Definition: instructions.hh:5541
gem5::VegaISA::Inst_VOP2__V_SUB_F32
Definition: instructions.hh:6211
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_I32
Definition: instructions.hh:3781
gem5::VegaISA::Inst_SOPK__S_ADDK_I32
Definition: instructions.hh:1991
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:4969
gem5::VegaISA::Inst_DS__DS_DEC_U32
Definition: instructions.hh:30893
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16
Definition: instructions.hh:21343
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:11707
gem5::VegaISA::Inst_DS__DS_WRITE2_B64
Definition: instructions.hh:33077
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32
Definition: instructions.hh:19337
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst)
Definition: decoder.cc:9554
gem5::VegaISA::Inst_VOP2__V_MAX_U32
Definition: instructions.hh:6653
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16
Definition: instructions.hh:11619
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32
Definition: instructions.hh:30187
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F16(MachInst)
Definition: decoder.cc:11593
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F16
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F16(MachInst)
Definition: decoder.cc:6457
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32
Definition: instructions.hh:21989
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10123
gem5::VegaISA::InFmt_SMEM::OP
unsigned int OP
Definition: gpu_decoder.hh:1733
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9404
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL_O
Definition: instructions.hh:39849
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F16
GPUStaticInst * decode_OPU_VOP3__V_MED3_F16(MachInst)
Definition: decoder.cc:6889
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64
Definition: instructions.hh:23893
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9410
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B32(MachInst)
Definition: decoder.cc:10453
gem5::VegaISA::Decoder::subDecode_OP_SMEM
GPUStaticInst * subDecode_OP_SMEM(MachInst)
Definition: decoder.cc:3770
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B64
GPUStaticInst * decode_OP_SOP2__S_LSHR_B64(MachInst)
Definition: decoder.cc:4363
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:11755
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
Definition: instructions.hh:38649
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32
Definition: instructions.hh:18725
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8509
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPC
static IsaDecodeMethod tableSubDecode_OP_SOPC[128]
Definition: gpu_decoder.hh:74
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8683
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_U32
Definition: instructions.hh:1799
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32
Definition: instructions.hh:12503
gem5::VegaISA::Inst_DS__DS_INC_U64
Definition: instructions.hh:32723
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9343
gem5::VegaISA::Inst_VOP3__V_MIN3_U32
Definition: instructions.hh:28589
gem5::VegaISA::InFmt_VOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1789
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_U32
Definition: instructions.hh:1831
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XAD_U32
GPUStaticInst * decode_OPU_VOP3__V_XAD_U32(MachInst)
Definition: decoder.cc:6847
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B32
Definition: instructions.hh:31919
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U32(MachInst)
Definition: decoder.cc:7861
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CLREXCP
GPUStaticInst * decode_OPU_VOP3__V_CLREXCP(MachInst)
Definition: decoder.cc:6415
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:12523
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U32
Definition: instructions.hh:30119
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORD(MachInst)
Definition: decoder.cc:9926
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_U64(MachInst)
Definition: decoder.cc:7585
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64
GPUStaticInst * decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst)
Definition: decoder.cc:7117
gem5::VegaISA::Inst_SOPP__S_DECPERFLEVEL
Definition: instructions.hh:5055
gem5::VegaISA::Inst_VOP3__V_ADD_CO_U32
Definition: instructions.hh:24745
gem5::VegaISA::Inst_VOP3__V_SUBREV_CO_U32
Definition: instructions.hh:24817
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:5569
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16
Definition: instructions.hh:11041
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:37993
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U32
Definition: instructions.hh:3973
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B
Definition: instructions.hh:39525
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:5449
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORD
Definition: instructions.hh:5505
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst)
Definition: decoder.cc:9115
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2
Definition: instructions.hh:41809
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:12433
gem5::VegaISA::Inst_VOP3__V_MUL_F32
Definition: instructions.hh:24133
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8665
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F32
GPUStaticInst * decode_OP_DS__DS_MAX_F32(MachInst)
Definition: decoder.cc:7315
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:4825
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64
Definition: instructions.hh:16753
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9854
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B32
Definition: instructions.hh:4165
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_F32(MachInst)
Definition: decoder.cc:11227
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst)
Definition: decoder.cc:8725
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16
Definition: instructions.hh:18487
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16
Definition: instructions.hh:18215
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:5293
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10213
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32(MachInst)
Definition: decoder.cc:7051
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10225
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B16_D16_HI(MachInst)
Definition: decoder.cc:7669
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst)
Definition: decoder.cc:9007
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10165
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U64(MachInst)
Definition: decoder.cc:7729
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U64
GPUStaticInst * decode_OP_DS__DS_MAX_U64(MachInst)
Definition: decoder.cc:7591
gem5::VegaISA::Inst_SOPK__S_CMOVK_I32
Definition: instructions.hh:1575
gem5::VegaISA::Inst_VOP2__V_MUL_I32_I24
Definition: instructions.hh:6347
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst)
Definition: decoder.cc:6775
gem5::VegaISA::Inst_DS__DS_MAX_F64
Definition: instructions.hh:33241
gem5::VegaISA::Inst_VOP3__V_SUBBREV_CO_U32
Definition: instructions.hh:24929
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_F32(MachInst)
Definition: decoder.cc:6295
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:6157
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst)
Definition: decoder.cc:7849
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64
Definition: instructions.hh:19779
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:38069
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9337
gem5::VegaISA::Inst_VOP3__V_MIN3_I32
Definition: instructions.hh:28553
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:4843
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16
Definition: instructions.hh:11381
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64
Definition: instructions.hh:19915
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst)
Definition: decoder.cc:8929
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:12373
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:12133
gem5::VegaISA::Inst_DS__DS_MAX_I64
Definition: instructions.hh:32819
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C
Definition: instructions.hh:39345
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10387
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:37651
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SWAP_B32
GPUStaticInst * decode_OP_VOP1__V_SWAP_B32(MachInst)
Definition: decoder.cc:11503
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B(MachInst)
Definition: decoder.cc:9061
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9446
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst)
Definition: decoder.cc:9001
gem5::VegaISA::Inst_VOP3__V_MUL_I32_I24
Definition: instructions.hh:24167
gem5::VegaISA::InstFormat::iFmt_MIMG
InFmt_MIMG iFmt_MIMG
Definition: gpu_decoder.hh:1911
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64
Definition: instructions.hh:20357
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX
Definition: instructions.hh:36893
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst)
Definition: decoder.cc:9103
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16
Definition: instructions.hh:21479
gem5::VegaISA::Inst_VOP3__V_CNDMASK_B32
Definition: instructions.hh:23961
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XOR_B32
GPUStaticInst * decode_OPU_VOP3__V_XOR_B32(MachInst)
Definition: decoder.cc:5941
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32
Definition: instructions.hh:22261
gem5::VegaISA::Inst_VOP3__V_TRUNC_F16
Definition: instructions.hh:27717
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16
Definition: instructions.hh:13931
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64
Definition: instructions.hh:17297
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16
Definition: instructions.hh:10837
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F16(MachInst)
Definition: decoder.cc:4663
gem5::VegaISA::Inst_VOP3__V_MIN3_F32
Definition: instructions.hh:28517
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F16
Definition: instructions.hh:29671
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORD
Definition: instructions.hh:5793
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE_BUFFER
Definition: instructions.hh:6107
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64
Definition: instructions.hh:23621
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9722
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:3955
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16
Definition: instructions.hh:18453
gem5::VegaISA::Inst_DS__DS_SUB_U32
Definition: instructions.hh:30797
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F64
GPUStaticInst * decode_OP_VOP1__V_FRACT_F64(MachInst)
Definition: decoder.cc:11335
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:5779
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4
Definition: instructions.hh:41877
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I32(MachInst)
Definition: decoder.cc:6661
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B64
GPUStaticInst * decode_OP_DS__DS_XOR_B64(MachInst)
Definition: decoder.cc:7609
gem5::VegaISA::Inst_VOP3__V_SIN_F16
Definition: instructions.hh:27813
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:5107
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32
Definition: instructions.hh:21921
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F16(MachInst)
Definition: decoder.cc:11545
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:9584
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32
Definition: instructions.hh:12707
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ABSDIFF_I32
GPUStaticInst * decode_OP_SOP2__S_ABSDIFF_I32(MachInst)
Definition: decoder.cc:4429
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_I32
GPUStaticInst * decode_OPU_VOP3__V_BFE_I32(MachInst)
Definition: decoder.cc:6595
gem5::VegaISA::Inst_VOP1__V_CEIL_F32
Definition: instructions.hh:8959
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16
Definition: instructions.hh:10667
gem5::VegaISA::Inst_DS__DS_READ_U8
Definition: instructions.hh:32427
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32
Definition: instructions.hh:2695
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64
Definition: instructions.hh:16243
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:5581
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:11983
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16
Definition: instructions.hh:14645
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE(MachInst)
Definition: decoder.cc:8737
gem5::VegaISA::Inst_MIMG__IMAGE_STORE
Definition: instructions.hh:38437
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32
Definition: instructions.hh:18657
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I32(MachInst)
Definition: decoder.cc:7381
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B64
Definition: instructions.hh:33113
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64
Definition: instructions.hh:16413
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:12277
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:11509
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst)
Definition: decoder.cc:6631
gem5::VegaISA::Inst_DS__DS_MAX_U64
Definition: instructions.hh:32883
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X
Definition: instructions.hh:37765
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10141
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10381
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64
Definition: instructions.hh:12979
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32
Definition: instructions.hh:31251
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:11947
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9500
gem5::VegaISA::Inst_SOP2__S_MUL_I32
Definition: instructions.hh:1271
gem5::VegaISA::InFmt_VOP3A
Definition: gpu_decoder.hh:1802
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE(MachInst)
Definition: decoder.cc:8173
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F16
GPUStaticInst * decode_OP_VOP2__V_MUL_F16(MachInst)
Definition: decoder.cc:4051
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32
Definition: instructions.hh:12129
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F32
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F32(MachInst)
Definition: decoder.cc:6283
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:5341
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:9614
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst)
Definition: decoder.cc:10879
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B64
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B64(MachInst)
Definition: decoder.cc:4291
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10267
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT(MachInst)
Definition: decoder.cc:9776
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I32(MachInst)
Definition: decoder.cc:6643
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:12529
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B32
GPUStaticInst * decode_OP_SOP1__S_NOT_B32(MachInst)
Definition: decoder.cc:10417
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64
Definition: instructions.hh:10497
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8155
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:5803
gem5::VegaISA::Inst_VOP2__V_CNDMASK_B32
Definition: instructions.hh:6141
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I64
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I64(MachInst)
Definition: decoder.cc:7111
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32
Definition: instructions.hh:18521
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:5467
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F16
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F16(MachInst)
Definition: decoder.cc:11431
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64
Definition: instructions.hh:20323
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:4723
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:5455
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:4699
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B16
Definition: instructions.hh:25307
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10315
gem5::VegaISA::Inst_VOP2__V_SUBREV_U32
Definition: instructions.hh:8001
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B64(MachInst)
Definition: decoder.cc:8077
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC0
Definition: instructions.hh:4541
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L
Definition: instructions.hh:39201
gem5::VegaISA::Inst_VOP3__V_MAD_I64_I32
Definition: instructions.hh:29425
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B64(MachInst)
Definition: decoder.cc:8065
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:6529
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM
GPUStaticInst * decode_OP_SOPP__S_ENDPGM(MachInst)
Definition: decoder.cc:10843
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC(MachInst)
Definition: decoder.cc:8611
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:4999
gem5::VegaISA::Inst_SOP2__S_XOR_B64
Definition: instructions.hh:625
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F64
Definition: instructions.hh:8703
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_F32
Definition: instructions.hh:34539
gem5::VegaISA::Inst_VOP3__V_BFREV_B32
Definition: instructions.hh:26985
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_U8(MachInst)
Definition: decoder.cc:6691
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B32
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B32(MachInst)
Definition: decoder.cc:4285
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32
Definition: instructions.hh:22023
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32
Definition: instructions.hh:21785
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9398
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U32(MachInst)
Definition: decoder.cc:12361
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst)
Definition: decoder.cc:9241
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst)
Definition: decoder.cc:10993
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B32(MachInst)
Definition: decoder.cc:7909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_U16_F16(MachInst)
Definition: decoder.cc:7165
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32
Definition: instructions.hh:22193
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F32
GPUStaticInst * decode_OP_VOP2__V_MAC_F32(MachInst)
Definition: decoder.cc:3979
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:11893
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B16
Definition: instructions.hh:25273
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:4867
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16
Definition: instructions.hh:14305
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONSUME
GPUStaticInst * decode_OP_DS__DS_CONSUME(MachInst)
Definition: decoder.cc:7993
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SSHORT
Definition: instructions.hh:36159
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I32(MachInst)
Definition: decoder.cc:5473
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I32
Definition: instructions.hh:24541
gem5::VegaISA::Inst_VOP3__V_RCP_F64
Definition: instructions.hh:26761
gem5::VegaISA::Inst_VOP3__V_FFBL_B32
Definition: instructions.hh:27049
gem5::VegaISA::Inst_VOP3__V_LOG_F16
Definition: instructions.hh:27525
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U32(MachInst)
Definition: decoder.cc:7897
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:5869
gem5::VegaISA::Inst_VOP3__V_RNDNE_F32
Definition: instructions.hh:26537
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U32
GPUStaticInst * decode_OP_DS__DS_INC_U32(MachInst)
Definition: decoder.cc:7219
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:11959
gem5::VegaISA::Inst_VOP3__V_MBCNT_LO_U32_B32
Definition: instructions.hh:30357
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_BR
Definition: instructions.hh:34661
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32
Definition: instructions.hh:19541
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:12481
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U16(MachInst)
Definition: decoder.cc:12211
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_U32(MachInst)
Definition: decoder.cc:4561
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:11833
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN_I32(MachInst)
Definition: decoder.cc:5887
gem5::VegaISA::InFmt_DS::OP
unsigned int OP
Definition: gpu_decoder.hh:1606
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:12427
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_O
Definition: instructions.hh:40857
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX
GPUStaticInst * decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst)
Definition: decoder.cc:10681
gem5::VegaISA::Inst_VOP3__V_MUL_F64
Definition: instructions.hh:29983
gem5::VegaISA::Inst_SOP2__S_BFE_U64
Definition: instructions.hh:1373
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16
Definition: instructions.hh:11653
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32
Definition: instructions.hh:22771
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10261
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U64(MachInst)
Definition: decoder.cc:8017
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_U16(MachInst)
Definition: decoder.cc:6799
gem5::VegaISA::Inst_VOP1__V_CEIL_F16
Definition: instructions.hh:10139
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B64
GPUStaticInst * decode_OP_DS__DS_READ_B64(MachInst)
Definition: decoder.cc:7831
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F64
Definition: instructions.hh:26249
gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32
Definition: instructions.hh:32527
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:5317
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_U16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U16(MachInst)
Definition: decoder.cc:6031
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F32
Definition: instructions.hh:34479
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32
Definition: instructions.hh:18895
gem5::VegaISA::InFmt_MIMG
Definition: gpu_decoder.hh:1658
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F32
Definition: instructions.hh:8287
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8521
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:5497
gem5::VegaISA::Decoder::tableSubDecode_OP_SMEM
static IsaDecodeMethod tableSubDecode_OP_SMEM[256]
Definition: gpu_decoder.hh:72
gem5::VegaISA::Inst_VOP1__V_SQRT_F32
Definition: instructions.hh:9279
gem5::VegaISA::Inst_SOP2__S_SUB_U32
Definition: instructions.hh:81
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_U32(MachInst)
Definition: decoder.cc:4543
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst)
Definition: decoder.cc:7801
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2
Definition: instructions.hh:5721
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I32
Definition: instructions.hh:34239
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64
Definition: instructions.hh:23111
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC
Definition: instructions.hh:42291
gem5::VegaISA::Inst_VOP2__V_MADMK_F16
Definition: instructions.hh:7385
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16_HI(MachInst)
Definition: decoder.cc:7681
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F32
GPUStaticInst * decode_OPU_VOP3__V_ADD_F32(MachInst)
Definition: decoder.cc:5821
gem5::VegaISA::Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64
GPUStaticInst * decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst)
Definition: decoder.cc:4435
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:11821
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B64(MachInst)
Definition: decoder.cc:8083
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B32
GPUStaticInst * decode_OP_SOP2__S_XNOR_B32(MachInst)
Definition: decoder.cc:4333
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:4099
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16
Definition: instructions.hh:14781
gem5::VegaISA::InFmt_SOP1::ENCODING
unsigned int ENCODING
Definition: gpu_decoder.hh:1747
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10327
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMTIME
GPUStaticInst * decode_OP_SMEM__S_MEMTIME(MachInst)
Definition: decoder.cc:10045
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64
Definition: instructions.hh:13149
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F32
Definition: instructions.hh:25833
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:11887
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC0
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC0(MachInst)
Definition: decoder.cc:10861
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U32(MachInst)
Definition: decoder.cc:7357
gem5::VegaISA::Inst_VOP1__V_FFBH_U32
Definition: instructions.hh:9471
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16
Definition: instructions.hh:20765
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64
Definition: instructions.hh:2663
gem5::VegaISA::InstFormat::iFmt_MTBUF
InFmt_MTBUF iFmt_MTBUF
Definition: gpu_decoder.hh:1913
gem5::VegaISA::InFmt_FLAT::OP
unsigned int OP
Definition: gpu_decoder.hh:1641
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8617
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL
Definition: instructions.hh:40353
gem5::VegaISA::Inst_DS__DS_READ2_B64
Definition: instructions.hh:33987
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:9686
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_F32(MachInst)
Definition: decoder.cc:5845
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F64(MachInst)
Definition: decoder.cc:11977
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F16
GPUStaticInst * decode_OP_VOP2__V_MAX_F16(MachInst)
Definition: decoder.cc:4117
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B64
Definition: instructions.hh:33749
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16
Definition: instructions.hh:17501
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8179
gem5::VegaISA::InFmt_DS
Definition: gpu_decoder.hh:1602
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst)
Definition: decoder.cc:10885
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT
Definition: instructions.hh:41503
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U16(MachInst)
Definition: decoder.cc:12169
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:5647
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32
Definition: instructions.hh:3525
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I32
Definition: instructions.hh:6721
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16
Definition: instructions.hh:17739
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U32
GPUStaticInst * decode_OPU_VOP3__V_SAD_U32(MachInst)
Definition: decoder.cc:6709
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst)
Definition: decoder.cc:8899
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B64
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B64(MachInst)
Definition: decoder.cc:7765
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst)
Definition: decoder.cc:8887
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64
Definition: instructions.hh:23077
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK
GPUStaticInst * decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst)
Definition: decoder.cc:4591
gem5::VegaISA::Inst_VOP1__V_READFIRSTLANE_B32
Definition: instructions.hh:8095
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F32
GPUStaticInst * decode_OP_VOP2__V_MAX_F32(MachInst)
Definition: decoder.cc:3913
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_U32
Definition: instructions.hh:1959
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B32
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B32(MachInst)
Definition: decoder.cc:7405
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:4981
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_U16(MachInst)
Definition: decoder.cc:12751
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64
Definition: instructions.hh:23655
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64
Definition: instructions.hh:13353
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64
Definition: instructions.hh:16311
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:12319
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F16
GPUStaticInst * decode_OP_VOP1__V_RCP_F16(MachInst)
Definition: decoder.cc:11389
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:11533
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64
Definition: instructions.hh:19813
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_ADDTID_B32(MachInst)
Definition: decoder.cc:7333
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B32
Definition: instructions.hh:34449
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:12673
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32
Definition: instructions.hh:22499
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B32(MachInst)
Definition: decoder.cc:10549
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F32
Definition: instructions.hh:29093
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:5305
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64
Definition: instructions.hh:16617
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B64
Definition: instructions.hh:33783
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:5065
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst)
Definition: decoder.cc:8137
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETPRIO
GPUStaticInst * decode_OP_SOPP__S_SETPRIO(MachInst)
Definition: decoder.cc:10927
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst)
Definition: decoder.cc:8857
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U16
GPUStaticInst * decode_OP_VOP2__V_SUB_U16(MachInst)
Definition: decoder.cc:4081
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U64
Definition: instructions.hh:4357
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B32
Definition: instructions.hh:34419
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64
Definition: instructions.hh:16821
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL2_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL2_ADD_U32(MachInst)
Definition: decoder.cc:4459
gem5::VegaISA::Inst_VOP2__V_MAX_I32
Definition: instructions.hh:6585
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10081
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32
Definition: instructions.hh:15121
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV_VOL
Definition: instructions.hh:5957
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F16
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F16(MachInst)
Definition: decoder.cc:6451
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F16
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F16(MachInst)
Definition: decoder.cc:11443
gem5::VegaISA::Inst_DS__DS_READ_U16
Definition: instructions.hh:32493
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst)
Definition: decoder.cc:6745
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE2
Definition: instructions.hh:8639
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:11377
gem5::VegaISA::Inst_SOPP__S_SLEEP
Definition: instructions.hh:4845
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F16
GPUStaticInst * decode_OP_VOP1__V_FRACT_F16(MachInst)
Definition: decoder.cc:11455
gem5::VegaISA::Inst_VOP1__V_CVT_OFF_F32_I4
Definition: instructions.hh:8479
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32
Definition: instructions.hh:15427
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9524
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:5587
gem5::VegaISA::Inst_SOP2__S_OR_B32
Definition: instructions.hh:523
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Definition: instructions.hh:42359
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:9644
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10093
gem5::VegaISA::Inst_SMEM__S_MEMTIME
Definition: instructions.hh:6013
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16
Definition: instructions.hh:21037
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
Definition: instructions.hh:40029
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9416
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B64
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B64(MachInst)
Definition: decoder.cc:4243
gem5::VegaISA::Inst_VOP2__V_MAX_F32
Definition: instructions.hh:6517
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10621
gem5::VegaISA::InstFormat::iFmt_VOP1
InFmt_VOP1 iFmt_VOP1
Definition: gpu_decoder.hh:1925
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CBRANCH_JOIN
GPUStaticInst * decode_OP_SOP1__S_CBRANCH_JOIN(MachInst)
Definition: decoder.cc:10669
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:5161
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
Definition: instructions.hh:38401
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_I32(MachInst)
Definition: decoder.cc:4537
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD
Definition: instructions.hh:38221
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F64
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F64(MachInst)
Definition: decoder.cc:6241
gem5::VegaISA::Decoder::decode_OP_EXP
GPUStaticInst * decode_OP_EXP(MachInst)
Definition: decoder.cc:4621
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAKEUP
GPUStaticInst * decode_OP_SOPP__S_WAKEUP(MachInst)
Definition: decoder.cc:10855
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst)
Definition: decoder.cc:7129
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F32
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F32(MachInst)
Definition: decoder.cc:11221
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:35961
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L
Definition: instructions.hh:39489
gem5::VegaISA::Inst_VOP2__V_MAC_F16
Definition: instructions.hh:7351
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64
Definition: instructions.hh:17059
gem5::VegaISA::Inst_VOP1__V_TRUNC_F16
Definition: instructions.hh:10171
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR(MachInst)
Definition: decoder.cc:8599
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10243
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2
Definition: instructions.hh:5829
gem5::VegaISA::Inst_VOP2__V_MUL_LO_U16
Definition: instructions.hh:7559
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:5617
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK
Definition: instructions.hh:38293
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:12511
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:11761
gem5::VegaISA::Inst_VOP3__V_CEIL_F32
Definition: instructions.hh:26505
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16
Definition: instructions.hh:10565
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_WRITELANE_B32
GPUStaticInst * decode_OPU_VOP3__V_WRITELANE_B32(MachInst)
Definition: decoder.cc:7075
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64
Definition: instructions.hh:23791
gem5::VegaISA::Inst_VOP1__V_CVT_RPI_I32_F32
Definition: instructions.hh:8415
gem5::VegaISA::Inst_SOPK__S_MULK_I32
Definition: instructions.hh:2023
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64
Definition: instructions.hh:23349
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9734
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B64
GPUStaticInst * decode_OP_SOP2__S_NOR_B64(MachInst)
Definition: decoder.cc:4327
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:5389
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:5377
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_I16_F16(MachInst)
Definition: decoder.cc:11485
gem5::VegaISA::InstFormat::iFmt_VOPC
InFmt_VOPC iFmt_VOPC
Definition: gpu_decoder.hh:1930
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_F32(MachInst)
Definition: decoder.cc:7303
gem5::VegaISA::Inst_VOP1__V_CVT_U16_F16
Definition: instructions.hh:9819
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B32
GPUStaticInst * decode_OP_SOP2__S_OR_B32(MachInst)
Definition: decoder.cc:4261
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_I32
Definition: instructions.hh:1607
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:37689
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_I32
Definition: instructions.hh:1639
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U16(MachInst)
Definition: decoder.cc:5329
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORD(MachInst)
Definition: decoder.cc:8485
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2
Definition: instructions.hh:42635
gem5::VegaISA::Inst_VOP2__V_SUBREV_F32
Definition: instructions.hh:6245
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B32
GPUStaticInst * decode_OP_DS__DS_OR_B32(MachInst)
Definition: decoder.cc:7261
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F32
Definition: instructions.hh:34509
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32
Definition: instructions.hh:18827
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8329
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8317
gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32
Definition: instructions.hh:1475
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9380
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_U32(MachInst)
Definition: decoder.cc:10765
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F32
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F32(MachInst)
Definition: decoder.cc:11203
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_LSHL_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_LSHL_U32(MachInst)
Definition: decoder.cc:6913
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8587
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F64(MachInst)
Definition: decoder.cc:7813
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:12247
gem5::VegaISA::Decoder::subDecode_OP_VOP3P
GPUStaticInst * subDecode_OP_VOP3P(MachInst)
Definition: decoder.cc:3730
gem5::VegaISA::Inst_DS__DS_WRITE_B96
Definition: instructions.hh:35301
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I32
Definition: instructions.hh:34269
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_U16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:11365
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16_HI(MachInst)
Definition: decoder.cc:7693
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8401
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:5125
gem5::VegaISA::Inst_SOPP__S_TRAP
Definition: instructions.hh:4965
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16
Definition: instructions.hh:11279
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC
Definition: instructions.hh:42325
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8
Definition: instructions.hh:5613
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:5017
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B64(MachInst)
Definition: decoder.cc:10495
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F64
GPUStaticInst * decode_OPU_VOP3__V_MAX_F64(MachInst)
Definition: decoder.cc:7033
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B32
GPUStaticInst * decode_OP_SOP2__S_LSHR_B32(MachInst)
Definition: decoder.cc:4357
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9746
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10099
gem5::VegaISA::Inst_VOP2__V_ADD_U32
Definition: instructions.hh:7933
gem5::VegaISA::Inst_VOP1__V_LOG_F32
Definition: instructions.hh:9087
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:4783
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_LDS_DWORD
Definition: instructions.hh:36585
gem5::VegaISA::Inst_VOP3__V_CVT_U16_F16
Definition: instructions.hh:27365
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16
Definition: instructions.hh:14543
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:6139
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_MODE
Definition: instructions.hh:5295
gem5::VegaISA::Inst_SOP2__S_XOR_B32
Definition: instructions.hh:591
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16
Definition: instructions.hh:11585
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F32
GPUStaticInst * decode_OPU_VOP3__V_SIN_F32(MachInst)
Definition: decoder.cc:6343
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32
Definition: instructions.hh:22737
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F32
GPUStaticInst * decode_OP_VOP1__V_FRACT_F32(MachInst)
Definition: decoder.cc:11197
gem5::VegaISA::Inst_VOP3__V_SAD_U16
Definition: instructions.hh:28913
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I64
Definition: instructions.hh:33443
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I32
GPUStaticInst * decode_OPU_VOP3__V_SUB_I32(MachInst)
Definition: decoder.cc:7177
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8797
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L
Definition: instructions.hh:40497
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_AND
Definition: instructions.hh:38887
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64
Definition: instructions.hh:20255
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst)
Definition: decoder.cc:9157
gem5::VegaISA::Inst_SOP2__S_XNOR_B64
Definition: instructions.hh:965
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:5557
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:12463
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I8
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I8(MachInst)
Definition: decoder.cc:10525
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10345
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B32(MachInst)
Definition: decoder.cc:7291
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16
Definition: instructions.hh:5649
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U64
GPUStaticInst * decode_OP_DS__DS_ADD_U64(MachInst)
Definition: decoder.cc:7543
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U64
Definition: instructions.hh:34911
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F64
Definition: instructions.hh:33885
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32
Definition: instructions.hh:15359
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U32(MachInst)
Definition: decoder.cc:7375
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
Definition: instructions.hh:37397
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F32
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F32(MachInst)
Definition: decoder.cc:7063
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F64
GPUStaticInst * decode_OPU_VOP3__V_MIN_F64(MachInst)
Definition: decoder.cc:7027
gem5::VegaISA::Inst_VOP1__V_FFBH_I32
Definition: instructions.hh:9535
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUBB_U32
GPUStaticInst * decode_OP_SOP2__S_SUBB_U32(MachInst)
Definition: decoder.cc:4207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:4795
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:11521
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64
Definition: instructions.hh:23519
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16
Definition: instructions.hh:21207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:5257
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8377
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst)
Definition: decoder.cc:9073
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_U32(MachInst)
Definition: decoder.cc:4549
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10357
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:11479
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4(MachInst)
Definition: decoder.cc:9037
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT
Definition: instructions.hh:36121
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16
Definition: instructions.hh:11313
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_U16_F16(MachInst)
Definition: decoder.cc:11491
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT(MachInst)
Definition: decoder.cc:8185
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64
Definition: instructions.hh:13251
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SWAP
Definition: instructions.hh:38615
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_ADD_U32(MachInst)
Definition: decoder.cc:4177
gem5::VegaISA::Inst_VOP3__V_SUB_F32
Definition: instructions.hh:24031
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:12193
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:5599
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16
Definition: instructions.hh:21717
gem5::VegaISA::Inst_VOP3__V_CEIL_F16
Definition: instructions.hh:27685
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:9866
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:35771
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:5233
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F32(MachInst)
Definition: decoder.cc:4855
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst)
Definition: decoder.cc:9223
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32
Definition: instructions.hh:19371
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst)
Definition: decoder.cc:7141
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_B32(MachInst)
Definition: decoder.cc:7273
gem5::VegaISA::Inst_SOPP__S_WAITCNT
Definition: instructions.hh:4785
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16
Definition: instructions.hh:14917
gem5::VegaISA::Inst_VOP3__V_SQRT_F32
Definition: instructions.hh:26825
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B64
Definition: instructions.hh:33647
gem5::VegaISA::Inst_VOP3__V_CVT_PKACCUM_U8_F32
Definition: instructions.hh:29707
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16
Definition: instructions.hh:17773
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I32(MachInst)
Definition: decoder.cc:7891
gem5::VegaISA::Decoder::decode_OP_DS__DS_NOP
GPUStaticInst * decode_OP_DS__DS_NOP(MachInst)
Definition: decoder.cc:7321
gem5::VegaISA::Inst_VOP2__V_SUB_U16
Definition: instructions.hh:7491
gem5::VegaISA::Decoder::subDecode_OP_VOP1
GPUStaticInst * subDecode_OP_VOP1(MachInst)
Definition: decoder.cc:3738
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE0
Definition: instructions.hh:26121
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMAX
Definition: instructions.hh:38819
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F16
GPUStaticInst * decode_OPU_VOP3__V_ADD_F16(MachInst)
Definition: decoder.cc:5989
gem5::VegaISA::Inst_SOP2__S_BFE_U32
Definition: instructions.hh:1305
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F32
Definition: instructions.hh:29775
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F16
GPUStaticInst * decode_OPU_VOP3__V_RCP_F16(MachInst)
Definition: decoder.cc:6445
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32
Definition: instructions.hh:21955
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F32
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F32(MachInst)
Definition: decoder.cc:6277
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32
Definition: instructions.hh:19201
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:5311
gem5::VegaISA::Inst_SOP2__S_LSHR_B32
Definition: instructions.hh:1067
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8365
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX
Definition: instructions.hh:36929
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:4831
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:11167
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8413
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:9944
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_I32(MachInst)
Definition: decoder.cc:7231
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_F16(MachInst)
Definition: decoder.cc:12787
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I32
GPUStaticInst * decode_OPU_VOP3__V_ADD_I32(MachInst)
Definition: decoder.cc:7171
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16(MachInst)
Definition: decoder.cc:7699
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMIN
Definition: instructions.hh:38751
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:3997
gem5::VegaISA::Decoder::subDecode_OP_SOPP
GPUStaticInst * subDecode_OP_SOPP(MachInst)
Definition: decoder.cc:3762
gem5::VegaISA::Inst_VOP2__V_SUBB_CO_U32
Definition: instructions.hh:7139
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9386
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32
Definition: instructions.hh:22465
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:35923
gem5::VegaISA::Inst_VOP3__V_FFBH_U32
Definition: instructions.hh:27017
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE(MachInst)
Definition: decoder.cc:11017
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst)
Definition: decoder.cc:8941
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:5653
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U64(MachInst)
Definition: decoder.cc:8053
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64
Definition: instructions.hh:20391
gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64
Definition: instructions.hh:3237
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:5035
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst)
Definition: decoder.cc:6751
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U32(MachInst)
Definition: decoder.cc:7867
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV
Definition: instructions.hh:5901
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:9590
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:12043
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_U32(MachInst)
Definition: decoder.cc:4555
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR
Definition: instructions.hh:37037
gem5::VegaISA::Inst_VOP3__V_SUBB_CO_U32
Definition: instructions.hh:24891
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16
Definition: instructions.hh:17399
gem5::VegaISA::Decoder::~Decoder
~Decoder()
Definition: decoder.cc:49
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_V
Definition: instructions.hh:34631
gem5::VegaISA::Decoder::tableSubDecode_OP_VINTRP
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4]
Definition: gpu_decoder.hh:76
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10687
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8803
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B32(MachInst)
Definition: decoder.cc:7447
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32
Definition: instructions.hh:15461
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B64(MachInst)
Definition: decoder.cc:10483
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32
Definition: instructions.hh:15223
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8569
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:12409
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:11245
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:6979
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B64(MachInst)
Definition: decoder.cc:10507
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U8_F32
Definition: instructions.hh:28985
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64
Definition: instructions.hh:13557
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F64(MachInst)
Definition: decoder.cc:8089
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
Definition: instructions.hh:36713
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10087
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT
Definition: instructions.hh:41537
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B64(MachInst)
Definition: decoder.cc:10801
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_U32
GPUStaticInst * decode_OP_SOP2__S_SUB_U32(MachInst)
Definition: decoder.cc:4183
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Definition: instructions.hh:42703
gem5::VegaISA::Inst_SOP2__S_BFE_I64
Definition: instructions.hh:1407
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64
Definition: instructions.hh:20561
gem5::VegaISA::Inst_SOPP__S_SENDMSG
Definition: instructions.hh:4905
gem5::VegaISA::Inst_DS__DS_READ_B128
Definition: instructions.hh:35397
gem5::VegaISA::Inst_DS__DS_READ2_B32
Definition: instructions.hh:32327
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16
Definition: instructions.hh:18181
gem5::VegaISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1682
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B32(MachInst)
Definition: decoder.cc:10789
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F16(MachInst)
Definition: decoder.cc:6001
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F32
Definition: instructions.hh:27241
gem5::VegaISA::Inst_VOP1__V_CVT_F16_F32
Definition: instructions.hh:8351
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B32(MachInst)
Definition: decoder.cc:10501
gem5::VegaISA::Decoder::decode_OP_SOP1__S_GETPC_B64
GPUStaticInst * decode_OP_SOP1__S_GETPC_B64(MachInst)
Definition: decoder.cc:10561
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:11701
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:9572
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:12439
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16
Definition: instructions.hh:21445
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10201
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:5251
gem5::VegaISA::Inst_VOP3__V_SAD_U8
Definition: instructions.hh:28841
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_READ_ADDTID_B32(MachInst)
Definition: decoder.cc:7987
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32
Definition: instructions.hh:15937
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_O
Definition: instructions.hh:39921
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:11341
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32
Definition: instructions.hh:12027
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:11995
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16
Definition: instructions.hh:13999
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:5755
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U32
GPUStaticInst * decode_OP_DS__DS_SUB_U32(MachInst)
Definition: decoder.cc:7207
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U16
GPUStaticInst * decode_OP_VOP2__V_MAX_U16(MachInst)
Definition: decoder.cc:4129
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L_O
Definition: instructions.hh:40929
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F64
Definition: instructions.hh:27145
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst)
Definition: decoder.cc:8905
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:9818
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:5857
gem5::VegaISA::Inst_VOP1__V_SQRT_F64
Definition: instructions.hh:9311
gem5::VegaISA::Inst_VOP3__V_CVT_F16_F32
Definition: instructions.hh:25897
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE
Definition: instructions.hh:39057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F32(MachInst)
Definition: decoder.cc:6637
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32
Definition: instructions.hh:22227
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_OR_B32(MachInst)
Definition: decoder.cc:6931
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst)
Definition: decoder.cc:8713
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB(MachInst)
Definition: decoder.cc:10027
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I32
GPUStaticInst * decode_OP_SOP2__S_BFE_I32(MachInst)
Definition: decoder.cc:4405
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32
Definition: instructions.hh:22805
gem5::VegaISA::Inst_SOPC__S_CMP_LT_I32
Definition: instructions.hh:3909
gem5::VegaISA::Inst_SOP1__S_MOV_B64
Definition: instructions.hh:2215
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16
Definition: instructions.hh:21751
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst)
Definition: decoder.cc:9211
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16
Definition: instructions.hh:10735
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U64(MachInst)
Definition: decoder.cc:7759
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32
Definition: instructions.hh:3461
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16
Definition: instructions.hh:14203
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst)
Definition: decoder.cc:9121
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8647
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B64
Definition: instructions.hh:4261
gem5::VegaISA::Inst_DS__DS_INC_RTN_U64
Definition: instructions.hh:33375
gem5::VegaISA::Inst_SOP2__S_SUB_I32
Definition: instructions.hh:149
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I32
GPUStaticInst * decode_OP_SOP2__S_ASHR_I32(MachInst)
Definition: decoder.cc:4369
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_U32
GPUStaticInst * decode_OP_SOP2__S_MIN_U32(MachInst)
Definition: decoder.cc:4219
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16
Definition: instructions.hh:13897
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1
Definition: instructions.hh:36617
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:5263
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:11869
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:11569
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:3871
gem5::VegaISA::InFmt_SOPP
Definition: gpu_decoder.hh:1772
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U24(MachInst)
Definition: decoder.cc:6559
gem5::VegaISA::Inst_DS__DS_NOP
Definition: instructions.hh:31415
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_U32(MachInst)
Definition: decoder.cc:7243
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_I16(MachInst)
Definition: decoder.cc:12739
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64
Definition: instructions.hh:3493
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F16
Definition: instructions.hh:10043
gem5::VegaISA::Inst_SOP2__S_ASHR_I32
Definition: instructions.hh:1135
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst)
Definition: decoder.cc:10039
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE(MachInst)
Definition: decoder.cc:9764
gem5::VegaISA::Inst_SOP1__S_BITSET0_B32
Definition: instructions.hh:2951
gem5::VegaISA::Inst_DS__DS_OR_RTN_B32
Definition: instructions.hh:31885
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:5119
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64
Definition: instructions.hh:16515
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:11743
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:12625
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR
Definition: instructions.hh:42257
gem5::VegaISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1703
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:35467
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16
Definition: instructions.hh:10633
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB
Definition: instructions.hh:36785
gem5::VegaISA::Inst_VOP3__V_MAX_U32
Definition: instructions.hh:24473
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst)
Definition: decoder.cc:9019
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X
Definition: instructions.hh:35581
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B32
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B32(MachInst)
Definition: decoder.cc:10633
gem5::VegaISA::InstFormat::iFmt_SOP1
InFmt_SOP1 iFmt_SOP1
Definition: gpu_decoder.hh:1919
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE
Definition: instructions.hh:6073
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:9920
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst)
Definition: decoder.cc:6733
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9974
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:3943
gem5::VegaISA::Inst_VOP3__V_FRACT_F32
Definition: instructions.hh:26441
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:11815
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9512
gem5::VegaISA::Inst_DS__DS_WRAP_RTN_B32
Definition: instructions.hh:32225
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64
Definition: instructions.hh:20595
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_I32(MachInst)
Definition: decoder.cc:4531
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F32(MachInst)
Definition: decoder.cc:4897
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F64
Definition: instructions.hh:9567
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32
Definition: instructions.hh:17263
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F16
GPUStaticInst * decode_OP_VOP2__V_SUB_F16(MachInst)
Definition: decoder.cc:4039
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U64(MachInst)
Definition: decoder.cc:8059
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_O
Definition: instructions.hh:39813
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F16(MachInst)
Definition: decoder.cc:6853
gem5::VegaISA::Inst_SOPC__S_CMP_LT_U32
Definition: instructions.hh:4101
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst)
Definition: decoder.cc:7435
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B32
GPUStaticInst * decode_OP_SOP1__S_CMOV_B32(MachInst)
Definition: decoder.cc:10405
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16
Definition: instructions.hh:14373
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32
Definition: instructions.hh:12537
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_F64(MachInst)
Definition: decoder.cc:7645
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64
Definition: instructions.hh:12775
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B64(MachInst)
Definition: decoder.cc:10663
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL
Definition: instructions.hh:40461
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64
Definition: instructions.hh:20459
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SLEEP
GPUStaticInst * decode_OP_SOPP__S_SLEEP(MachInst)
Definition: decoder.cc:10921
gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64
Definition: instructions.hh:3269
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
Definition: instructions.hh:37145
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:12367
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B64(MachInst)
Definition: decoder.cc:7807
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_I32
Definition: instructions.hh:1767
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F64(MachInst)
Definition: decoder.cc:11971
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B64
GPUStaticInst * decode_OP_SOP2__S_OR_B64(MachInst)
Definition: decoder.cc:4267
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U64
Definition: instructions.hh:33511
gem5::VegaISA::Inst_SOPP__S_SENDMSGHALT
Definition: instructions.hh:4935
gem5::VegaISA::Inst_VOP1__V_RSQ_F32
Definition: instructions.hh:9183
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_U32
Definition: instructions.hh:1863
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_U32(MachInst)
Definition: decoder.cc:4567
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_RELEASE_ALL
Definition: instructions.hh:34569
gem5::VegaISA::Inst_VOP1__V_RCP_F32
Definition: instructions.hh:9119
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:11851
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64
Definition: instructions.hh:16039
gem5::VegaISA::Inst_SOP1__S_RFE_B64
Definition: instructions.hh:3173
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8575
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_U32
Definition: instructions.hh:1927
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32
Definition: instructions.hh:19269
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D
Definition: instructions.hh:39129
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADDC_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:4015
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_U32(MachInst)
Definition: decoder.cc:4573
gem5::VegaISA::Inst_DS__DS_READ_I8
Definition: instructions.hh:32395
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B64
GPUStaticInst * decode_OP_SOP1__S_NOT_B64(MachInst)
Definition: decoder.cc:10423
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_SAVED
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_SAVED(MachInst)
Definition: decoder.cc:10999
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U64(MachInst)
Definition: decoder.cc:12553
gem5::VegaISA::InFmt_MIMG::OP
unsigned int OP
Definition: gpu_decoder.hh:1668
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst)
Definition: decoder.cc:6829
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B64
GPUStaticInst * decode_OP_SOP1__S_CMOV_B64(MachInst)
Definition: decoder.cc:10411
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_B64(MachInst)
Definition: decoder.cc:7639
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32
Definition: instructions.hh:22533
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:5185
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:5401
gem5::VegaISA::Inst_SOP2__S_NOR_B32
Definition: instructions.hh:863
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_I16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:6427
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:12493
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:3883
gem5::VegaISA::Inst_MIMG__IMAGE_GET_LOD
Definition: instructions.hh:41073
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:6121
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:5077
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:4759
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3
Definition: instructions.hh:41843
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:6181
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64
Definition: instructions.hh:17093
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:9692
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX_F32(MachInst)
Definition: decoder.cc:5881
gem5::VegaISA::Inst_VOP1__V_RNDNE_F16
Definition: instructions.hh:10203
gem5::VegaISA::Inst_VOP3__V_LDEXP_F32
Definition: instructions.hh:30221
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:12685
gem5::VegaISA::Inst_DS__DS_READ_I16
Definition: instructions.hh:32461
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:12127
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_U32(MachInst)
Definition: decoder.cc:10771
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:12649
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9452
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8
GPUStaticInst * decode_OP_DS__DS_READ_I8(MachInst)
Definition: decoder.cc:7501
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_U32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_U32(MachInst)
Definition: decoder.cc:6367
gem5::VegaISA::Inst_DS__DS_WRITE_B32
Definition: instructions.hh:31181
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F32(MachInst)
Definition: decoder.cc:11737
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U32
GPUStaticInst * decode_OP_DS__DS_ADD_U32(MachInst)
Definition: decoder.cc:7201
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst)
Definition: decoder.cc:9169
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F64
Definition: instructions.hh:29131
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B32
GPUStaticInst * decode_OP_SOP1__S_BREV_B32(MachInst)
Definition: decoder.cc:10441
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:9824
gem5::VegaISA::Inst_VOP3__V_FFBH_I32
Definition: instructions.hh:27081
gem5::VegaISA::Inst_VOP1__V_CVT_F32_U32
Definition: instructions.hh:8223
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:11071
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:5635
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B32(MachInst)
Definition: decoder.cc:10489
gem5::VegaISA::Inst_VOP3__V_READLANE_B32
Definition: instructions.hh:30255
gem5::VegaISA::Inst_SOP2__S_MIN_U32
Definition: instructions.hh:285
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN_U32(MachInst)
Definition: decoder.cc:5899
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64
Definition: instructions.hh:13727
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64
Definition: instructions.hh:16957
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9265
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:12397
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:5071
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:11617
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:38183
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U32(MachInst)
Definition: decoder.cc:10753
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10171
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst)
Definition: decoder.cc:9163
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16
Definition: instructions.hh:11245
gem5::VegaISA::Inst_VOP3__V_CVT_F32_U32
Definition: instructions.hh:25769
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L_O
Definition: instructions.hh:40065
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:11899
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_U32
GPUStaticInst * decode_OP_SOP2__S_MAX_U32(MachInst)
Definition: decoder.cc:4231
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F64
GPUStaticInst * decode_OP_VOP1__V_RCP_F64(MachInst)
Definition: decoder.cc:11257
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8563
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64
Definition: instructions.hh:3557
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16
Definition: instructions.hh:20833
gem5::VegaISA::Inst_VOP3__V_FRACT_F16
Definition: instructions.hh:27781
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32
Definition: instructions.hh:10395
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10153
gem5::VegaISA::Inst_SOPC__S_CMP_LG_I32
Definition: instructions.hh:3813
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10219
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32
Definition: instructions.hh:18759
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:5383
gem5::VegaISA::Inst_DS__DS_DEC_U64
Definition: instructions.hh:32755
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16
Definition: instructions.hh:17569
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64
Definition: instructions.hh:13047
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16
Definition: instructions.hh:17841
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16
Definition: instructions.hh:14509
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR3_B32
GPUStaticInst * decode_OPU_VOP3__V_OR3_B32(MachInst)
Definition: decoder.cc:6937
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8791
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8479
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:12475
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst)
Definition: decoder.cc:6715
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32
Definition: instructions.hh:19031
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:5041
gem5::VegaISA::Inst_VOP2__V_ADD_F32
Definition: instructions.hh:6177
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:11689
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SETVSKIP
GPUStaticInst * decode_OP_SOPC__S_SETVSKIP(MachInst)
Definition: decoder.cc:10813
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECZ
Definition: instructions.hh:4665
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ
Definition: instructions.hh:39597
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B64
GPUStaticInst * decode_OP_DS__DS_OR_B64(MachInst)
Definition: decoder.cc:7603
gem5::VegaISA::Inst_SOP2__S_LSHL_B32
Definition: instructions.hh:999
gem5::VegaISA::Inst_VOP3__V_QSAD_PK_U16_U8
Definition: instructions.hh:29279
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16
Definition: instructions.hh:20731
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_B64(MachInst)
Definition: decoder.cc:7621
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32
Definition: instructions.hh:15903
gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64
Definition: instructions.hh:3301
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U16
GPUStaticInst * decode_OP_VOP2__V_MIN_U16(MachInst)
Definition: decoder.cc:4141
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
Definition: instructions.hh:37613
gem5::VegaISA::Inst_VOP3__V_EXP_LEGACY_F32
Definition: instructions.hh:27877
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV(MachInst)
Definition: decoder.cc:10021
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16
Definition: instructions.hh:17467
gem5::VegaISA::Inst_SOPP__S_INCPERFLEVEL
Definition: instructions.hh:5025
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:11077
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:11935
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4
Definition: instructions.hh:5577
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFI_B32
GPUStaticInst * decode_OPU_VOP3__V_BFI_B32(MachInst)
Definition: decoder.cc:6601
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN_F16(MachInst)
Definition: decoder.cc:6067
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:9674
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst)
Definition: decoder.cc:6739
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL
Definition: instructions.hh:40569
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U32(MachInst)
Definition: decoder.cc:7351
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:11773
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_I64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_I64(MachInst)
Definition: decoder.cc:10519
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:12145
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9356
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U32
Definition: instructions.hh:34149
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:11563
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LERP_U8
GPUStaticInst * decode_OPU_VOP3__V_LERP_U8(MachInst)
Definition: decoder.cc:6619
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64
Definition: instructions.hh:23927
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B32
GPUStaticInst * decode_OP_DS__DS_XOR_B32(MachInst)
Definition: decoder.cc:7267
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_WREXEC_B64(MachInst)
Definition: decoder.cc:10699
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I32
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:5917
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U32
Definition: instructions.hh:4005
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
Definition: instructions.hh:5175
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND(MachInst)
Definition: decoder.cc:10285
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst)
Definition: decoder.cc:9494
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F32
GPUStaticInst * decode_OP_VOP1__V_SQRT_F32(MachInst)
Definition: decoder.cc:11269
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_B32(MachInst)
Definition: decoder.cc:7297
gem5::VegaISA::Decoder::subDecode_OPU_VOP3
GPUStaticInst * subDecode_OPU_VOP3(MachInst)
Definition: decoder.cc:3778
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I16_F16
Definition: instructions.hh:10075
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_I16(MachInst)
Definition: decoder.cc:12697
gem5::VegaISA::Inst_VOP3__V_MAX_I32
Definition: instructions.hh:24405
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64
Definition: instructions.hh:20493
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:5749
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64
Definition: instructions.hh:13625
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U64
GPUStaticInst * decode_OP_DS__DS_SUB_U64(MachInst)
Definition: decoder.cc:7549
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9470
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:11809
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_F16(MachInst)
Definition: decoder.cc:12805
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL
Definition: instructions.hh:39165
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16
Definition: instructions.hh:20935
gem5::VegaISA::Inst_VOP3__V_RNDNE_F64
Definition: instructions.hh:26377
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16
Definition: instructions.hh:14883
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9938
gem5::VegaISA::Inst_VOP3__V_FMA_F64
Definition: instructions.hh:28373
gem5::VegaISA::Inst_VOP1__V_RCP_IFLAG_F32
Definition: instructions.hh:9151
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8653
gem5::VegaISA::Inst_SOP2__S_BFE_I32
Definition: instructions.hh:1339
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16
Definition: instructions.hh:21105
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst)
Definition: decoder.cc:8731
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8839
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U64(MachInst)
Definition: decoder.cc:7717
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16_HI(MachInst)
Definition: decoder.cc:7705
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32
Definition: instructions.hh:15393
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16
Definition: instructions.hh:10973
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:11629
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F16
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F16(MachInst)
Definition: decoder.cc:6499
gem5::VegaISA::Inst_VOP3__V_MAX_F32
Definition: instructions.hh:24337
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:9668
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32
Definition: instructions.hh:12095
gem5::VegaISA::Inst_VOP3__V_LOG_F32
Definition: instructions.hh:26633
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B64
Definition: instructions.hh:33715
gem5::VegaISA::Inst_VOP3__V_SQRT_F64
Definition: instructions.hh:26857
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:9995
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8695
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U32
Definition: instructions.hh:31613
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U64(MachInst)
Definition: decoder.cc:10831
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F16
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F16(MachInst)
Definition: decoder.cc:6493
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst)
Definition: decoder.cc:7153
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_READLANE_B32
GPUStaticInst * decode_OPU_VOP3__V_READLANE_B32(MachInst)
Definition: decoder.cc:7069
gem5::VegaISA::Inst_VOP2__V_SUB_F16
Definition: instructions.hh:7249
gem5::VegaISA::Inst_VOP3__V_MAC_F16
Definition: instructions.hh:25103
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE
Definition: instructions.hh:41707
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8407
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2
Definition: instructions.hh:5361
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16
Definition: instructions.hh:18419
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9362
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT
Definition: instructions.hh:36395
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10273
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64
Definition: instructions.hh:13523
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U64
GPUStaticInst * decode_OP_DS__DS_INC_U64(MachInst)
Definition: decoder.cc:7561
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:4645
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9782
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32
Definition: instructions.hh:2759
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:5575
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I64(MachInst)
Definition: decoder.cc:12547
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16
Definition: instructions.hh:10531
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I16(MachInst)
Definition: decoder.cc:6955
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P2_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:11029
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B
Definition: instructions.hh:40533
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_U64(MachInst)
Definition: decoder.cc:7555
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16
Definition: instructions.hh:21003
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B32(MachInst)
Definition: decoder.cc:7423
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:35695
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F16
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F16(MachInst)
Definition: decoder.cc:6505
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32
Definition: instructions.hh:22635
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U16(MachInst)
Definition: decoder.cc:6883
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ICACHE_INV
GPUStaticInst * decode_OP_SOPP__S_ICACHE_INV(MachInst)
Definition: decoder.cc:10951
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:9980
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64
Definition: instructions.hh:16787
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:12691
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE
Definition: instructions.hh:36037
gem5::VegaISA::Inst_VOP3__V_LDEXP_F64
Definition: instructions.hh:30085
gem5::VegaISA::Inst_DS__DS_SUB_U64
Definition: instructions.hh:32659
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND
Definition: instructions.hh:42189
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9758
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I64
Definition: instructions.hh:33477
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_OFF
Definition: instructions.hh:5265
gem5::VegaISA::Inst_VOP3__V_OR_B32
Definition: instructions.hh:24643
gem5::VegaISA::Inst_VOP2__V_MUL_LEGACY_F32
Definition: instructions.hh:6279
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16
Definition: instructions.hh:17943
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:35809
gem5::VegaISA::Decoder::tableSubDecode_OP_SCRATCH
static IsaDecodeMethod tableSubDecode_OP_SCRATCH[128]
Definition: gpu_decoder.hh:71
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:6187
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_F32(MachInst)
Definition: decoder.cc:3877
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F32
GPUStaticInst * decode_OP_VOP2__V_SUB_F32(MachInst)
Definition: decoder.cc:3859
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP(MachInst)
Definition: decoder.cc:8743
gem5::VegaISA::Inst_DS__DS_CONDXCHG32_RTN_B64
Definition: instructions.hh:34055
gem5::VegaISA::Inst_VOP3__V_CUBESC_F32
Definition: instructions.hh:28121
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:5221
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F16
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F16(MachInst)
Definition: decoder.cc:6511
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F64
Definition: instructions.hh:33919
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:4651
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:12451
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:11575
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10603
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F32(MachInst)
Definition: decoder.cc:3865
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32
Definition: instructions.hh:11687
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBETC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBETC_F32(MachInst)
Definition: decoder.cc:6577
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_U16(MachInst)
Definition: decoder.cc:12763
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:11665
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:11695
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32
Definition: instructions.hh:22329
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_HI_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_HI_U8(MachInst)
Definition: decoder.cc:6697
gem5::VegaISA::Inst_SOP2__S_ORN2_B32
Definition: instructions.hh:727
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:4861
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
Definition: instructions.hh:37803
gem5::VegaISA::Inst_VOP1__V_COS_F32
Definition: instructions.hh:9375
gem5::VegaISA::Inst_VOP1__V_FRACT_F32
Definition: instructions.hh:8895
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32
Definition: instructions.hh:15189
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LL_F16
Definition: instructions.hh:29843
gem5::VegaISA::Inst_VOP2__V_OR_B32
Definition: instructions.hh:6823
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32
Definition: instructions.hh:14951
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8641
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8371
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst)
Definition: decoder.cc:8923
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:11383
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10351
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:6391
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:5785
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32
Definition: instructions.hh:19065
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:4717
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F64
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F64(MachInst)
Definition: decoder.cc:6337
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:5245
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B64(MachInst)
Definition: decoder.cc:7783
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:4879
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:5515
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE1
Definition: instructions.hh:8607
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32
Definition: instructions.hh:15495
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst)
Definition: decoder.cc:8761
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32
Definition: instructions.hh:19099
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U32
Definition: instructions.hh:31579
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_U32(MachInst)
Definition: decoder.cc:4159
gem5::VegaISA::Inst_VOP1__V_CVT_I16_F16
Definition: instructions.hh:9851
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst)
Definition: decoder.cc:9229
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U64(MachInst)
Definition: decoder.cc:8029
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32
Definition: instructions.hh:12231
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64
Definition: instructions.hh:13489
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32
Definition: instructions.hh:15971
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:37727
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U64(MachInst)
Definition: decoder.cc:12595
gem5::VegaISA::Inst_VOP2__V_MUL_F16
Definition: instructions.hh:7317
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE(MachInst)
Definition: decoder.cc:8461
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:10129
gem5::VegaISA::Inst_SOP2__S_NAND_B64
Definition: instructions.hh:829
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:5773
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B32
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B32(MachInst)
Definition: decoder.cc:7495
gem5::VegaISA::IsaDecodeMethod
GPUStaticInst *(Decoder::*)(MachInst) IsaDecodeMethod
Definition: gpu_decoder.hh:52
gem5::VegaISA::Inst_VOP3__V_PERM_B32
Definition: instructions.hh:29571
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst)
Definition: decoder.cc:6727
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32
Definition: instructions.hh:22363
gem5::VegaISA::Inst_VOP2__V_AND_B32
Definition: instructions.hh:6789
gem5::VegaISA::Inst_VOP3__V_TRUNC_F32
Definition: instructions.hh:26473
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B128
GPUStaticInst * decode_OP_DS__DS_WRITE_B128(MachInst)
Definition: decoder.cc:8107
gem5::VegaISA::Inst_SOP1__S_BREV_B32
Definition: instructions.hh:2439
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:12301
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F16
GPUStaticInst * decode_OP_VOP1__V_LOG_F16(MachInst)
Definition: decoder.cc:11407
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B64(MachInst)
Definition: decoder.cc:10459
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL
Definition: instructions.hh:40245
gem5::VegaISA::Inst_VOP3__V_CVT_I16_F16
Definition: instructions.hh:27397
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8515
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:6133
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9536
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B64
GPUStaticInst * decode_OP_DS__DS_AND_B64(MachInst)
Definition: decoder.cc:7597
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst)
Definition: decoder.cc:6721
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I16
GPUStaticInst * decode_OPU_VOP3__V_MED3_I16(MachInst)
Definition: decoder.cc:6895
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U16(MachInst)
Definition: decoder.cc:6835
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_I16(MachInst)
Definition: decoder.cc:12745
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_PCK
Definition: instructions.hh:38509
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:12031
gem5::VegaISA::Inst_VOP2__V_SUB_CO_U32
Definition: instructions.hh:7029
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:5527
gem5::VegaISA::Inst_VOP3__V_MIN_F64
Definition: instructions.hh:30017
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ASHRREV_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ASHRREV_I16(MachInst)
Definition: decoder.cc:12733
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:5509
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:12175
gem5::VegaISA::Inst_VOP3__V_CUBEID_F32
Definition: instructions.hh:28085
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst)
Definition: decoder.cc:6991
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10333
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8
GPUStaticInst * decode_OP_DS__DS_READ_U8(MachInst)
Definition: decoder.cc:7507
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U32(MachInst)
Definition: decoder.cc:7399
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U16
GPUStaticInst * decode_OPU_VOP3__V_MED3_U16(MachInst)
Definition: decoder.cc:6901
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10105
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:5419
gem5::VegaISA::InstFormat::iFmt_FLAT
InFmt_FLAT iFmt_FLAT
Definition: gpu_decoder.hh:1908
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2_B64(MachInst)
Definition: decoder.cc:7627
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS
Definition: instructions.hh:5115
gem5::VegaISA::Inst_VOP1__V_EXP_F32
Definition: instructions.hh:9055
gem5::VegaISA::InFmt_VOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1830
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B32
GPUStaticInst * decode_OP_SOP2__S_LSHL_B32(MachInst)
Definition: decoder.cc:4345
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F64
GPUStaticInst * decode_OPU_VOP3__V_ADD_F64(MachInst)
Definition: decoder.cc:7015
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F64
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F64(MachInst)
Definition: decoder.cc:6247
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10195
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I16
GPUStaticInst * decode_OP_VOP2__V_MAX_I16(MachInst)
Definition: decoder.cc:4135
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U64
Definition: instructions.hh:34881
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:5539
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10117
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:5731
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:35657
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_U16
GPUStaticInst * decode_OPU_VOP3__V_SUB_U16(MachInst)
Definition: decoder.cc:6025
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64
Definition: instructions.hh:23145
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F64
Definition: instructions.hh:33851
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8491
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MSAD_U8
GPUStaticInst * decode_OPU_VOP3__V_MSAD_U8(MachInst)
Definition: decoder.cc:6757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:5593
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:6985
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I32
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:3949
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:4657
gem5::VegaISA::InstFormat::iFmt_VOP3B
InFmt_VOP3B iFmt_VOP3B
Definition: gpu_decoder.hh:1929
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD_X2
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD_X2(MachInst)
Definition: decoder.cc:10075
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:5737
gem5::VegaISA::Inst_VOP1__V_FRACT_F16
Definition: instructions.hh:10235
gem5::VegaISA::Decoder::decode_OP_SOP1__S_RFE_B64
GPUStaticInst * decode_OP_SOP1__S_RFE_B64(MachInst)
Definition: decoder.cc:10579
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16
Definition: instructions.hh:14101
gem5::VegaISA::Inst_DS__DS_XOR_B32
Definition: instructions.hh:31117
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B64
Definition: instructions.hh:30459
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8689
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16
Definition: instructions.hh:11483
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F64
GPUStaticInst * decode_OPU_VOP3__V_FMA_F64(MachInst)
Definition: decoder.cc:6613
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER8H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER8H_PCK(MachInst)
Definition: decoder.cc:9097
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B32
Definition: instructions.hh:31953
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B64
Definition: instructions.hh:33817
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:5743
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B96
GPUStaticInst * decode_OP_DS__DS_READ_B96(MachInst)
Definition: decoder.cc:8113
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:11149
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_I32
Definition: instructions.hh:1671
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64
Definition: instructions.hh:23757
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B64
GPUStaticInst * decode_OP_SOP1__S_MOV_B64(MachInst)
Definition: decoder.cc:10399
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:5965
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:12577
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_I32
Definition: instructions.hh:1735
gem5::VegaISA::Inst_SOP2__S_SUBB_U32
Definition: instructions.hh:217
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_U32
Definition: instructions.hh:1895
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I64(MachInst)
Definition: decoder.cc:7747
gem5::VegaISA::Inst_VOP1__V_MOV_B32
Definition: instructions.hh:8063
gem5::VegaISA::Inst_SOP1__S_CMOV_B64
Definition: instructions.hh:2279
gem5::VegaISA::Inst_DS__DS_XOR_B64
Definition: instructions.hh:32979
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LO_U16
GPUStaticInst * decode_OP_VOP2__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:4093
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:11611
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:6973
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9283
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:11857
gem5::VegaISA::Inst_VOP2__V_XOR_B32
Definition: instructions.hh:6857
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B64
Definition: instructions.hh:30425
gem5::VegaISA::Decoder::decode_OP_VOP2__V_CNDMASK_B32
GPUStaticInst * decode_OP_VOP2__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:3847
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:6307
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX_F16(MachInst)
Definition: decoder.cc:6061
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B32
Definition: instructions.hh:31987
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX_U32(MachInst)
Definition: decoder.cc:5905
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_U32
GPUStaticInst * decode_OP_VOP1__V_FFBH_U32(MachInst)
Definition: decoder.cc:11305
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:6145
gem5::VegaISA::Inst_SOP2__S_MIN_I32
Definition: instructions.hh:251
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B64
GPUStaticInst * decode_OP_SOP2__S_XNOR_B64(MachInst)
Definition: decoder.cc:4339
gem5::VegaISA::Inst_VOP1__V_EXP_LEGACY_F32
Definition: instructions.hh:10331
gem5::VegaISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1778
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F32(MachInst)
Definition: decoder.cc:7939
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst)
Definition: decoder.cc:8989
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:12223
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9878
gem5::VegaISA::Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10585
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:11425
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst)
Definition: decoder.cc:9542
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:11329
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L_O
Definition: instructions.hh:40713
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:4687
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CLREXCP
GPUStaticInst * decode_OP_VOP1__V_CLREXCP(MachInst)
Definition: decoder.cc:11353
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:4957
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32_U24
Definition: instructions.hh:24269
gem5::VegaISA::Inst_SOPK__S_SETREG_B32
Definition: instructions.hh:2119
gem5::VegaISA::Inst_SOPP__S_ENDPGM
Definition: instructions.hh:4451
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_I32
GPUStaticInst * decode_OP_SOP2__S_MAX_I32(MachInst)
Definition: decoder.cc:4225
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I32
GPUStaticInst * decode_OPU_VOP3__V_MED3_I32(MachInst)
Definition: decoder.cc:6679
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32
Definition: instructions.hh:15665
gem5::VegaISA::Inst_VOP3__V_RSQ_F32
Definition: instructions.hh:26729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:5137
gem5::VegaISA::InFmt_FLAT::SEG
unsigned int SEG
Definition: gpu_decoder.hh:1638
gem5::VegaISA::Inst_VOP3__V_RCP_F32
Definition: instructions.hh:26665
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16
Definition: instructions.hh:14271
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:11797
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16
Definition: instructions.hh:21683
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:12679
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD(MachInst)
Definition: decoder.cc:8701
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:12613
gem5::VegaISA::Inst_VOP3__V_MAX_F64
Definition: instructions.hh:30051
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst)
Definition: decoder.cc:8707
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10693
gem5::VegaISA::Inst_SOP2__S_ANDN2_B32
Definition: instructions.hh:659
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32(MachInst)
Definition: decoder.cc:7057
gem5::VegaISA::Inst_SOP2__S_XNOR_B32
Definition: instructions.hh:931
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64
Definition: instructions.hh:20051
gem5::VegaISA::Inst_SOPP__S_ICACHE_INV
Definition: instructions.hh:4995
gem5::VegaISA::InstFormat::iFmt_VOP2
InFmt_VOP2 iFmt_VOP2
Definition: gpu_decoder.hh:1926
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst)
Definition: decoder.cc:9458
gem5::VegaISA::Decoder::decode_OP_DS__DS_APPEND
GPUStaticInst * decode_OP_DS__DS_APPEND(MachInst)
Definition: decoder.cc:7999
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U64
Definition: instructions.hh:33545
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F32
GPUStaticInst * decode_OP_VOP1__V_COS_F32(MachInst)
Definition: decoder.cc:11287
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64
Definition: instructions.hh:20221
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst)
Definition: decoder.cc:8869
gem5::VegaISA::Inst_VOP3__V_INTERP_MOV_F32
Definition: instructions.hh:29809
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10375
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:12091
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F32
GPUStaticInst * decode_OPU_VOP3__V_FMA_F32(MachInst)
Definition: decoder.cc:6607
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F32
GPUStaticInst * decode_OP_VOP2__V_MADAK_F32(MachInst)
Definition: decoder.cc:3991
gem5::VegaISA::Inst_VOP1__V_FLOOR_F16
Definition: instructions.hh:10107
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16
Definition: instructions.hh:14169
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst)
Definition: decoder.cc:7147
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst)
Definition: decoder.cc:8959
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I16
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:6055
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADDC_U32
GPUStaticInst * decode_OP_SOP2__S_ADDC_U32(MachInst)
Definition: decoder.cc:4201
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B64
Definition: instructions.hh:33681
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
Definition: instructions.hh:41361
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64
Definition: instructions.hh:23485
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64
Definition: instructions.hh:13115
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PACK_B32_F16
GPUStaticInst * decode_OPU_VOP3__V_PACK_B32_F16(MachInst)
Definition: decoder.cc:7195
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:5629
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4
Definition: instructions.hh:36311
gem5::VegaISA::Inst_SOP2__S_CBRANCH_G_FORK
Definition: instructions.hh:1441
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX_U16(MachInst)
Definition: decoder.cc:6073
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B32(MachInst)
Definition: decoder.cc:7411
gem5::VegaISA::Inst_VOP3__V_SUB_U16
Definition: instructions.hh:25171
gem5::VegaISA::Inst_VOP2__V_MIN_U32
Definition: instructions.hh:6619
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:12637
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8233
gem5::VegaISA::Inst_SOP1__S_BITSET0_B64
Definition: instructions.hh:2983
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:12013
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32
Definition: instructions.hh:12571
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:5083
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6763
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8773
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_LEGACY_F16(MachInst)
Definition: decoder.cc:6817
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:9656
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:11065
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9908
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U16(MachInst)
Definition: decoder.cc:4087
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10237
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I16
Definition: instructions.hh:7661
gem5::VegaISA::Inst_VOP3__V_CVT_OFF_F32_I4
Definition: instructions.hh:26025
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1(MachInst)
Definition: decoder.cc:9548
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8785
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8215
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_OR_B32(MachInst)
Definition: decoder.cc:5935
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:5395
gem5::VegaISA::Inst_SMEM__S_STORE_DWORD
Definition: instructions.hh:5685
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBL_B32
GPUStaticInst * decode_OPU_VOP3__V_FFBL_B32(MachInst)
Definition: decoder.cc:6373
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:5269
gem5::VegaISA::Inst_VOP3__V_SUB_CO_U32
Definition: instructions.hh:24781
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_B32(MachInst)
Definition: decoder.cc:5929
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:5761
gem5::VegaISA::Inst_VOP1__V_CVT_FLR_I32_F32
Definition: instructions.hh:8447
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L
Definition: instructions.hh:40281
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND_X2
Definition: instructions.hh:37433
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:5689
gem5::VegaISA::Inst_DS__DS_AND_B32
Definition: instructions.hh:31053
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4
Definition: instructions.hh:5865
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I16
GPUStaticInst * decode_OPU_VOP3__V_ADD_I16(MachInst)
Definition: decoder.cc:7183
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8827
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16
Definition: instructions.hh:21411
gem5::VegaISA::Inst_SOPP__S_BARRIER
Definition: instructions.hh:4725
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64
Definition: instructions.hh:16209
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U32
GPUStaticInst * decode_OP_SOP2__S_BFE_U32(MachInst)
Definition: decoder.cc:4399
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B64(MachInst)
Definition: decoder.cc:8071
gem5::VegaISA::Decoder::decode_invalid
GPUStaticInst * decode_invalid(MachInst)
Definition: decoder.cc:12829
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_I32(MachInst)
Definition: decoder.cc:4507
gem5::VegaISA::InFmt_VOP3P
Definition: gpu_decoder.hh:1885
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B64
GPUStaticInst * decode_OP_SOP1__S_BREV_B64(MachInst)
Definition: decoder.cc:10447
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32
Definition: instructions.hh:2631
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C(MachInst)
Definition: decoder.cc:9079
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:12457
gem5::VegaISA::Inst_VOP1__V_CVT_F32_I32
Definition: instructions.hh:8191
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U16
GPUStaticInst * decode_OPU_VOP3__V_SAD_U16(MachInst)
Definition: decoder.cc:6703
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:11557
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_I32(MachInst)
Definition: decoder.cc:10741
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:11845
gem5::VegaISA::Inst_VOP3__V_MSAD_U8
Definition: instructions.hh:29243
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:12181
gem5::VegaISA::Inst_SOPP__S_ENDPGM_SAVED
Definition: instructions.hh:5235
gem5::VegaISA::Decoder::subDecode_OP_MTBUF
GPUStaticInst * subDecode_OP_MTBUF(MachInst)
Definition: decoder.cc:3831
gem5::VegaISA::Inst_VOP1__V_NOT_B32
Definition: instructions.hh:9407
gem5::VegaISA::Decoder::decode_OP_DS__DS_SWIZZLE_B32
GPUStaticInst * decode_OP_DS__DS_SWIZZLE_B32(MachInst)
Definition: decoder.cc:7525
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_B32(MachInst)
Definition: decoder.cc:7279
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Definition: instructions.hh:42429
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32
Definition: instructions.hh:18997
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMAX
Definition: instructions.hh:38853
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Definition: instructions.hh:42465
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:11539
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ_O
Definition: instructions.hh:40821
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_F32(MachInst)
Definition: decoder.cc:11239
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U32(MachInst)
Definition: decoder.cc:7045
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:12229
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F16
GPUStaticInst * decode_OPU_VOP3__V_SIN_F16(MachInst)
Definition: decoder.cc:6517
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXLO_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXLO_F16(MachInst)
Definition: decoder.cc:12817
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:12139
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ
Definition: instructions.hh:40389
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64
Definition: instructions.hh:13421
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16
Definition: instructions.hh:20969
gem5::VegaISA::Inst_VOP3__V_CVT_F32_I32
Definition: instructions.hh:25737
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:9704
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F32(MachInst)
Definition: decoder.cc:7933
gem5::VegaISA::Inst_SOP1__S_MOV_B32
Definition: instructions.hh:2183
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMIN
Definition: instructions.hh:38785
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:9962
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32
Definition: instructions.hh:15801
gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64
Definition: instructions.hh:3205
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U64
Definition: instructions.hh:34851
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F16
GPUStaticInst * decode_OP_VOP2__V_MAC_F16(MachInst)
Definition: decoder.cc:4057
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_I32(MachInst)
Definition: decoder.cc:4447
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16
Definition: instructions.hh:14067
gem5::VegaISA::Inst_VOP1__V_TRUNC_F32
Definition: instructions.hh:8927
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:5029
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst)
Definition: decoder.cc:9031
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSG
GPUStaticInst * decode_OP_SOPP__S_SENDMSG(MachInst)
Definition: decoder.cc:10933
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9896
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst)
Definition: decoder.cc:8977
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_ADD
Definition: instructions.hh:38683
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRAP_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRAP_RTN_B32(MachInst)
Definition: decoder.cc:7471
gem5::VegaISA::Inst_SOPC__S_SET_GPR_IDX_ON
Definition: instructions.hh:4325
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9313
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U64_U32
GPUStaticInst * decode_OPU_VOP3__V_MAD_U64_U32(MachInst)
Definition: decoder.cc:6781
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9860
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64
Definition: instructions.hh:16685
gem5::VegaISA::Decoder::tableSubDecode_OP_MUBUF
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128]
Definition: gpu_decoder.hh:70
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst)
Definition: decoder.cc:8983
gem5::VegaISA::Inst_VOP3__V_CVT_PKRTZ_F16_F32
Definition: instructions.hh:30663
gem5::VegaISA::Inst_VOP2__V_MIN_U16
Definition: instructions.hh:7831
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:5425
gem5::VegaISA::Decoder::decode_OP_VOP1__V_BFREV_B32
GPUStaticInst * decode_OP_VOP1__V_BFREV_B32(MachInst)
Definition: decoder.cc:11299
gem5::VegaISA::Inst_VOP3__V_MAX3_U32
Definition: instructions.hh:28697
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16
Definition: instructions.hh:10803
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B32
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B32(MachInst)
Definition: decoder.cc:4237
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:6205
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32
Definition: instructions.hh:14985
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN_F32(MachInst)
Definition: decoder.cc:5875
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64
Definition: instructions.hh:13285
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8419
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8269
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16
Definition: instructions.hh:13965
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst)
Definition: decoder.cc:9013
gem5::VegaISA::Inst_DS__DS_OR_B64
Definition: instructions.hh:32947
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:11059
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst)
Definition: decoder.cc:8821
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B32(MachInst)
Definition: decoder.cc:7927
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:11647
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK
Definition: instructions.hh:38365
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:9914
gem5::VegaISA::Inst_VOP3__V_ADD_F32
Definition: instructions.hh:23997
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3
Definition: instructions.hh:41639
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2
Definition: instructions.hh:42737
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U32(MachInst)
Definition: decoder.cc:7855
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:11623
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F16
GPUStaticInst * decode_OP_VOP1__V_EXP_F16(MachInst)
Definition: decoder.cc:11413
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:11953
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:5059
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I64
GPUStaticInst * decode_OP_SOP2__S_ASHR_I64(MachInst)
Definition: decoder.cc:4375
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:9560
gem5::VegaISA::Decoder::subDecode_OP_FLAT
GPUStaticInst * subDecode_OP_FLAT(MachInst)
Definition: decoder.cc:3802
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:11089
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32
Definition: instructions.hh:11721
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F32
GPUStaticInst * decode_OP_VOP1__V_CEIL_F32(MachInst)
Definition: decoder.cc:11209
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:9710
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8497
gem5::VegaISA::Inst_VOP3__V_MAD_F32
Definition: instructions.hh:27977
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16
Definition: instructions.hh:10701
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOT_B32
GPUStaticInst * decode_OP_VOP1__V_NOT_B32(MachInst)
Definition: decoder.cc:11293
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U64
Definition: instructions.hh:4389
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B64
GPUStaticInst * decode_OP_SOP2__S_ORN2_B64(MachInst)
Definition: decoder.cc:4303
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F32
Definition: instructions.hh:29169
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32
Definition: instructions.hh:12367
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:5923
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H(MachInst)
Definition: decoder.cc:9049
gem5::VegaISA::Inst_VOP3__V_MAD_LEGACY_F32
Definition: instructions.hh:27941
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst)
Definition: decoder.cc:9085
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL1_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL1_ADD_U32(MachInst)
Definition: decoder.cc:4453
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:4993
gem5::VegaISA::InstFormat::iFmt_DS
InFmt_DS iFmt_DS
Definition: gpu_decoder.hh:1904
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U32(MachInst)
Definition: decoder.cc:7363
gem5::VegaISA::Inst_VOP2__V_ADD_U16
Definition: instructions.hh:7457
gem5::VegaISA::Inst_VOP2__V_MUL_HI_U32_U24
Definition: instructions.hh:6449
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:6049
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B64
GPUStaticInst * decode_OP_SOP2__S_NAND_B64(MachInst)
Definition: decoder.cc:4315
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:12325
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32
Definition: instructions.hh:15631
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_U32(MachInst)
Definition: decoder.cc:4165
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B64
Definition: instructions.hh:35151
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F64
Definition: instructions.hh:29207
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9331
gem5::VegaISA::Inst_VOP3__V_SAD_U32
Definition: instructions.hh:28949
gem5::VegaISA::Inst_VOP3__V_MAX3_I32
Definition: instructions.hh:28661
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32
Definition: instructions.hh:15767
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10010
gem5::VegaISA::Decoder::subDecode_OP_MUBUF
GPUStaticInst * subDecode_OP_MUBUF(MachInst)
Definition: decoder.cc:3823
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:5011
gem5::VegaISA::Inst_VOP3__V_SAD_HI_U8
Definition: instructions.hh:28877
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16
Definition: instructions.hh:17875
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_O
Definition: instructions.hh:39993
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_U16
GPUStaticInst * decode_OPU_VOP3__V_ADD_U16(MachInst)
Definition: decoder.cc:6019
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U16
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:6037
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:12445
gem5::VegaISA::Inst_VOP2__V_ADDC_CO_U32
Definition: instructions.hh:7101
gem5::VegaISA::Inst_VOP3__V_MAX3_F32
Definition: instructions.hh:28625
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16
Definition: instructions.hh:11075
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32(MachInst)
Definition: decoder.cc:10513
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B32(MachInst)
Definition: decoder.cc:7921
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16
GPUStaticInst * decode_OP_DS__DS_READ_U16(MachInst)
Definition: decoder.cc:7519
gem5::VegaISA::Inst_VOP3__V_COS_F32
Definition: instructions.hh:26921
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL
Definition: instructions.hh:39273
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:5227
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16
Definition: instructions.hh:11347
gem5::VegaISA::Inst_VOP3__V_ADDC_CO_U32
Definition: instructions.hh:24853
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:11605
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_USHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_USHORT(MachInst)
Definition: decoder.cc:9728
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32
GPUStaticInst * decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32(MachInst)
Definition: decoder.cc:11359
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9253
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TTRACEDATA
GPUStaticInst * decode_OP_SOPP__S_TTRACEDATA(MachInst)
Definition: decoder.cc:10969
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:9626
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:6535
gem5::VegaISA::Inst_DS__DS_RSUB_U64
Definition: instructions.hh:32691
gem5::VegaISA::InFmt_VOP3A::OP
unsigned int OP
Definition: gpu_decoder.hh:1807
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:11107
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:11905
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16
Definition: instructions.hh:14611
gem5::VegaISA::Inst_VOP3__V_SUB_F16
Definition: instructions.hh:25001
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8551
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64
Definition: instructions.hh:23043
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_O
Definition: instructions.hh:39705
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B32(MachInst)
Definition: decoder.cc:10795
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16
Definition: instructions.hh:18249
gem5::VegaISA::Inst_VOP3__V_WRITELANE_B32
Definition: instructions.hh:30289
gem5::VegaISA::Inst_VOP2__V_MAX_U16
Definition: instructions.hh:7763
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:5131
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:5203
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64
Definition: instructions.hh:19609
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL4_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL4_ADD_U32(MachInst)
Definition: decoder.cc:4471
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64
Definition: instructions.hh:13013
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst)
Definition: decoder.cc:8305
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE3
Definition: instructions.hh:8671
gem5::VegaISA::Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32
GPUStaticInst * decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst)
Definition: decoder.cc:11053
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F64
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F64(MachInst)
Definition: decoder.cc:6235
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64
Definition: instructions.hh:13693
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst)
Definition: decoder.cc:9133
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:5371
gem5::VegaISA::InFmt_MTBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1687
gpu_decoder.hh
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_OR
Definition: instructions.hh:38921
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:11323
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16
Definition: instructions.hh:11415
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:35847
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64
Definition: instructions.hh:22873
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F16
GPUStaticInst * decode_OP_VOP2__V_MIN_F16(MachInst)
Definition: decoder.cc:4123
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8527
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:11827
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:6439
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:4813
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10309
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B64
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B64(MachInst)
Definition: decoder.cc:10639
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64
Definition: instructions.hh:16923
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
Definition: instructions.hh:37217
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:5797
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:10135
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F64
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F64(MachInst)
Definition: decoder.cc:11185
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64
Definition: instructions.hh:13183
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:11155
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBL_B32
GPUStaticInst * decode_OP_VOP1__V_FFBL_B32(MachInst)
Definition: decoder.cc:11311
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U64
Definition: instructions.hh:33341
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:4927
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16
Definition: instructions.hh:20901
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:4771
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8623
gem5::VegaISA::Decoder::tableSubDecode_OP_MTBUF
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16]
Definition: gpu_decoder.hh:69
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I32
GPUStaticInst * decode_OP_VOP2__V_MIN_I32(MachInst)
Definition: decoder.cc:3919
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16
Definition: instructions.hh:14135
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_I32(MachInst)
Definition: decoder.cc:10735
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32
Definition: instructions.hh:18793
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32
Definition: instructions.hh:22601
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16
Definition: instructions.hh:17637
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_I32
Definition: instructions.hh:1703
gem5::VegaISA::Inst_SOP1__S_CBRANCH_JOIN
Definition: instructions.hh:3653
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst)
Definition: decoder.cc:11005
gem5::VegaISA::Inst_VOP3__V_SUBREV_U16
Definition: instructions.hh:25205
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:11653
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U32(MachInst)
Definition: decoder.cc:7873
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:5155
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32
Definition: instructions.hh:18963
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32
Definition: instructions.hh:21819
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:9608
gem5::VegaISA::Inst_VOP3__V_EXP_F32
Definition: instructions.hh:26601
gem5::VegaISA::Inst_VOP1__V_CVT_F16_U16
Definition: instructions.hh:9755
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst)
Definition: decoder.cc:8149
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16
Definition: instructions.hh:20799
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F32
GPUStaticInst * decode_OPU_VOP3__V_MAC_F32(MachInst)
Definition: decoder.cc:5947
gem5::VegaISA::Inst_DS__DS_OR_B32
Definition: instructions.hh:31085
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F16
Definition: instructions.hh:27589
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECNZ
Definition: instructions.hh:4695
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32
Definition: instructions.hh:18555
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F16
GPUStaticInst * decode_OP_VOP1__V_COS_F16(MachInst)
Definition: decoder.cc:11467
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:5359
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U32
Definition: instructions.hh:34119
gem5::VegaISA::Inst_SOP1__S_CMOV_B32
Definition: instructions.hh:2247
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64
Definition: instructions.hh:23315
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B64
Definition: instructions.hh:35181
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16
Definition: instructions.hh:17535
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16
Definition: instructions.hh:14849
gem5::VegaISA::Inst_VOP3__V_MUL_F16
Definition: instructions.hh:25069
gem5::VegaISA::Decoder::decode_OP_SOPK__S_ADDK_I32
GPUStaticInst * decode_OP_SOPK__S_ADDK_I32(MachInst)
Definition: decoder.cc:4579
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8779
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32
Definition: instructions.hh:12435
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9374
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst)
Definition: decoder.cc:9025
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16
Definition: instructions.hh:5469
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:35733
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:12097
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B64(MachInst)
Definition: decoder.cc:10471
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8467
gem5::VegaISA::Inst_VOP3__V_MAD_U32_U24
Definition: instructions.hh:28049
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_BR
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_BR(MachInst)
Definition: decoder.cc:7969
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32
Definition: instructions.hh:19575
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst)
Definition: decoder.cc:9175
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32
Definition: instructions.hh:15019
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:5851
gem5::VegaISA::Inst_SOP1__S_SET_GPR_IDX_IDX
Definition: instructions.hh:3749
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LV_F16
Definition: instructions.hh:29877
gem5::VegaISA::Inst_VOP3__V_CVT_F16_U16
Definition: instructions.hh:27301
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9806
gem5::VegaISA::Inst_VOP3__V_AND_B32
Definition: instructions.hh:24609
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10015
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U32(MachInst)
Definition: decoder.cc:4171
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32
Definition: instructions.hh:15699
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F64
Definition: instructions.hh:8511
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:4921
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F64(MachInst)
Definition: decoder.cc:7819
gem5::VegaISA::Inst_VOP3__V_MOV_B32
Definition: instructions.hh:25641
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64
Definition: instructions.hh:19881
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:5275
gem5::VegaISA::Inst_VOP2__V_MIN_I32
Definition: instructions.hh:6551
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64
Definition: instructions.hh:23825
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64
Definition: instructions.hh:20527
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:4807
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:11917
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32
Definition: instructions.hh:11755
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:5545
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:11641
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_I32(MachInst)
Definition: decoder.cc:10723
gem5::VegaISA::Inst_VOP3__V_CUBEMA_F32
Definition: instructions.hh:28193
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16(MachInst)
Definition: decoder.cc:6823
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst)
Definition: decoder.cc:8935
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_U16(MachInst)
Definition: decoder.cc:12775
gem5::VegaISA::Decoder::subDecode_OP_VINTRP
GPUStaticInst * subDecode_OP_VINTRP(MachInst)
Definition: decoder.cc:3786
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32
Definition: instructions.hh:22567
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:11713
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16
Definition: instructions.hh:21173
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F64
Definition: instructions.hh:26057
gem5::VegaISA::Inst_VOP2__V_MIN_F32
Definition: instructions.hh:6483
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32
Definition: instructions.hh:11925
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR
Definition: instructions.hh:42223
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:5983
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F16(MachInst)
Definition: decoder.cc:6871
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:4747
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32
Definition: instructions.hh:2567
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_F16(MachInst)
Definition: decoder.cc:6943
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:11803
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL_O
Definition: instructions.hh:40785
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Definition: instructions.hh:42499
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B64
GPUStaticInst * decode_OP_DS__DS_READ2_B64(MachInst)
Definition: decoder.cc:7837
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst)
Definition: decoder.cc:9247
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U64
Definition: instructions.hh:35091
instructions.hh
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:4021
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8299
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16
Definition: instructions.hh:21581
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:4939
gem5::VegaISA::Inst_VOP3__V_TRIG_PREOP_F64
Definition: instructions.hh:30527
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32
Definition: instructions.hh:22091
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32
Definition: instructions.hh:17229
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:11527
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD
Definition: instructions.hh:36197
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:11635
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON
GPUStaticInst * decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst)
Definition: decoder.cc:10819
gem5::VegaISA::Inst_SOPC__S_CMP_LE_I32
Definition: instructions.hh:3941
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32
Definition: instructions.hh:15733
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F32(MachInst)
Definition: decoder.cc:11785
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16
Definition: instructions.hh:21071
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL_O
Definition: instructions.hh:39957
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10249
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITREPLICATE_B64_B32
GPUStaticInst * decode_OP_SOP1__S_BITREPLICATE_B64_B32(MachInst)
Definition: decoder.cc:10711
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:12589
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U64
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U64(MachInst)
Definition: decoder.cc:7711
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X
Definition: instructions.hh:35429
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F16
GPUStaticInst * decode_OP_VOP1__V_RSQ_F16(MachInst)
Definition: decoder.cc:11401
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_I32(MachInst)
Definition: decoder.cc:10729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F64(MachInst)
Definition: decoder.cc:5089
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B32
Definition: instructions.hh:24507
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ_O
Definition: instructions.hh:41037
gem5::VegaISA::Decoder::decode_OP_SOP2__S_HH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_HH_B32_B16(MachInst)
Definition: decoder.cc:4489
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst)
Definition: decoder.cc:7087
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F16
GPUStaticInst * decode_OP_VOP2__V_ADD_F16(MachInst)
Definition: decoder.cc:4033
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_I32(MachInst)
Definition: decoder.cc:4513
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64
Definition: instructions.hh:19983
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U32(MachInst)
Definition: decoder.cc:7879
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F16(MachInst)
Definition: decoder.cc:4711
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F64(MachInst)
Definition: decoder.cc:11929
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT
Definition: instructions.hh:41741
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32_I24
Definition: instructions.hh:24201
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:11137
gem5::VegaISA::Inst_VOP3__V_XOR_B32
Definition: instructions.hh:24677
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst)
Definition: decoder.cc:8719
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16
Definition: instructions.hh:21241
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64
Definition: instructions.hh:20289
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U64(MachInst)
Definition: decoder.cc:7735
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL_O
Definition: instructions.hh:39669
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC_X2
Definition: instructions.hh:37541
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:11989
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16
Definition: instructions.hh:10769
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETKILL
GPUStaticInst * decode_OP_SOPP__S_SETKILL(MachInst)
Definition: decoder.cc:10903
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOT_B32
GPUStaticInst * decode_OPU_VOP3__V_NOT_B32(MachInst)
Definition: decoder.cc:6355
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:4789
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64
Definition: instructions.hh:13081
gem5::VegaISA::Inst_DS__DS_ADD_F32
Definition: instructions.hh:31445
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64
Definition: instructions.hh:23553
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B32
Definition: instructions.hh:24575
gem5::VegaISA::Inst_SOP1__S_WQM_B64
Definition: instructions.hh:2407
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64
Definition: instructions.hh:20425
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:12565
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB
Definition: instructions.hh:42019
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2
Definition: instructions.hh:36235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U32
GPUStaticInst * decode_OPU_VOP3__V_MED3_U32(MachInst)
Definition: decoder.cc:6685
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8389
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B32
Definition: instructions.hh:4197
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16
Definition: instructions.hh:17977
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8239
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16
Definition: instructions.hh:17433
gem5::VegaISA::InstFormat::iFmt_SOPC
InFmt_SOPC iFmt_SOPC
Definition: gpu_decoder.hh:1921
gem5::VegaISA::Inst_SOPC__S_CMP_LE_U32
Definition: instructions.hh:4133
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFM_B32
GPUStaticInst * decode_OPU_VOP3__V_BFM_B32(MachInst)
Definition: decoder.cc:7123
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:5023
gem5::VegaISA::Inst_DS__DS_INC_RTN_U32
Definition: instructions.hh:31647
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32
Definition: instructions.hh:12605
gem5::VegaISA::Inst_SOPP__S_SETPRIO
Definition: instructions.hh:4875
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_I32
GPUStaticInst * decode_OP_SOP2__S_ADD_I32(MachInst)
Definition: decoder.cc:4189
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16
Definition: instructions.hh:14407
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_I32(MachInst)
Definition: decoder.cc:4525
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBESC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBESC_F32(MachInst)
Definition: decoder.cc:6571
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:6433
gem5::VegaISA::Inst_VOP2__V_SUBREV_U16
Definition: instructions.hh:7525
gem5::VegaISA::Inst_VOP3__V_MBCNT_HI_U32_B32
Definition: instructions.hh:30391
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:5299
gem5::VegaISA::Inst_VOP2__V_MIN_I16
Definition: instructions.hh:7865
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8671
gem5::VegaISA::Inst_VOP3__V_BCNT_U32_B32
Definition: instructions.hh:30323
gem5::VegaISA::Decoder::decode_OP_SOPP__S_NOP
GPUStaticInst * decode_OP_SOPP__S_NOP(MachInst)
Definition: decoder.cc:10837
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64
Definition: instructions.hh:13591
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16
Definition: instructions.hh:18045
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:12517
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32
Definition: instructions.hh:19235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I16
GPUStaticInst * decode_OPU_VOP3__V_SUB_I16(MachInst)
Definition: decoder.cc:7189
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:5113
gem5::VegaISA::Decoder::tableSubDecode_OP_VOPC
static IsaDecodeMethod tableSubDecode_OP_VOPC[256]
Definition: gpu_decoder.hh:78
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16
Definition: instructions.hh:11143
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16
Definition: instructions.hh:20697
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
Definition: instructions.hh:37289
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:6217
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:12235
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_I32
GPUStaticInst * decode_OP_SOP2__S_SUB_I32(MachInst)
Definition: decoder.cc:4195
gem5::VegaISA::Inst_VOP1__V_FLOOR_F64
Definition: instructions.hh:8863
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:9788
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F32
Definition: instructions.hh:32123
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9392
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:5863
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9368
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16
Definition: instructions.hh:21309
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I16(MachInst)
Definition: decoder.cc:12121
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U16(MachInst)
Definition: decoder.cc:6865
gem5::VegaISA::Inst_VOP3__V_FRACT_F64
Definition: instructions.hh:27177
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:5335
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I16
Definition: instructions.hh:25341
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:12307
gem5::VegaISA::Inst_VOP2__V_MIN_F16
Definition: instructions.hh:7729
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst)
Definition: decoder.cc:9235
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B
Definition: instructions.hh:40317
gem5::VegaISA::Inst_SOP1__S_ABS_I32
Definition: instructions.hh:3685
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B32
Definition: instructions.hh:6687
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:4729
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B32
Definition: instructions.hh:32089
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:12109
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:12295
gem5::VegaISA::Inst_DS__DS_READ_B32
Definition: instructions.hh:32293
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:35505
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst)
Definition: decoder.cc:7789
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:11767
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8677
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32
Definition: instructions.hh:12741
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:3901
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:5791
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32
Definition: instructions.hh:22669
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32
Definition: instructions.hh:21853
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_I16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:11371
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32
Definition: instructions.hh:2503
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F32
GPUStaticInst * decode_OP_VOP2__V_MIN_F32(MachInst)
Definition: decoder.cc:3907
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16
Definition: instructions.hh:17365
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:11941
gem5::VegaISA::Inst_VOP3__V_NOT_B32
Definition: instructions.hh:26953
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64
Definition: instructions.hh:2599
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32
Definition: instructions.hh:2823
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:5641
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B64
GPUStaticInst * decode_OP_SOP2__S_AND_B64(MachInst)
Definition: decoder.cc:4255
gem5::VegaISA::Inst_VOP3__V_SUBREV_F16
Definition: instructions.hh:25035
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8131
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst)
Definition: decoder.cc:9205
gem5::VegaISA::Inst_DS__DS_ADD_U32
Definition: instructions.hh:30765
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6769
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F64
Definition: instructions.hh:27113
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC
Definition: instructions.hh:37109
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND(MachInst)
Definition: decoder.cc:8593
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32
Definition: instructions.hh:18589
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32
Definition: instructions.hh:6755
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I24(MachInst)
Definition: decoder.cc:6553
gem5::VegaISA::Inst_SOP1__S_SETPC_B64
Definition: instructions.hh:3109
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMOVK_I32
GPUStaticInst * decode_OP_SOPK__S_CMOVK_I32(MachInst)
Definition: decoder.cc:4501
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_F32(MachInst)
Definition: decoder.cc:11233
gem5::VegaISA::Inst_VOP2__V_ADD_F16
Definition: instructions.hh:7215
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64
Definition: instructions.hh:13795
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8341
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_F32(MachInst)
Definition: decoder.cc:6289
gem5::VegaISA::Inst_VOP1__V_EXP_F16
Definition: instructions.hh:10011
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B32(MachInst)
Definition: decoder.cc:7915
gem5::VegaISA::Inst_VOP2__V_MADMK_F32
Definition: instructions.hh:6925
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP
Definition: instructions.hh:41947
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Definition: instructions.hh:42567
gem5::VegaISA::Inst_SOPP__S_NOP
Definition: instructions.hh:4421
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:6175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:12469
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9716
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst)
Definition: decoder.cc:8893
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U64(MachInst)
Definition: decoder.cc:8011
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F16(MachInst)
Definition: decoder.cc:4705
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B32(MachInst)
Definition: decoder.cc:10537
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9440
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_PCK(MachInst)
Definition: decoder.cc:8749
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_F32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_F32(MachInst)
Definition: decoder.cc:7477
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB_VOL
Definition: instructions.hh:5985
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADDC_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:5971
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16
Definition: instructions.hh:18385
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:12421
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8
Definition: instructions.hh:5433
gem5::VegaISA::Inst_VOP2__V_LDEXP_F16
Definition: instructions.hh:7899
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:12415
gem5::VegaISA::InstFormat::iFmt_SOP2
InFmt_SOP2 iFmt_SOP2
Definition: gpu_decoder.hh:1920
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:12283
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I64(MachInst)
Definition: decoder.cc:5623
gem5::VegaISA::Inst_DS__DS_AND_RTN_B32
Definition: instructions.hh:31851
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32
Definition: instructions.hh:19439
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10369
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B32
GPUStaticInst * decode_OP_SOP2__S_NOR_B32(MachInst)
Definition: decoder.cc:4321
gem5::VegaISA::Decoder::tableSubDecode_OP_FLAT
static IsaDecodeMethod tableSubDecode_OP_FLAT[128]
Definition: gpu_decoder.hh:66
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_I32(MachInst)
Definition: decoder.cc:10717
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:12019
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL
Definition: instructions.hh:39453
gem5::VegaISA::Decoder::Decoder
Decoder()
Definition: decoder.cc:45
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F32
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F32(MachInst)
Definition: decoder.cc:6271
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:5551
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F32
Definition: instructions.hh:9663
gem5::VegaISA::Inst_DS__DS_MIN_F64
Definition: instructions.hh:33209
gem5::VegaISA::Inst_VOP3__V_FMA_F16
Definition: instructions.hh:29635
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
Definition: instructions.hh:41001
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B64
Definition: instructions.hh:35211
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE2
Definition: instructions.hh:26185
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPP
static IsaDecodeMethod tableSubDecode_OP_SOPP[128]
Definition: gpu_decoder.hh:75
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PERM_B32
GPUStaticInst * decode_OPU_VOP3__V_PERM_B32(MachInst)
Definition: decoder.cc:6811
gem5::VegaISA::Inst_VOP2__V_MAX_I16
Definition: instructions.hh:7797
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64
Definition: instructions.hh:16481
gem5::VegaISA::Decoder::subDecode_OP_VOPC
GPUStaticInst * subDecode_OP_VOPC(MachInst)
Definition: decoder.cc:3722
gem5::VegaISA::Inst_SOPP__S_SETKILL
Definition: instructions.hh:4755
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:5953
gem5::VegaISA::Inst_VINTRP__V_INTERP_P2_F32
Definition: instructions.hh:17161
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32
Definition: instructions.hh:19133
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LDEXP_F16
GPUStaticInst * decode_OP_VOP2__V_LDEXP_F16(MachInst)
Definition: decoder.cc:4153
gem5::VegaISA::Inst_VOP3__V_CVT_RPI_I32_F32
Definition: instructions.hh:25961
gem5::VegaISA::Inst_DS__DS_MIN_I64
Definition: instructions.hh:32787
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ_O
Definition: instructions.hh:39885
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:12583
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9770
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U64
Definition: instructions.hh:34971
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
Definition: instructions.hh:41289
gem5::VegaISA::Inst_EXP__EXP
Definition: instructions.hh:41397
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD
Definition: instructions.hh:41571
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD
Definition: instructions.hh:41181
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE(MachInst)
Definition: decoder.cc:8845
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD
Definition: instructions.hh:5325
gem5::VegaISA::Inst_DS__DS_WRITE2_B32
Definition: instructions.hh:31215
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F16
GPUStaticInst * decode_OPU_VOP3__V_EXP_F16(MachInst)
Definition: decoder.cc:6469
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32
Definition: instructions.hh:22397
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F16
GPUStaticInst * decode_OP_VOP2__V_MADAK_F16(MachInst)
Definition: decoder.cc:4069
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32
Definition: instructions.hh:22125
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32
Definition: instructions.hh:12265
gem5::VegaISA::Inst_VOP2__V_MAX_F16
Definition: instructions.hh:7695
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16
Definition: instructions.hh:17603
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32
Definition: instructions.hh:12061
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_F16(MachInst)
Definition: decoder.cc:6961
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64
Definition: instructions.hh:10463
gem5::VegaISA::Inst_VOP3__V_BFE_U32
Definition: instructions.hh:28229
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:12187
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64
Definition: instructions.hh:16073
gem5::VegaISA::Inst_SOP2__S_ANDN2_B64
Definition: instructions.hh:693
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9968
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U32(MachInst)
Definition: decoder.cc:5521
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3
Definition: instructions.hh:36273
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:5101
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:12559
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR
Definition: instructions.hh:37001
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:5347
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst)
Definition: decoder.cc:8917
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst)
Definition: decoder.cc:9151
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32
Definition: instructions.hh:10429
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP1
static IsaDecodeMethod tableSubDecode_OP_VOP1[256]
Definition: gpu_decoder.hh:77
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9319
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32
Definition: instructions.hh:15529
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64
Definition: instructions.hh:16107
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:6211
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16
Definition: instructions.hh:14339
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16
Definition: instructions.hh:21547
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:5695
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP
Definition: instructions.hh:41911
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B32(MachInst)
Definition: decoder.cc:10645
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64
Definition: instructions.hh:12809
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10609
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:4933
gem5::VegaISA::Inst_VOP3__V_SUBREV_F32
Definition: instructions.hh:24065
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64
Definition: instructions.hh:20629
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_USHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_USHORT(MachInst)
Definition: decoder.cc:8425
gem5::VegaISA::Inst_DS__DS_MIN_U64
Definition: instructions.hh:32851
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U32(MachInst)
Definition: decoder.cc:7369
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64
Definition: instructions.hh:20085
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIX_F32
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIX_F32(MachInst)
Definition: decoder.cc:12811
gem5::VegaISA::Inst_VOP2__V_MUL_HI_I32_I24
Definition: instructions.hh:6381
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64
Definition: instructions.hh:2535
gem5::VegaISA::Inst_VOP2__V_MAC_F32
Definition: instructions.hh:6891
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64
Definition: instructions.hh:12843
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP_PCK
Definition: instructions.hh:38545
gem5::VegaISA::Inst_VOP1__V_FLOOR_F32
Definition: instructions.hh:9023
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32
Definition: instructions.hh:15257
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Definition: instructions.hh:42533
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16
Definition: instructions.hh:10905
gem5::VegaISA::Decoder::decode_OP_VOP2__V_XOR_B32
GPUStaticInst * decode_OP_VOP2__V_XOR_B32(MachInst)
Definition: decoder.cc:3973
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:9698
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10627
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND
Definition: instructions.hh:36965
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:4909
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC1
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC1(MachInst)
Definition: decoder.cc:10867
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8557
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16
Definition: instructions.hh:10599
gem5::VegaISA::Inst_VOP3__V_MIN_U32
Definition: instructions.hh:24439
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F32(MachInst)
Definition: decoder.cc:6655
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16
Definition: instructions.hh:14237
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16
GPUStaticInst * decode_OP_DS__DS_WRITE_B16(MachInst)
Definition: decoder.cc:7345
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F32
GPUStaticInst * decode_OPU_VOP3__V_COS_F32(MachInst)
Definition: decoder.cc:6349
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:4873
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:3889
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_O
Definition: instructions.hh:40749
gem5::VegaISA::Inst_MIMG__IMAGE_GET_RESINFO
Definition: instructions.hh:38581
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:5611
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN
Definition: instructions.hh:42053
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst)
Definition: decoder.cc:7441
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32
Definition: instructions.hh:19473
gem5::VegaISA::Inst_VOP2__V_MUL_U32_U24
Definition: instructions.hh:6415
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I32(MachInst)
Definition: decoder.cc:12355
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16
Definition: instructions.hh:13863
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:5005
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LL_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LL_B32_B16(MachInst)
Definition: decoder.cc:4477
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst)
Definition: decoder.cc:8965
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_FMA_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_FMA_F16(MachInst)
Definition: decoder.cc:12781
gem5::VegaISA::Decoder::decode_OP_VOP2__V_AND_B32
GPUStaticInst * decode_OP_VOP2__V_AND_B32(MachInst)
Definition: decoder.cc:3961
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:11923
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8203
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32
Definition: instructions.hh:22703
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8581
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32
Definition: instructions.hh:12673
gem5::VegaISA::Inst_VOP2__V_SUBREV_F16
Definition: instructions.hh:7283
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC(MachInst)
Definition: decoder.cc:10303
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:11143
gem5::VegaISA::Inst_DS__DS_MSKOR_B64
Definition: instructions.hh:33011
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16(MachInst)
Definition: decoder.cc:7003
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:11113
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_U32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_U32(MachInst)
Definition: decoder.cc:4441
gem5::VegaISA::Inst_VOP1__V_SIN_F32
Definition: instructions.hh:9343
gem5::VegaISA::Inst_VOP3__V_FMA_F32
Definition: instructions.hh:28337
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9932
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_F32(MachInst)
Definition: decoder.cc:6301
gem5::VegaISA::Inst_SOPP__S_WAKEUP
Definition: instructions.hh:4511
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H_PCK(MachInst)
Definition: decoder.cc:9091
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:5413
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16
Definition: instructions.hh:18011
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8449
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U32
GPUStaticInst * decode_OP_VOP2__V_MIN_U32(MachInst)
Definition: decoder.cc:3931
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I16_F16
Definition: instructions.hh:27621
gem5::VegaISA::Decoder::tableDecodePrimary
static IsaDecodeMethod tableDecodePrimary[512]
Definition: gpu_decoder.hh:63
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst)
Definition: decoder.cc:10033
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4
Definition: instructions.hh:5757
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10255
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:35999
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:12385
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst)
Definition: decoder.cc:10063
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10297
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9842
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:9602
gem5::VegaISA::InstFormat
Definition: gpu_decoder.hh:1903
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64
Definition: instructions.hh:16991
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9271
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst)
Definition: decoder.cc:9145
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst)
Definition: decoder.cc:9181
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16
Definition: instructions.hh:21275
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I64(MachInst)
Definition: decoder.cc:8041
gem5::VegaISA::Inst_VOP3__V_MUL_U32_U24
Definition: instructions.hh:24235
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst)
Definition: decoder.cc:8881
gem5::VegaISA::Inst_SOPP__S_BRANCH
Definition: instructions.hh:4481
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
Definition: instructions.hh:37505
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9428
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8
Definition: instructions.hh:2887
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9259
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LH_B32_B16(MachInst)
Definition: decoder.cc:4483
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_O(MachInst)
Definition: decoder.cc:9127
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16
Definition: instructions.hh:11551
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8809
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U16
GPUStaticInst * decode_OP_VOP2__V_ADD_U16(MachInst)
Definition: decoder.cc:4075
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst)
Definition: decoder.cc:7429
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:11095
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ABS_I32
GPUStaticInst * decode_OP_SOP1__S_ABS_I32(MachInst)
Definition: decoder.cc:10675
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:9985
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B32
Definition: instructions.hh:32021
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:5911
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:6115
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64
Definition: instructions.hh:16175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:12289
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B64
Definition: instructions.hh:4229
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32
Definition: instructions.hh:3589
gem5::VegaISA::InFmt_MUBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1711
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:5053
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8359
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U64(MachInst)
Definition: decoder.cc:5671
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_O
Definition: instructions.hh:40965
gem5::VegaISA::Decoder::decode_OP_SOPK__S_GETREG_B32
GPUStaticInst * decode_OP_SOPK__S_GETREG_B32(MachInst)
Definition: decoder.cc:4597
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32
Definition: instructions.hh:18861
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX_I16(MachInst)
Definition: decoder.cc:6079
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:12199
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32
Definition: instructions.hh:19167
gem5::VegaISA::Inst_DS__DS_RSUB_U32
Definition: instructions.hh:30829
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst)
Definition: decoder.cc:10873
gem5::VegaISA::Inst_VOP3__V_MOV_FED_B32
Definition: instructions.hh:25865
gem5::VegaISA::Inst_DS__DS_READ_B64
Definition: instructions.hh:33953
gem5::VegaISA::Decoder::subDecode_OP_DS
GPUStaticInst * subDecode_OP_DS(MachInst)
Definition: decoder.cc:3794
gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64
Definition: instructions.hh:3141
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4
Definition: instructions.hh:41673
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16
Definition: instructions.hh:14747
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_DEC
Definition: instructions.hh:39023
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:5677
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:12061
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64
Definition: instructions.hh:12911
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8293
gem5::VegaISA::Inst_VOP1__V_FRACT_F64
Definition: instructions.hh:9631
gem5::VegaISA::Inst_VOP2__V_MADAK_F16
Definition: instructions.hh:7421
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:11119
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F16
GPUStaticInst * decode_OPU_VOP3__V_MAC_F16(MachInst)
Definition: decoder.cc:6013
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:12631
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst)
Definition: decoder.cc:9506
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32
Definition: instructions.hh:11993
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32
Definition: instructions.hh:22431
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst)
Definition: decoder.cc:6625
gem5::VegaISA::Inst_VOP3__V_MIN_U16
Definition: instructions.hh:25511
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16
Definition: instructions.hh:18283
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:12055
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:12025
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_V
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_V(MachInst)
Definition: decoder.cc:7963
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst)
Definition: decoder.cc:8947
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64
Definition: instructions.hh:13387
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32
Definition: instructions.hh:16005
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:5209
gem5::VegaISA::Inst_SOPP__S_TTRACEDATA
Definition: instructions.hh:5085
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHLREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHLREV_B16(MachInst)
Definition: decoder.cc:12721
gem5::VegaISA::Inst_SOP2__S_AND_B32
Definition: instructions.hh:455
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64
Definition: instructions.hh:22907
gem5::VegaISA::Decoder::decode_OP_SOPP__S_INCPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_INCPERFLEVEL(MachInst)
Definition: decoder.cc:10957
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:4735
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U64
Definition: instructions.hh:33307
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F32
GPUStaticInst * decode_OP_VOP1__V_SIN_F32(MachInst)
Definition: decoder.cc:11281
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:5485
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32
Definition: instructions.hh:15053
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64
Definition: instructions.hh:16651
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F16
Definition: instructions.hh:29913
gem5::VegaISA::Inst_VOP1__V_CVT_F16_I16
Definition: instructions.hh:9787
gem5::VegaISA::InstFormat::iFmt_SMEM
InFmt_SMEM iFmt_SMEM
Definition: gpu_decoder.hh:1917
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE0
Definition: instructions.hh:8575
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I16(MachInst)
Definition: decoder.cc:12163
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:4003
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I64_I32
GPUStaticInst * decode_OPU_VOP3__V_MAD_I64_I32(MachInst)
Definition: decoder.cc:6787
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64
Definition: instructions.hh:19643
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64
Definition: instructions.hh:22941
gem5::VegaISA::Inst_VOP3__V_BFE_I32
Definition: instructions.hh:28265
gem5::VegaISA::Inst_SOP2__S_NAND_B32
Definition: instructions.hh:795
gem5::VegaISA::InFmt_VOP1
Definition: gpu_decoder.hh:1787
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10159
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Definition: instructions.hh:42601
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD
Definition: instructions.hh:41109
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:4849
gem5::VegaISA::Inst_DS__DS_GWS_INIT
Definition: instructions.hh:34599
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9307
gem5::VegaISA::InstFormat::iFmt_EXP
InFmt_EXP iFmt_EXP
Definition: gpu_decoder.hh:1906
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2
Definition: instructions.hh:41605
gem5::VegaISA::Inst_VOP2__V_SUBREV_CO_U32
Definition: instructions.hh:7065
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN
Definition: instructions.hh:42087
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U16_U32
Definition: instructions.hh:30697
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64
Definition: instructions.hh:16549
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32
Definition: instructions.hh:11789
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64
Definition: instructions.hh:19677
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP3P
static IsaDecodeMethod tableSubDecode_OP_VOP3P[128]
Definition: gpu_decoder.hh:79
gem5::VegaISA::Inst_DS__DS_INC_U32
Definition: instructions.hh:30861
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:12049
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I32
GPUStaticInst * decode_OP_DS__DS_MAX_I32(MachInst)
Definition: decoder.cc:7237
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16
Definition: instructions.hh:2919
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8287
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ
Definition: instructions.hh:39309
gem5::VegaISA::Inst_SOP1__S_NOT_B64
Definition: instructions.hh:2343
gem5::VegaISA::Inst_VOP3__V_ADD_U16
Definition: instructions.hh:25137
gem5::VegaISA::Inst_VOP3__V_MAD_U64_U32
Definition: instructions.hh:29387
gem5::VegaISA::Inst_VOP3__V_CVT_F16_I16
Definition: instructions.hh:27333
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10177
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:4891
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:12331
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I16(MachInst)
Definition: decoder.cc:5239
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:5605
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:6229
gem5::VegaISA::Inst_DS__DS_ORDERED_COUNT
Definition: instructions.hh:34819
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL
Definition: instructions.hh:39561
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16
Definition: instructions.hh:18317
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:4669
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9740
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64
Definition: instructions.hh:23859
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD
Definition: instructions.hh:36433
gem5::VegaISA::Inst_DS__DS_ADD_RTN_F32
Definition: instructions.hh:32259
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:37955
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16
Definition: instructions.hh:14679
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_I32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_I32(MachInst)
Definition: decoder.cc:6379
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:5197
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32
Definition: instructions.hh:12639
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9422
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8539
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16
Definition: instructions.hh:14577
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_I32
GPUStaticInst * decode_OP_SOP2__S_MIN_I32(MachInst)
Definition: decoder.cc:4213
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:12253
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U64(MachInst)
Definition: decoder.cc:7723
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64
Definition: instructions.hh:20663
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F64
GPUStaticInst * decode_OPU_VOP3__V_MUL_F64(MachInst)
Definition: decoder.cc:7021
gem5::VegaISA::Inst_VOP3__V_MIN_I32
Definition: instructions.hh:24371
gem5::VegaISA::Decoder::decode_OP_VOP1__V_MOV_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_B32(MachInst)
Definition: decoder.cc:11047
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F16
GPUStaticInst * decode_OP_VOP2__V_MADMK_F16(MachInst)
Definition: decoder.cc:4063
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32
Definition: instructions.hh:15291
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64
Definition: instructions.hh:13761
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_LO_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_LO_U16(MachInst)
Definition: decoder.cc:12703
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I64(MachInst)
Definition: decoder.cc:5665
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:12379
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_O
Definition: instructions.hh:39633
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B32
Definition: instructions.hh:32055
gem5::VegaISA::Inst_VOP3__V_CVT_FLR_I32_F32
Definition: instructions.hh:25993
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst)
Definition: decoder.cc:9109
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:5809
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst)
Definition: decoder.cc:8863
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL_O
Definition: instructions.hh:39741
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst)
Definition: decoder.cc:6541
gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64
Definition: instructions.hh:3365
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:35885
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:6199
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_B32(MachInst)
Definition: decoder.cc:6109
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst)
Definition: decoder.cc:10981
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32
Definition: instructions.hh:15835
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16
Definition: instructions.hh:10939
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_I16(MachInst)
Definition: decoder.cc:6805
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:11551
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:38145
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64
Definition: instructions.hh:23179
gem5::VegaISA::InFmt_SOP1
Definition: gpu_decoder.hh:1743
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE
Definition: instructions.hh:41435
gem5::VegaISA::Inst_VOP3__V_MIN_F32
Definition: instructions.hh:24303
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst)
Definition: decoder.cc:9043
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I64(MachInst)
Definition: decoder.cc:7741
gem5::VegaISA::Inst_VOP3__V_FLOOR_F16
Definition: instructions.hh:27653
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U32(MachInst)
Definition: decoder.cc:12403
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8659
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F32
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F32(MachInst)
Definition: decoder.cc:11215
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U64(MachInst)
Definition: decoder.cc:8035
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_U32(MachInst)
Definition: decoder.cc:10777
gem5::VegaISA::Inst_VOP3__V_MAX_U16
Definition: instructions.hh:25443
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U64(MachInst)
Definition: decoder.cc:7753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:5959
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:4639
gem5::VegaISA::Inst_SOPK__S_CBRANCH_I_FORK
Definition: instructions.hh:2055
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:4741
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B64(MachInst)
Definition: decoder.cc:7099
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4
Definition: instructions.hh:36547
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64
Definition: instructions.hh:23213
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32
Definition: instructions.hh:22839
gem5::VegaISA::Inst_DS__DS_PERMUTE_B32
Definition: instructions.hh:32559
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F64
Definition: instructions.hh:35271
gem5::VegaISA::Inst_VINTRP__V_INTERP_MOV_F32
Definition: instructions.hh:17195
gem5::VegaISA::Decoder::decode_OP_VOP2__V_OR_B32
GPUStaticInst * decode_OP_VOP2__V_OR_B32(MachInst)
Definition: decoder.cc:3967
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I32
Definition: instructions.hh:31715
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B64(MachInst)
Definition: decoder.cc:10543
gem5::VegaISA::Inst_VOP3__V_TRUNC_F64
Definition: instructions.hh:26313
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1_VOL
Definition: instructions.hh:36647
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:9596
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F32
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F32(MachInst)
Definition: decoder.cc:6313
gem5::VegaISA::Decoder::tableSubDecode_OP_GLOBAL
static IsaDecodeMethod tableSubDecode_OP_GLOBAL[128]
Definition: gpu_decoder.hh:67
gem5::VegaISA::Inst_SOPP__S_SETHALT
Definition: instructions.hh:4815
gem5::VegaISA::Inst_DS__DS_MIN_F32
Definition: instructions.hh:31351
gem5::VegaISA::InFmt_VOPC
Definition: gpu_decoder.hh:1827
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U32
Definition: instructions.hh:31681
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:35543
gem5::VegaISA::Inst_DS__DS_MAX_F32
Definition: instructions.hh:31383
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10615
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:4945
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U32
GPUStaticInst * decode_OP_DS__DS_DEC_U32(MachInst)
Definition: decoder.cc:7225
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_F16(MachInst)
Definition: decoder.cc:12799
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I64
Definition: instructions.hh:35031
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F32
Definition: instructions.hh:32157
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_O
Definition: instructions.hh:40101
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst)
Definition: decoder.cc:8815
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64
Definition: instructions.hh:23417
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64
Definition: instructions.hh:23009
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_WREXEC_B64(MachInst)
Definition: decoder.cc:10705
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst)
Definition: decoder.cc:9217
gem5::VegaISA::Inst_DS__DS_MIN_I32
Definition: instructions.hh:30925
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:5659
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:4627
gem5::VegaISA::Inst_DS__DS_MAX_I32
Definition: instructions.hh:30957
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B128
GPUStaticInst * decode_OP_DS__DS_READ_B128(MachInst)
Definition: decoder.cc:8119
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:12541
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:9872
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:11515
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXHI_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXHI_F16(MachInst)
Definition: decoder.cc:12823
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst)
Definition: decoder.cc:6967
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9295
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I16(MachInst)
Definition: decoder.cc:6841
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L(MachInst)
Definition: decoder.cc:9055
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64
Definition: instructions.hh:23587
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:4009
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64
Definition: instructions.hh:19745
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
Definition: instructions.hh:40173
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORD(MachInst)
Definition: decoder.cc:8437
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:4105
gem5::VegaISA::InFmt_VOP3P::OP
unsigned int OP
Definition: gpu_decoder.hh:1891
gem5::VegaISA::Inst_DS__DS_READ2ST64_B32
Definition: instructions.hh:32361
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:12499
gem5::VegaISA::Inst_DS__DS_CMPST_B64
Definition: instructions.hh:33145
gem5::VegaISA::Inst_SOPC__S_CMP_GT_I32
Definition: instructions.hh:3845
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64
Definition: instructions.hh:20153
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I16(MachInst)
Definition: decoder.cc:6877
gem5::VegaISA::Decoder::subDecode_OP_SOPC
GPUStaticInst * subDecode_OP_SOPC(MachInst)
Definition: decoder.cc:3754
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4
Definition: instructions.hh:5397
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64
Definition: instructions.hh:16583
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:6127
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32
Definition: instructions.hh:19405
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F32(MachInst)
Definition: decoder.cc:5833
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B96
GPUStaticInst * decode_OP_DS__DS_WRITE_B96(MachInst)
Definition: decoder.cc:8101
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16
Definition: instructions.hh:11449
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2
Definition: instructions.hh:36471
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:11473
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16
Definition: instructions.hh:17705
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B64(MachInst)
Definition: decoder.cc:10555
gem5::VegaISA::Inst_DS__DS_CMPST_F64
Definition: instructions.hh:33177
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16
Definition: instructions.hh:21513
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U32(MachInst)
Definition: decoder.cc:5479
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_U16_F32
Definition: instructions.hh:30629
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:12607
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64
Definition: instructions.hh:13319
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:4681
gem5::VegaISA::Inst_VOP1__V_RSQ_F16
Definition: instructions.hh:9947
gem5::VegaISA::Inst_SOP2__S_ORN2_B64
Definition: instructions.hh:761
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:37879
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64
Definition: instructions.hh:19847
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_I64(MachInst)
Definition: decoder.cc:7573
gem5::VegaISA::Inst_VOP1__V_RCP_F16
Definition: instructions.hh:9883
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_B32(MachInst)
Definition: decoder.cc:10393
gem5::VegaISA::Inst_VOP3__V_EXP_F16
Definition: instructions.hh:27557
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:11719
gem5::VegaISA::Inst_VOP1__V_CVT_F64_U32
Definition: instructions.hh:8735
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F16
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F16(MachInst)
Definition: decoder.cc:6487
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32
Definition: instructions.hh:21887
gem5::VegaISA::Inst_DS__DS_MIN_U32
Definition: instructions.hh:30989
gem5::VegaISA::Inst_DS__DS_MAX_U32
Definition: instructions.hh:31021
gem5::VegaISA::Inst_VOP3__V_MIN_I16
Definition: instructions.hh:25545
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_I16(MachInst)
Definition: decoder.cc:12709
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:11863
gem5::VegaISA::Inst_DS__DS_MSKOR_B32
Definition: instructions.hh:31149
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Definition: instructions.hh:42771
gem5::VegaISA::InFmt_SOPC
Definition: gpu_decoder.hh:1758
gem5::VegaISA::Inst_VOP1__V_BFREV_B32
Definition: instructions.hh:9439
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst)
Definition: decoder.cc:9067
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F16
GPUStaticInst * decode_OP_VOP1__V_SQRT_F16(MachInst)
Definition: decoder.cc:11395
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9325
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:12571
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I16
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:4111
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U32
GPUStaticInst * decode_OP_VOP2__V_MAX_U32(MachInst)
Definition: decoder.cc:3937
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_O
Definition: instructions.hh:41325
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32
Definition: instructions.hh:18623
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:12079
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:6409
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I16(MachInst)
Definition: decoder.cc:5281
gem5::VegaISA::Inst_SOPC__S_CMP_GT_U32
Definition: instructions.hh:4037
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16
Definition: instructions.hh:14713
gem5::VegaISA::Inst_VOP3__V_RCP_IFLAG_F32
Definition: instructions.hh:26697
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:6193
gem5::VegaISA::Inst_VOP3__V_CVT_F64_U32
Definition: instructions.hh:26281
gem5::VegaISA::Inst_VOP3__V_MIN_F16
Definition: instructions.hh:25409
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8635
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:37181
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F16(MachInst)
Definition: decoder.cc:4045
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F16(MachInst)
Definition: decoder.cc:11587
gem5::VegaISA::Inst_VOP1__V_RNDNE_F32
Definition: instructions.hh:8991
gem5::VegaISA::Inst_VOP3__V_LDEXP_F16
Definition: instructions.hh:25579
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:5767
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:4675
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:12073
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:4885
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64
Definition: instructions.hh:23281
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst)
Definition: decoder.cc:10891
gem5::VegaISA::Inst_DS__DS_WRITE_B16
Definition: instructions.hh:31511
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD3_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD3_U32(MachInst)
Definition: decoder.cc:6919
gem5::VegaISA::Decoder::decode
GPUStaticInst * decode(MachInst mach_inst)
Definition: decoder.cc:3714
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8533
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_O
Definition: instructions.hh:41253
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B32
Definition: instructions.hh:34359
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB
Definition: instructions.hh:5929
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:11677
gem5::VegaISA::Inst_SOP1__S_GETPC_B64
Definition: instructions.hh:3079
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst)
Definition: decoder.cc:9187
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN_I16(MachInst)
Definition: decoder.cc:6091
gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64
Definition: instructions.hh:3397
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16
Definition: instructions.hh:17807
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32
Definition: instructions.hh:18929
gem5::VegaISA::Inst_VOP1__V_SQRT_F16
Definition: instructions.hh:9915
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD
Definition: instructions.hh:41775
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9902
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst)
Definition: decoder.cc:8995
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64
Definition: instructions.hh:13829
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:4753
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:38031
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN
Definition: instructions.hh:38329
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F64
GPUStaticInst * decode_OP_VOP1__V_SQRT_F64(MachInst)
Definition: decoder.cc:11275
gem5::VegaISA::Inst_VOP3__V_ADD_F16
Definition: instructions.hh:24967
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F64
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F64(MachInst)
Definition: decoder.cc:6253
gem5::VegaISA::Inst_VOP1__V_CEIL_F64
Definition: instructions.hh:8799
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U32
Definition: instructions.hh:34209
gem5::VegaISA::Inst_SOP1__S_BITSET1_B32
Definition: instructions.hh:3015
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_F32(MachInst)
Definition: decoder.cc:7945
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst)
Definition: decoder.cc:6997
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32
Definition: instructions.hh:11959
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U16
Definition: instructions.hh:25239
gem5::VegaISA::Decoder::subDecode_OP_MIMG
GPUStaticInst * subDecode_OP_MIMG(MachInst)
Definition: decoder.cc:3839
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32
Definition: instructions.hh:15869
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:9620
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:11965
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_I32(MachInst)
Definition: decoder.cc:4519
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MULK_I32
GPUStaticInst * decode_OP_SOPK__S_MULK_I32(MachInst)
Definition: decoder.cc:4585
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_U32
GPUStaticInst * decode_OPU_VOP3__V_BFE_U32(MachInst)
Definition: decoder.cc:6589
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_O
Definition: instructions.hh:40641
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8191
gem5::VegaISA::Inst_DS__DS_WRITE_B128
Definition: instructions.hh:35333
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F16(MachInst)
Definition: decoder.cc:6793
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8629
gem5::VegaISA::InstFormat::iFmt_VOP3A
InFmt_VOP3A iFmt_VOP3A
Definition: gpu_decoder.hh:1927
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:4027
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:11347
gem5::VegaISA::Inst_VOP3__V_MQSAD_U32_U8
Definition: instructions.hh:29351
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U32(MachInst)
Definition: decoder.cc:6649
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_I32
GPUStaticInst * decode_OP_VOP1__V_FFBH_I32(MachInst)
Definition: decoder.cc:11317
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U32
Definition: instructions.hh:31545
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B64(MachInst)
Definition: decoder.cc:7633
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32
Definition: instructions.hh:22159
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:11581
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:4801
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:12667
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B64(MachInst)
Definition: decoder.cc:7777
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP
Definition: instructions.hh:38473
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32
Definition: instructions.hh:19303
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:12157
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:4975
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:5167
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I64(MachInst)
Definition: decoder.cc:8047
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_XOR
Definition: instructions.hh:38955
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst)
Definition: decoder.cc:10975
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:5143
gem5::VegaISA::InFmt_SOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1761
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:5437
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8161
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst)
Definition: decoder.cc:8911
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:5173
gem5::VegaISA::Inst_SOP1__S_BREV_B64
Definition: instructions.hh:2471
gem5::VegaISA::Inst_VOP3__V_MAX_I16
Definition: instructions.hh:25477
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10189
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4
Definition: instructions.hh:40209
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32
Definition: instructions.hh:12469
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B64(MachInst)
Definition: decoder.cc:7771
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL
Definition: instructions.hh:41145
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8143
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:4777
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:4765
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32
Definition: instructions.hh:11857
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE
Definition: instructions.hh:36349
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:12265
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_BARRIER
GPUStaticInst * decode_OP_DS__DS_GWS_BARRIER(MachInst)
Definition: decoder.cc:7981
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:12661
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BRANCH
GPUStaticInst * decode_OP_SOPP__S_BRANCH(MachInst)
Definition: decoder.cc:10849
gem5::VegaISA::Inst_SOP2__S_RFE_RESTORE_B64
Definition: instructions.hh:1509
gem5::VegaISA::Inst_SOPC__S_CMP_GE_I32
Definition: instructions.hh:3877
gem5::VegaISA::Inst_VOP3__V_ALIGNBIT_B32
Definition: instructions.hh:28445
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F32(MachInst)
Definition: decoder.cc:7453
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
Definition: instructions.hh:5205
gem5::VegaISA::Inst_SMEM__S_MEMREALTIME
Definition: instructions.hh:6043
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F32
GPUStaticInst * decode_OPU_VOP3__V_MED3_F32(MachInst)
Definition: decoder.cc:6673
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10111
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U64
Definition: instructions.hh:35061
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst)
Definition: decoder.cc:7951
gem5::VegaISA::Inst_VOP3__V_MAX_F16
Definition: instructions.hh:25375
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFREV_B32
GPUStaticInst * decode_OPU_VOP3__V_BFREV_B32(MachInst)
Definition: decoder.cc:6361
gem5::VegaISA::InstFormat::iFmt_SOPK
InFmt_SOPK iFmt_SOPK
Definition: gpu_decoder.hh:1922
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F32
Definition: instructions.hh:29021
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64
Definition: instructions.hh:23723
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:11419
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8605
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:12271
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16
Definition: instructions.hh:11517
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32
Definition: instructions.hh:19507
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B64(MachInst)
Definition: decoder.cc:10807
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B32
GPUStaticInst * decode_OP_SOP2__S_ORN2_B32(MachInst)
Definition: decoder.cc:4297
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F32
GPUStaticInst * decode_OP_VOP2__V_MADMK_F32(MachInst)
Definition: decoder.cc:3985
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F32
GPUStaticInst * decode_OP_VOP2__V_ADD_F32(MachInst)
Definition: decoder.cc:3853
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN
Definition: instructions.hh:36821
gem5::VegaISA::Inst_DS__DS_AND_RTN_B64
Definition: instructions.hh:33579
gem5::VegaISA::Inst_VOP3__V_SIN_F32
Definition: instructions.hh:26889
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst)
Definition: decoder.cc:9193
gem5::VegaISA::Inst_SOP1__S_WQM_B32
Definition: instructions.hh:2375
gem5::VegaISA::Inst_DS__DS_APPEND
Definition: instructions.hh:34787
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I16
GPUStaticInst * decode_OP_VOP2__V_MIN_I16(MachInst)
Definition: decoder.cc:4147
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U32
Definition: instructions.hh:31783
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64
Definition: instructions.hh:16345
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CALL_B64
GPUStaticInst * decode_OP_SOPK__S_CALL_B64(MachInst)
Definition: decoder.cc:4615
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SUB
Definition: instructions.hh:38717
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9301
gem5::VegaISA::Inst_VOP3__V_CUBETC_F32
Definition: instructions.hh:28157
gem5::VegaISA::Inst_SOPK__S_GETREG_B32
Definition: instructions.hh:2087
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B
Definition: instructions.hh:39237
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOP
GPUStaticInst * decode_OPU_VOP3__V_NOP(MachInst)
Definition: decoder.cc:6103
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I16
GPUStaticInst * decode_OP_DS__DS_READ_I16(MachInst)
Definition: decoder.cc:7513
gem5::VegaISA::Inst_VOP3__V_CVT_PK_I16_I32
Definition: instructions.hh:30731
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16(MachInst)
Definition: decoder.cc:7687
gem5::VegaISA::Decoder::tableSubDecode_OP_DS
static IsaDecodeMethod tableSubDecode_OP_DS[256]
Definition: gpu_decoder.hh:65
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16
Definition: instructions.hh:11007
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8281
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:5353
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64
Definition: instructions.hh:16379
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32
Definition: instructions.hh:12197
gem5::VegaISA::Inst_SOPK__S_MOVK_I32
Definition: instructions.hh:1543
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9752
gem5::VegaISA::Decoder::decode_OP_DS__DS_BPERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_BPERMUTE_B32(MachInst)
Definition: decoder.cc:7537
gem5::VegaISA::Inst_VOP3__V_MAC_F32
Definition: instructions.hh:24711
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:9518
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16
Definition: instructions.hh:10871
gem5::VegaISA::Inst_DS__DS_ADD_U64
Definition: instructions.hh:32627
gem5::VegaISA::Inst_SOPC__S_CMP_GE_U32
Definition: instructions.hh:4069
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:5839
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9800
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B32(MachInst)
Definition: decoder.cc:7417
gem5::VegaISA::InFmt_FLAT
Definition: gpu_decoder.hh:1635
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP
Definition: instructions.hh:38257
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C
Definition: instructions.hh:40425
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:9662
gem5::VegaISA::Inst_SOP2__S_BFM_B64
Definition: instructions.hh:1237
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:12259
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:12217
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B32
Definition: instructions.hh:34389
gem5::VegaISA::InstFormat::iFmt_MUBUF
InFmt_MUBUF iFmt_MUBUF
Definition: gpu_decoder.hh:1915
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8395
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:9632
gem5::VegaISA::Inst_VOP1__V_COS_F16
Definition: instructions.hh:10299
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:6223
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B32
GPUStaticInst * decode_OP_SOP2__S_AND_B32(MachInst)
Definition: decoder.cc:4249
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F64
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F64(MachInst)
Definition: decoder.cc:7039
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:12655
gem5::VegaISA::Inst_VOP1__V_RSQ_F64
Definition: instructions.hh:9247
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U32(MachInst)
Definition: decoder.cc:7393
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B32
GPUStaticInst * decode_OP_SOP2__S_NAND_B32(MachInst)
Definition: decoder.cc:4309
gem5::VegaISA::Inst_VOP1__V_TRUNC_F64
Definition: instructions.hh:8767
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE(MachInst)
Definition: decoder.cc:10057
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F16
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F16(MachInst)
Definition: decoder.cc:11449
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_INIT
GPUStaticInst * decode_OP_DS__DS_GWS_INIT(MachInst)
Definition: decoder.cc:7957
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SAT_PK_U8_I16
GPUStaticInst * decode_OP_VOP1__V_SAT_PK_U8_I16(MachInst)
Definition: decoder.cc:11497
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_I32(MachInst)
Definition: decoder.cc:4393
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:12487
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8455
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64
Definition: instructions.hh:20187
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F32(MachInst)
Definition: decoder.cc:11779
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32
Definition: instructions.hh:30153
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F16
GPUStaticInst * decode_OPU_VOP3__V_SUB_F16(MachInst)
Definition: decoder.cc:5995
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCNZ
Definition: instructions.hh:4633
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX_I32(MachInst)
Definition: decoder.cc:5893
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE1
Definition: instructions.hh:26153
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I64
GPUStaticInst * decode_OP_DS__DS_MAX_I64(MachInst)
Definition: decoder.cc:7579
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst)
Definition: decoder.cc:8875
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:9836
gem5::VegaISA::Inst_VOP3__V_INTERP_P1_F32
Definition: instructions.hh:29741
gem5::VegaISA::Inst_VOP1__V_NOP
Definition: instructions.hh:8035
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_I16(MachInst)
Definition: decoder.cc:12715
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64
Definition: instructions.hh:16277
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ
Definition: instructions.hh:40605
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:4837
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64
Definition: instructions.hh:17025
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8
GPUStaticInst * decode_OP_DS__DS_WRITE_B8(MachInst)
Definition: decoder.cc:7339
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F16
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F16(MachInst)
Definition: decoder.cc:6097
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8545
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B32
GPUStaticInst * decode_OP_DS__DS_READ_B32(MachInst)
Definition: decoder.cc:7483
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U32
GPUStaticInst * decode_OP_DS__DS_MAX_U32(MachInst)
Definition: decoder.cc:7249
gem5::VegaISA::Inst_VOP3__V_LOG_LEGACY_F32
Definition: instructions.hh:27909
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst)
Definition: decoder.cc:9139
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64
Definition: instructions.hh:23451
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_F64(MachInst)
Definition: decoder.cc:7651
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SWAPPC_B64
GPUStaticInst * decode_OP_SOP1__S_SWAPPC_B64(MachInst)
Definition: decoder.cc:10573
gem5::VegaISA::Inst_VOP3__V_MED3_U32
Definition: instructions.hh:28805
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_U32(MachInst)
Definition: decoder.cc:10783
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F32(MachInst)
Definition: decoder.cc:7459
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
Definition: instructions.hh:37577
gem5::VegaISA::Inst_VOP2__V_MUL_F32
Definition: instructions.hh:6313
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
Definition: instructions.hh:40137
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F64
GPUStaticInst * decode_OP_VOP1__V_RSQ_F64(MachInst)
Definition: decoder.cc:11263
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD
Definition: instructions.hh:41983
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16
Definition: instructions.hh:18351
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64
Definition: instructions.hh:3621
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:4963
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:10005
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64
Definition: instructions.hh:13455
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16
Definition: instructions.hh:21649
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst)
Definition: decoder.cc:8323
gem5::VegaISA::Inst_VOP3__V_RNDNE_F16
Definition: instructions.hh:27749
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64
Definition: instructions.hh:2727
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC
Definition: instructions.hh:37073
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:5683
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U64
Definition: instructions.hh:33273

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