gem5  v21.1.0.2
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
int.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2014 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2009 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include <cassert>
42 
43 #ifndef __ARCH_ARM_REGS_INT_HH__
44 #define __ARCH_ARM_REGS_INT_HH__
45 
46 #include "arch/arm/types.hh"
47 #include "base/logging.hh"
48 #include "sim/core.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ArmISA
54 {
55 
56 BitUnion32(PackedIntReg)
57  Bitfield<31, 16> uh1;
58  Bitfield<15, 0> uh0;
59  SignedBitfield<31, 16> sh1;
60  SignedBitfield<15, 0> sh0;
61  Bitfield<31, 0> uw;
62  SignedBitfield<31, 0> sw;
63 EndBitUnion(PackedIntReg)
64 
65 enum IntRegIndex
66 {
67  /* All the unique register indices. */
68  INTREG_R0,
69  INTREG_R1,
70  INTREG_R2,
71  INTREG_R3,
72  INTREG_R4,
73  INTREG_R5,
74  INTREG_R6,
75  INTREG_R7,
76  INTREG_R8,
77  INTREG_R9,
78  INTREG_R10,
79  INTREG_R11,
80  INTREG_R12,
81  INTREG_R13,
82  INTREG_SP = INTREG_R13,
83  INTREG_R14,
84  INTREG_LR = INTREG_R14,
85  INTREG_R15,
86  INTREG_PC = INTREG_R15,
87 
88  INTREG_R13_SVC,
89  INTREG_SP_SVC = INTREG_R13_SVC,
90  INTREG_R14_SVC,
91  INTREG_LR_SVC = INTREG_R14_SVC,
92 
93  INTREG_R13_MON,
94  INTREG_SP_MON = INTREG_R13_MON,
95  INTREG_R14_MON,
96  INTREG_LR_MON = INTREG_R14_MON,
97 
98  INTREG_R13_HYP,
99  INTREG_SP_HYP = INTREG_R13_HYP,
100 
101  INTREG_R13_ABT,
102  INTREG_SP_ABT = INTREG_R13_ABT,
103  INTREG_R14_ABT,
104  INTREG_LR_ABT = INTREG_R14_ABT,
105 
106  INTREG_R13_UND,
107  INTREG_SP_UND = INTREG_R13_UND,
108  INTREG_R14_UND,
109  INTREG_LR_UND = INTREG_R14_UND,
110 
111  INTREG_R13_IRQ,
112  INTREG_SP_IRQ = INTREG_R13_IRQ,
113  INTREG_R14_IRQ,
114  INTREG_LR_IRQ = INTREG_R14_IRQ,
115 
116  INTREG_R8_FIQ,
117  INTREG_R9_FIQ,
118  INTREG_R10_FIQ,
119  INTREG_R11_FIQ,
120  INTREG_R12_FIQ,
121  INTREG_R13_FIQ,
122  INTREG_SP_FIQ = INTREG_R13_FIQ,
123  INTREG_R14_FIQ,
124  INTREG_LR_FIQ = INTREG_R14_FIQ,
125 
126  INTREG_ZERO,
127  INTREG_UREG0,
128  INTREG_UREG1,
129  INTREG_UREG2,
130  INTREG_DUMMY, // Dummy reg used to throw away int reg results
131 
132  INTREG_SP0,
133  INTREG_SP1,
134  INTREG_SP2,
135  INTREG_SP3,
136 
137  NUM_INTREGS,
138  NUM_ARCH_INTREGS = 32,
139 
140  /* AArch64 registers */
141  INTREG_X0 = 0,
142  INTREG_X1,
143  INTREG_X2,
144  INTREG_X3,
145  INTREG_X4,
146  INTREG_X5,
147  INTREG_X6,
148  INTREG_X7,
149  INTREG_X8,
150  INTREG_X9,
151  INTREG_X10,
152  INTREG_X11,
153  INTREG_X12,
154  INTREG_X13,
155  INTREG_X14,
156  INTREG_X15,
157  INTREG_X16,
158  INTREG_X17,
159  INTREG_X18,
160  INTREG_X19,
161  INTREG_X20,
162  INTREG_X21,
163  INTREG_X22,
164  INTREG_X23,
165  INTREG_X24,
166  INTREG_X25,
167  INTREG_X26,
168  INTREG_X27,
169  INTREG_X28,
170  INTREG_X29,
171  INTREG_X30,
172  INTREG_X31,
173 
174  INTREG_SPX = NUM_INTREGS,
175 
176  /* All the aliased indexes. */
177 
178  /* USR mode */
179  INTREG_R0_USR = INTREG_R0,
180  INTREG_R1_USR = INTREG_R1,
181  INTREG_R2_USR = INTREG_R2,
182  INTREG_R3_USR = INTREG_R3,
183  INTREG_R4_USR = INTREG_R4,
184  INTREG_R5_USR = INTREG_R5,
185  INTREG_R6_USR = INTREG_R6,
186  INTREG_R7_USR = INTREG_R7,
187  INTREG_R8_USR = INTREG_R8,
188  INTREG_R9_USR = INTREG_R9,
189  INTREG_R10_USR = INTREG_R10,
190  INTREG_R11_USR = INTREG_R11,
191  INTREG_R12_USR = INTREG_R12,
192  INTREG_R13_USR = INTREG_R13,
193  INTREG_SP_USR = INTREG_SP,
194  INTREG_R14_USR = INTREG_R14,
195  INTREG_LR_USR = INTREG_LR,
196  INTREG_R15_USR = INTREG_R15,
197  INTREG_PC_USR = INTREG_PC,
198 
199  /* SVC mode */
200  INTREG_R0_SVC = INTREG_R0,
201  INTREG_R1_SVC = INTREG_R1,
202  INTREG_R2_SVC = INTREG_R2,
203  INTREG_R3_SVC = INTREG_R3,
204  INTREG_R4_SVC = INTREG_R4,
205  INTREG_R5_SVC = INTREG_R5,
206  INTREG_R6_SVC = INTREG_R6,
207  INTREG_R7_SVC = INTREG_R7,
208  INTREG_R8_SVC = INTREG_R8,
209  INTREG_R9_SVC = INTREG_R9,
210  INTREG_R10_SVC = INTREG_R10,
211  INTREG_R11_SVC = INTREG_R11,
212  INTREG_R12_SVC = INTREG_R12,
213  INTREG_PC_SVC = INTREG_PC,
214  INTREG_R15_SVC = INTREG_R15,
215 
216  /* MON mode */
217  INTREG_R0_MON = INTREG_R0,
218  INTREG_R1_MON = INTREG_R1,
219  INTREG_R2_MON = INTREG_R2,
220  INTREG_R3_MON = INTREG_R3,
221  INTREG_R4_MON = INTREG_R4,
222  INTREG_R5_MON = INTREG_R5,
223  INTREG_R6_MON = INTREG_R6,
224  INTREG_R7_MON = INTREG_R7,
225  INTREG_R8_MON = INTREG_R8,
226  INTREG_R9_MON = INTREG_R9,
227  INTREG_R10_MON = INTREG_R10,
228  INTREG_R11_MON = INTREG_R11,
229  INTREG_R12_MON = INTREG_R12,
230  INTREG_PC_MON = INTREG_PC,
231  INTREG_R15_MON = INTREG_R15,
232 
233  /* ABT mode */
234  INTREG_R0_ABT = INTREG_R0,
235  INTREG_R1_ABT = INTREG_R1,
236  INTREG_R2_ABT = INTREG_R2,
237  INTREG_R3_ABT = INTREG_R3,
238  INTREG_R4_ABT = INTREG_R4,
239  INTREG_R5_ABT = INTREG_R5,
240  INTREG_R6_ABT = INTREG_R6,
241  INTREG_R7_ABT = INTREG_R7,
242  INTREG_R8_ABT = INTREG_R8,
243  INTREG_R9_ABT = INTREG_R9,
244  INTREG_R10_ABT = INTREG_R10,
245  INTREG_R11_ABT = INTREG_R11,
246  INTREG_R12_ABT = INTREG_R12,
247  INTREG_PC_ABT = INTREG_PC,
248  INTREG_R15_ABT = INTREG_R15,
249 
250  /* HYP mode */
251  INTREG_R0_HYP = INTREG_R0,
252  INTREG_R1_HYP = INTREG_R1,
253  INTREG_R2_HYP = INTREG_R2,
254  INTREG_R3_HYP = INTREG_R3,
255  INTREG_R4_HYP = INTREG_R4,
256  INTREG_R5_HYP = INTREG_R5,
257  INTREG_R6_HYP = INTREG_R6,
258  INTREG_R7_HYP = INTREG_R7,
259  INTREG_R8_HYP = INTREG_R8,
260  INTREG_R9_HYP = INTREG_R9,
261  INTREG_R10_HYP = INTREG_R10,
262  INTREG_R11_HYP = INTREG_R11,
263  INTREG_R12_HYP = INTREG_R12,
264  INTREG_LR_HYP = INTREG_LR,
265  INTREG_R14_HYP = INTREG_R14,
266  INTREG_PC_HYP = INTREG_PC,
267  INTREG_R15_HYP = INTREG_R15,
268 
269  /* UND mode */
270  INTREG_R0_UND = INTREG_R0,
271  INTREG_R1_UND = INTREG_R1,
272  INTREG_R2_UND = INTREG_R2,
273  INTREG_R3_UND = INTREG_R3,
274  INTREG_R4_UND = INTREG_R4,
275  INTREG_R5_UND = INTREG_R5,
276  INTREG_R6_UND = INTREG_R6,
277  INTREG_R7_UND = INTREG_R7,
278  INTREG_R8_UND = INTREG_R8,
279  INTREG_R9_UND = INTREG_R9,
280  INTREG_R10_UND = INTREG_R10,
281  INTREG_R11_UND = INTREG_R11,
282  INTREG_R12_UND = INTREG_R12,
283  INTREG_PC_UND = INTREG_PC,
284  INTREG_R15_UND = INTREG_R15,
285 
286  /* IRQ mode */
287  INTREG_R0_IRQ = INTREG_R0,
288  INTREG_R1_IRQ = INTREG_R1,
289  INTREG_R2_IRQ = INTREG_R2,
290  INTREG_R3_IRQ = INTREG_R3,
291  INTREG_R4_IRQ = INTREG_R4,
292  INTREG_R5_IRQ = INTREG_R5,
293  INTREG_R6_IRQ = INTREG_R6,
294  INTREG_R7_IRQ = INTREG_R7,
295  INTREG_R8_IRQ = INTREG_R8,
296  INTREG_R9_IRQ = INTREG_R9,
297  INTREG_R10_IRQ = INTREG_R10,
298  INTREG_R11_IRQ = INTREG_R11,
299  INTREG_R12_IRQ = INTREG_R12,
300  INTREG_PC_IRQ = INTREG_PC,
301  INTREG_R15_IRQ = INTREG_R15,
302 
303  /* FIQ mode */
304  INTREG_R0_FIQ = INTREG_R0,
305  INTREG_R1_FIQ = INTREG_R1,
306  INTREG_R2_FIQ = INTREG_R2,
307  INTREG_R3_FIQ = INTREG_R3,
308  INTREG_R4_FIQ = INTREG_R4,
309  INTREG_R5_FIQ = INTREG_R5,
310  INTREG_R6_FIQ = INTREG_R6,
311  INTREG_R7_FIQ = INTREG_R7,
312  INTREG_PC_FIQ = INTREG_PC,
313  INTREG_R15_FIQ = INTREG_R15
314 };
315 
316 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
317 
318 const IntRegMap IntReg64Map = {
319  INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,
320  INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,
321  INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
322  INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
323  INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
324  INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
325  INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
326  INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
327 };
328 
329 const IntRegMap IntRegUsrMap = {
330  INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
331  INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
332  INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
333  INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
334  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
335  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
336  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
337  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
338 };
339 
340 static inline IntRegIndex
341 INTREG_USR(unsigned index)
342 {
343  assert(index < NUM_ARCH_INTREGS);
344  return IntRegUsrMap[index];
345 }
346 
347 const IntRegMap IntRegHypMap = {
348  INTREG_R0_HYP, INTREG_R1_HYP, INTREG_R2_HYP, INTREG_R3_HYP,
349  INTREG_R4_HYP, INTREG_R5_HYP, INTREG_R6_HYP, INTREG_R7_HYP,
350  INTREG_R8_HYP, INTREG_R9_HYP, INTREG_R10_HYP, INTREG_R11_HYP,
351  INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
352  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
353  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
354  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
355  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
356 };
357 
358 static inline IntRegIndex
359 INTREG_HYP(unsigned index)
360 {
361  assert(index < NUM_ARCH_INTREGS);
362  return IntRegHypMap[index];
363 }
364 
365 const IntRegMap IntRegSvcMap = {
366  INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
367  INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
368  INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
369  INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
370  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
371  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
372  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
373  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
374 };
375 
376 static inline IntRegIndex
377 INTREG_SVC(unsigned index)
378 {
379  assert(index < NUM_ARCH_INTREGS);
380  return IntRegSvcMap[index];
381 }
382 
383 const IntRegMap IntRegMonMap = {
384  INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
385  INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
386  INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
387  INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
388  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
389  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
390  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
391  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
392 };
393 
394 static inline IntRegIndex
395 INTREG_MON(unsigned index)
396 {
397  assert(index < NUM_ARCH_INTREGS);
398  return IntRegMonMap[index];
399 }
400 
401 const IntRegMap IntRegAbtMap = {
402  INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
403  INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
404  INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
405  INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
406  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
407  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
408  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
409  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
410 };
411 
412 static inline IntRegIndex
413 INTREG_ABT(unsigned index)
414 {
415  assert(index < NUM_ARCH_INTREGS);
416  return IntRegAbtMap[index];
417 }
418 
419 const IntRegMap IntRegUndMap = {
420  INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
421  INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
422  INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
423  INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
424  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
425  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
426  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
427  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
428 };
429 
430 static inline IntRegIndex
431 INTREG_UND(unsigned index)
432 {
433  assert(index < NUM_ARCH_INTREGS);
434  return IntRegUndMap[index];
435 }
436 
437 const IntRegMap IntRegIrqMap = {
438  INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
439  INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
440  INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
441  INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
442  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
443  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
444  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
445  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
446 };
447 
448 static inline IntRegIndex
449 INTREG_IRQ(unsigned index)
450 {
451  assert(index < NUM_ARCH_INTREGS);
452  return IntRegIrqMap[index];
453 }
454 
455 const IntRegMap IntRegFiqMap = {
456  INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
457  INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
458  INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
459  INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
460  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
461  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
462  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
463  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
464 };
465 
466 static inline IntRegIndex
467 INTREG_FIQ(unsigned index)
468 {
469  assert(index < NUM_ARCH_INTREGS);
470  return IntRegFiqMap[index];
471 }
472 
473 static const unsigned intRegsPerMode = NUM_INTREGS;
474 
475 static inline int
476 intRegInMode(OperatingMode mode, int reg)
477 {
478  assert(reg < NUM_ARCH_INTREGS);
479  return mode * intRegsPerMode + reg;
480 }
481 
482 static inline int
483 flattenIntRegModeIndex(int reg)
484 {
485  int mode = reg / intRegsPerMode;
486  reg = reg % intRegsPerMode;
487  switch (mode) {
488  case MODE_USER:
489  case MODE_SYSTEM:
490  return INTREG_USR(reg);
491  case MODE_FIQ:
492  return INTREG_FIQ(reg);
493  case MODE_IRQ:
494  return INTREG_IRQ(reg);
495  case MODE_SVC:
496  return INTREG_SVC(reg);
497  case MODE_MON:
498  return INTREG_MON(reg);
499  case MODE_ABORT:
500  return INTREG_ABT(reg);
501  case MODE_HYP:
502  return INTREG_HYP(reg);
503  case MODE_UNDEFINED:
504  return INTREG_UND(reg);
505  default:
506  panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
507  curTick(), reg, mode);
508  }
509 }
510 
511 
512 static inline IntRegIndex
513 makeSP(IntRegIndex reg)
514 {
515  if (reg == INTREG_X31)
516  reg = INTREG_SPX;
517  return reg;
518 }
519 
520 static inline IntRegIndex
521 makeZero(IntRegIndex reg)
522 {
523  if (reg == INTREG_X31)
524  reg = INTREG_ZERO;
525  return reg;
526 }
527 
528 static inline bool
529 isSP(IntRegIndex reg)
530 {
531  return reg == INTREG_SPX;
532 }
533 
534 // Semantically meaningful register indices
535 const int ReturnValueReg = 0;
536 const int ReturnValueReg1 = 1;
537 const int ReturnValueReg2 = 2;
538 const int NumArgumentRegs = 4;
539 const int NumArgumentRegs64 = 8;
540 const int ArgumentReg0 = 0;
541 const int ArgumentReg1 = 1;
542 const int ArgumentReg2 = 2;
543 const int ArgumentReg3 = 3;
544 const int FramePointerReg = 11;
545 const int StackPointerReg = INTREG_SP;
546 const int ReturnAddressReg = INTREG_LR;
547 const int PCReg = INTREG_PC;
548 
549 const int SyscallNumReg = ReturnValueReg;
550 const int SyscallPseudoReturnReg = ReturnValueReg;
551 const int SyscallSuccessReg = ReturnValueReg;
552 
553 } // namespace ArmISA
554 } // namespace gem5
555 
556 #endif
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::ArgumentReg3
const int ArgumentReg3
Definition: int.hh:543
gem5::ArmISA::FramePointerReg
const int FramePointerReg
Definition: int.hh:544
gem5::ArmISA::intRegInMode
static int intRegInMode(OperatingMode mode, int reg)
Definition: int.hh:476
gem5::ArmISA::INTREG_FIQ
static IntRegIndex INTREG_FIQ(unsigned index)
Definition: int.hh:467
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::INTREG_MON
static IntRegIndex INTREG_MON(unsigned index)
Definition: int.hh:395
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::NumArgumentRegs64
const int NumArgumentRegs64
Definition: int.hh:539
gem5::ArmISA::isSP
static bool isSP(IntRegIndex reg)
Definition: int.hh:529
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::ArgumentReg0
const int ArgumentReg0
Definition: int.hh:540
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::INTREG_SVC
static IntRegIndex INTREG_SVC(unsigned index)
Definition: int.hh:377
gem5::ArmISA::IntRegMap
IntRegIndex IntRegMap[NUM_ARCH_INTREGS]
Definition: int.hh:314
gem5::ArmISA::INTREG_UND
static IntRegIndex INTREG_UND(unsigned index)
Definition: int.hh:431
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::INTREG_USR
static IntRegIndex INTREG_USR(unsigned index)
Definition: int.hh:341
gem5::ArmISA::INTREG_HYP
static IntRegIndex INTREG_HYP(unsigned index)
Definition: int.hh:359
gem5::ArmISA::IntRegFiqMap
const IntRegMap IntRegFiqMap
Definition: int.hh:455
gem5::ArmISA::ReturnAddressReg
const int ReturnAddressReg
Definition: int.hh:546
gem5::ArmISA::IntRegUsrMap
const IntRegMap IntRegUsrMap
Definition: int.hh:329
gem5::ArmISA::NumArgumentRegs
const int NumArgumentRegs
Definition: int.hh:538
gem5::ArmISA::ReturnValueReg1
const int ReturnValueReg1
Definition: int.hh:536
types.hh
gem5::ArmISA::ArgumentReg2
const int ArgumentReg2
Definition: int.hh:542
gem5::ArmISA::uw
Bitfield< 31, 0 > uw
Definition: int.hh:61
gem5::ArmISA::IntReg64Map
const IntRegMap IntReg64Map
Definition: int.hh:318
gem5::SparcISA::INTREG_UREG0
@ INTREG_UREG0
Definition: int.hh:57
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::BitUnion32
BitUnion32(PackedIntReg) Bitfield< 31
gem5::ArmISA::IntRegSvcMap
const IntRegMap IntRegSvcMap
Definition: int.hh:365
gem5::ArmISA::makeZero
static IntRegIndex makeZero(IntRegIndex reg)
Definition: int.hh:521
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::sw
SignedBitfield< 31, 0 > sw
Definition: int.hh:62
gem5::ArmISA::SyscallSuccessReg
const int SyscallSuccessReg
Definition: int.hh:551
gem5::ArmISA::IntRegUndMap
const IntRegMap IntRegUndMap
Definition: int.hh:419
core.hh
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::ArmISA::SyscallPseudoReturnReg
const int SyscallPseudoReturnReg
Definition: int.hh:550
gem5::ArmISA::IntRegAbtMap
const IntRegMap IntRegAbtMap
Definition: int.hh:401
gem5::ArmISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:545
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::makeSP
static IntRegIndex makeSP(IntRegIndex reg)
Definition: int.hh:513
gem5::ArmISA::uh1
uh1
Definition: int.hh:57
gem5::ArmISA::INTREG_IRQ
static IntRegIndex INTREG_IRQ(unsigned index)
Definition: int.hh:449
gem5::ArmISA::EndBitUnion
EndBitUnion(PackedIntReg) enum IntRegIndex
Definition: int.hh:63
gem5::ArmISA::IntRegIrqMap
const IntRegMap IntRegIrqMap
Definition: int.hh:437
gem5::ArmISA::INTREG_ABT
static IntRegIndex INTREG_ABT(unsigned index)
Definition: int.hh:413
gem5::ArmISA::ReturnValueReg2
const int ReturnValueReg2
Definition: int.hh:537
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::intRegsPerMode
static const unsigned intRegsPerMode
Definition: int.hh:473
gem5::ArmISA::flattenIntRegModeIndex
static int flattenIntRegModeIndex(int reg)
Definition: int.hh:483
logging.hh
gem5::ArmISA::ArgumentReg1
const int ArgumentReg1
Definition: int.hh:541
gem5::ArmISA::IntRegHypMap
const IntRegMap IntRegHypMap
Definition: int.hh:347
gem5::ArmISA::uh0
Bitfield< 15, 0 > uh0
Definition: int.hh:58
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::SyscallNumReg
const int SyscallNumReg
Definition: int.hh:549
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::sh1
SignedBitfield< 31, 16 > sh1
Definition: int.hh:59
gem5::ArmISA::ReturnValueReg
const int ReturnValueReg
Definition: int.hh:535
gem5::ArmISA::IntRegMonMap
const IntRegMap IntRegMonMap
Definition: int.hh:383
gem5::ArmISA::PCReg
const int PCReg
Definition: int.hh:547
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::sh0
SignedBitfield< 15, 0 > sh0
Definition: int.hh:60
Generated on Tue Sep 21 2021 12:24:37 for gem5 by doxygen 1.8.17