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v21.1.0.2
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arch
null
vecregs.hh
Go to the documentation of this file.
1
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_NULL_VECREGS_HH__
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#define __ARCH_NULL_VECREGS_HH__
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#include <cstdint>
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#include "
arch/generic/types.hh
"
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#include "
arch/generic/vec_pred_reg.hh
"
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#include "
arch/generic/vec_reg.hh
"
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namespace
gem5
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{
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namespace
NullISA
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{
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// Not applicable to null
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using
VecElem
=
::gem5::DummyVecElem
;
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using
VecRegContainer
=
::gem5::DummyVecRegContainer
;
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constexpr
unsigned
NumVecElemPerVecReg
=
::gem5::DummyNumVecElemPerVecReg
;
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// Not applicable to null
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using
VecPredRegContainer
=
::gem5::DummyVecPredRegContainer
;
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}
// namespace NullISA
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}
// namespace gem5
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#endif // __ARCH_NULL_VECREGS_HH__
gem5::VecPredRegContainer
Generic predicate register container.
Definition:
vec_pred_reg.hh:53
gem5::DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition:
vec_reg.hh:266
gem5::NullISA::VecElem
::gem5::DummyVecElem VecElem
Definition:
vecregs.hh:54
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition:
vec_reg.hh:121
vec_pred_reg.hh
vec_reg.hh
types.hh
gem5::DummyVecRegContainer
VecRegContainer< DummyNumVecElemPerVecReg *sizeof(DummyVecElem)> DummyVecRegContainer
Definition:
vec_reg.hh:269
gem5::NullISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition:
vecregs.hh:56
gem5::DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition:
vec_reg.hh:267
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
decoder.cc:40
gem5::DummyVecPredRegContainer
VecPredRegContainer< 8, false > DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition:
vec_pred_reg.hh:395
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