pcstate.hh

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/*
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __ARCH_POWER_PCSTATE_HH__
#define __ARCH_POWER_PCSTATE_HH__
 
#include "arch/generic/types.hh"
#include "arch/power/types.hh"
#include "enums/ByteOrder.hh"
 
namespace gem5
{
 
namespace PowerISA
{
 
class PCState : public GenericISA::SimplePCState<4>
{
  private:
    typedef GenericISA::SimplePCState<4> Base;
    ByteOrder guestByteOrder = ByteOrder::big;
 
  public:
    PCState()
    {}
 
    void
    set(Addr val)
    {
        Base::set(val);
        npc(val + 4);
    }
 
    PCState(Addr val)
    {
        set(val);
    }
 
    ByteOrder
    byteOrder() const
    {
        return guestByteOrder;
    }
 
    void
    byteOrder(ByteOrder order)
    {
        guestByteOrder = order;
    }
};
 
} // namespace PowerISA
} // namespace gem5
 
#endif // __ARCH_POWER_PCSTATE_HH__