gem5::SimpleThread Class Reference

The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface. More...

#include <simple_thread.hh>

Inheritance diagram for gem5::SimpleThread:

Public Types
typedef ThreadContext::Status	Status
Public Types inherited from gem5::ThreadState
typedef ThreadContext::Status	Status
Public Types inherited from gem5::ThreadContext
enum	Status { Active, Suspended, Halting, Halted }

Public Member Functions
std::string	name () const
	SimpleThread (BaseCPU *_cpu, int _thread_num, System *_system, BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
	SimpleThread (BaseCPU *_cpu, int _thread_num, System *_system, Process *_process, BaseMMU *_mmu, BaseISA *_isa, InstDecoder *_decoder)
virtual	~SimpleThread ()
void	takeOverFrom (ThreadContext *oldContext) override
void	copyState (ThreadContext *oldContext)
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
ThreadContext *	getTC ()
	Returns the pointer to this SimpleThread's ThreadContext. More...
void	demapPage (Addr vaddr, uint64_t asn)
bool	schedule (PCEvent *e) override
bool	remove (PCEvent *e) override
void	scheduleInstCountEvent (Event *event, Tick count) override
void	descheduleInstCountEvent (Event *event) override
Tick	getCurrentInstCount () override
BaseCPU *	getCpuPtr () override
int	cpuId () const override
uint32_t	socketId () const override
int	threadId () const override
void	setThreadId (int id) override
ContextID	contextId () const override
void	setContextId (ContextID id) override
BaseMMU *	getMMUPtr () override
CheckerCPU *	getCheckerCpuPtr () override
BaseISA *	getIsaPtr () override
InstDecoder *	getDecoderPtr () override
System *	getSystemPtr () override
Process *	getProcessPtr () override
void	setProcessPtr (Process *p) override
Status	status () const override
void	setStatus (Status newStatus) override
void	activate () override
	Set the status to Active. More...
void	suspend () override
	Set the status to Suspended. More...
void	halt () override
	Set the status to Halted. More...
Tick	readLastActivate () override
Tick	readLastSuspend () override
void	copyArchRegs (ThreadContext *tc) override
void	clearArchRegs () override
RegVal	readIntReg (RegIndex reg_idx) const override
RegVal	readFloatReg (RegIndex reg_idx) const override
const TheISA::VecRegContainer &	readVecReg (const RegId &reg) const override
TheISA::VecRegContainer &	getWritableVecReg (const RegId &reg) override
RegVal	readVecElem (const RegId &reg) const override
const TheISA::VecPredRegContainer &	readVecPredReg (const RegId &reg) const override
TheISA::VecPredRegContainer &	getWritableVecPredReg (const RegId &reg) override
RegVal	readCCReg (RegIndex reg_idx) const override
void	setIntReg (RegIndex reg_idx, RegVal val) override
void	setFloatReg (RegIndex reg_idx, RegVal val) override
void	setVecReg (const RegId &reg, const TheISA::VecRegContainer &val) override
void	setVecElem (const RegId &reg, RegVal val) override
void	setVecPredReg (const RegId &reg, const TheISA::VecPredRegContainer &val) override
void	setCCReg (RegIndex reg_idx, RegVal val) override
const PCStateBase &	pcState () const override
void	pcState (const PCStateBase &val) override
void	pcStateNoRecord (const PCStateBase &val) override
bool	readPredicate () const
void	setPredicate (bool val)
RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override
RegVal	readMiscReg (RegIndex misc_reg) override
void	setMiscRegNoEffect (RegIndex misc_reg, RegVal val) override
void	setMiscReg (RegIndex misc_reg, RegVal val) override
RegId	flattenRegId (const RegId &regId) const override
unsigned	readStCondFailures () const override
bool	readMemAccPredicate ()
void	setMemAccPredicate (bool val)
void	setStCondFailures (unsigned sc_failures) override
RegVal	readIntRegFlat (RegIndex idx) const override
	Flat register interfaces. More...
void	setIntRegFlat (RegIndex idx, RegVal val) override
RegVal	readFloatRegFlat (RegIndex idx) const override
void	setFloatRegFlat (RegIndex idx, RegVal val) override
const TheISA::VecRegContainer &	readVecRegFlat (RegIndex reg) const override
TheISA::VecRegContainer &	getWritableVecRegFlat (RegIndex reg) override
void	setVecRegFlat (RegIndex reg, const TheISA::VecRegContainer &val) override
RegVal	readVecElemFlat (RegIndex reg, const ElemIndex &elemIndex) const override
void	setVecElemFlat (RegIndex reg, const ElemIndex &elemIndex, RegVal val) override
const TheISA::VecPredRegContainer &	readVecPredRegFlat (RegIndex reg) const override
TheISA::VecPredRegContainer &	getWritableVecPredRegFlat (RegIndex reg) override
void	setVecPredRegFlat (RegIndex reg, const TheISA::VecPredRegContainer &val) override
RegVal	readCCRegFlat (RegIndex idx) const override
void	setCCRegFlat (RegIndex idx, RegVal val) override
void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override
BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override
void	setHtmCheckpointPtr (BaseHTMCheckpointPtr new_cpt) override
Public Member Functions inherited from gem5::ThreadState
	ThreadState (BaseCPU *cpu, ThreadID _tid, Process *_process)
virtual	~ThreadState ()=default
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
int	cpuId () const
uint32_t	socketId () const
ContextID	contextId () const
void	setContextId (ContextID id)
void	setThreadId (ThreadID id)
ThreadID	threadId () const
Tick	readLastActivate () const
Tick	readLastSuspend () const
Process *	getProcessPtr ()
void	setProcessPtr (Process *p)
Status	status () const
	Returns the status of this thread. More...
void	setStatus (Status new_status)
	Sets the status of this thread. More...
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()
void	setUseForClone (bool new_val)
virtual	~ThreadContext ()
virtual void	sendFunctional (PacketPtr pkt)
void	quiesce ()
	Quiesce thread context. More...
void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume. More...
virtual void	regStats (const std::string &name)
void	pcState (Addr addr)
virtual int	exit ()

Public Attributes
PCEventQueue	pcEventQueue
EventQueue	comInstEventQueue
	An instruction-based event queue. More...
System *	system
BaseMMU *	mmu
InstDecoder *	decoder
int64_t	htmTransactionStarts
int64_t	htmTransactionStops
Public Attributes inherited from gem5::ThreadState
Counter	numInst
	Number of instructions committed. More...
Counter	numOp
	Number of ops (including micro ops) committed. More...
gem5::ThreadState::ThreadStateStats	threadStats
Counter	numLoad
	Number of simulated loads, used for tracking events based on the number of loads committed. More...
Counter	startNumLoad
	The number of simulated loads committed prior to this run. More...
Tick	lastActivate
	Last time activate was called on this thread. More...
Tick	lastSuspend
	Last time suspend was called on this thread. More...
unsigned	storeCondFailures
Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult
double	floatResult = DefaultFloatResult
int	intOffset = 0

Protected Attributes
std::vector< RegVal >	floatRegs
std::vector< RegVal >	intRegs
std::vector< TheISA::VecRegContainer >	vecRegs
std::vector< RegVal >	vecElemRegs
std::vector< TheISA::VecPredRegContainer >	vecPredRegs
std::vector< RegVal >	ccRegs
TheISA::ISA *const	isa
std::unique_ptr< PCStateBase >	_pcState
std::unique_ptr< BaseHTMCheckpoint >	_htmCheckpoint
bool	predicate
	Did this instruction execute or is it predicated false. More...
bool	memAccPredicate
	True if the memory access should be skipped for this instruction. More...
Protected Attributes inherited from gem5::ThreadState
ThreadContext::Status	_status
BaseCPU *	baseCpu
ContextID	_contextId
ThreadID	_threadId
Process *	process
Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Additional Inherited Members
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...
Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext *one, ThreadContext *two)
	function to compare two thread contexts (for debugging) More...
Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []
static const double	floats []
static const int	DefaultIntResult = 0
static const double	DefaultFloatResult = 0.0

Detailed Description

The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface.

It implements the ThreadContext interface and adds to the ThreadState object by adding all the objects needed for simple functional execution, including a simple architectural register file, and pointers to the ITB and DTB in full system mode. For CPU models that do not need more advanced ways to hold state (i.e. a separate physical register file, or separate fetch and commit PC's), this SimpleThread class provides all the necessary state for full architecture-level functional simulation. See the AtomicSimpleCPU or TimingSimpleCPU for examples.

Definition at line 93 of file simple_thread.hh.

Member Typedef Documentation

Status

typedef ThreadContext::Status gem5::SimpleThread::Status

Definition at line 96 of file simple_thread.hh.

Constructor & Destructor Documentation

SimpleThread() [1/2]

gem5::SimpleThread::SimpleThread	(	BaseCPU *	_cpu,
		int	_thread_num,
		System *	_system,
		BaseMMU *	_mmu,
		BaseISA *	_isa,
		InstDecoder *	_decoder
	)

Definition at line 90 of file simple_thread.cc.

SimpleThread() [2/2]

gem5::SimpleThread::SimpleThread	(	BaseCPU *	_cpu,
		int	_thread_num,
		System *	_system,
		Process *	_process,
		BaseMMU *	_mmu,
		BaseISA *	_isa,
		InstDecoder *	_decoder
	)

Definition at line 69 of file simple_thread.cc.

References gem5::CCRegClass, ccRegs, clearArchRegs(), gem5::FloatRegClass, floatRegs, gem5::IntRegClass, intRegs, isa, gem5::VecElemClass, vecElemRegs, gem5::VecPredRegClass, vecPredRegs, gem5::VecRegClass, and vecRegs.

~SimpleThread()

virtual gem5::SimpleThread::~SimpleThread ( )

inlinevirtual

Definition at line 151 of file simple_thread.hh.

Member Function Documentation

activate()

void gem5::SimpleThread::activate ( )

overridevirtual

Set the status to Active.

Implements gem5::ThreadContext.

Definition at line 133 of file simple_thread.cc.

References gem5::ThreadState::_status, gem5::ThreadState::_threadId, gem5::ThreadContext::Active, gem5::ThreadState::baseCpu, gem5::curTick(), gem5::ThreadState::lastActivate, and status().

Referenced by gem5::BaseKvmCPU::wakeup().

clearArchRegs()

void gem5::SimpleThread::clearArchRegs ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 249 of file simple_thread.hh.

References _pcState, ccRegs, gem5::MipsISA::fill, floatRegs, intRegs, isa, vecElemRegs, vecPredRegs, and vecRegs.

Referenced by gem5::CheckerThreadContext< TC >::clearArchRegs(), and SimpleThread().

contextId()

ContextID gem5::SimpleThread::contextId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 206 of file simple_thread.hh.

References gem5::ThreadState::contextId().

Referenced by gem5::minor::ExecContext::contextId(), gem5::TimingSimpleCPU::fetch(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateHtmCmd(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), and gem5::TimingSimpleCPU::writeMem().

copyArchRegs()

void gem5::SimpleThread::copyArchRegs ( ThreadContext *  tc )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 167 of file simple_thread.cc.

References gem5::BaseISA::copyRegsFrom(), and getIsaPtr().

Referenced by gem5::CheckerThreadContext< TC >::copyArchRegs(), and copyState().

copyState()

void gem5::SimpleThread::copyState

(

ThreadContext *

oldContext

)

Definition at line 107 of file simple_thread.cc.

References gem5::ThreadState::_contextId, gem5::ThreadState::_status, gem5::ThreadState::_threadId, gem5::ThreadContext::contextId(), copyArchRegs(), gem5::ThreadContext::status(), and gem5::ThreadContext::threadId().

Referenced by gem5::CheckerThreadContext< TC >::takeOverFrom().

cpuId()

int gem5::SimpleThread::cpuId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 202 of file simple_thread.hh.

References gem5::ThreadState::cpuId().

demapPage()

void gem5::SimpleThread::demapPage ( Addr  vaddr, uint64_t  asn  )

inline

Definition at line 172 of file simple_thread.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

Referenced by gem5::SimpleExecContext::demapPage().

descheduleInstCountEvent()

void gem5::SimpleThread::descheduleInstCountEvent ( Event *  event )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 190 of file simple_thread.hh.

References comInstEventQueue, gem5::EventQueue::deschedule(), and gem5::MipsISA::event.

flattenRegId()

RegId gem5::SimpleThread::flattenRegId ( const RegId &  regId ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 459 of file simple_thread.hh.

References isa.

getCheckerCpuPtr()

CheckerCPU* gem5::SimpleThread::getCheckerCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 211 of file simple_thread.hh.

getCpuPtr()

BaseCPU* gem5::SimpleThread::getCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 200 of file simple_thread.hh.

References gem5::ThreadState::baseCpu.

getCurrentInstCount()

Tick gem5::SimpleThread::getCurrentInstCount ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 195 of file simple_thread.hh.

References comInstEventQueue, and gem5::EventQueue::getCurTick().

getDecoderPtr()

InstDecoder* gem5::SimpleThread::getDecoderPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 215 of file simple_thread.hh.

References decoder.

getHtmCheckpointPtr()

BaseHTMCheckpointPtr & gem5::SimpleThread::getHtmCheckpointPtr ( )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 184 of file simple_thread.cc.

References _htmCheckpoint.

getIsaPtr()

BaseISA* gem5::SimpleThread::getIsaPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 213 of file simple_thread.hh.

References isa.

Referenced by copyArchRegs(), gem5::TimingSimpleCPU::handleReadPacket(), gem5::AtomicSimpleCPU::readMem(), gem5::TimingSimpleCPU::sendData(), gem5::minor::LSQ::tryToSendToTransfers(), and gem5::AtomicSimpleCPU::writeMem().

getMMUPtr()

BaseMMU* gem5::SimpleThread::getMMUPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 209 of file simple_thread.hh.

References mmu.

Referenced by gem5::minor::ExecContext::demapPage().

getProcessPtr()

Process* gem5::SimpleThread::getProcessPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 219 of file simple_thread.hh.

References gem5::ThreadState::getProcessPtr().

getSystemPtr()

System* gem5::SimpleThread::getSystemPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 217 of file simple_thread.hh.

References system.

getTC()

ThreadContext* gem5::SimpleThread::getTC ( )

inline

Returns the pointer to this SimpleThread's ThreadContext.

Used when a ThreadContext must be passed to objects outside of the CPU.

Definition at line 169 of file simple_thread.hh.

Referenced by gem5::AtomicSimpleCPU::amoMem(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::BaseKvmCPU::doMMIOAccess(), gem5::TimingSimpleCPU::fetch(), gem5::TimingSimpleCPU::handleReadPacket(), gem5::TimingSimpleCPU::handleWritePacket(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::MinorCPU::MinorCPU(), gem5::BaseSimpleCPU::preExecute(), gem5::AtomicSimpleCPU::readMem(), gem5::CheckerCPU::setSystem(), gem5::minor::ExecContext::tcBase(), gem5::SimpleExecContext::tcBase(), gem5::AtomicSimpleCPU::tick(), gem5::AtomicSimpleCPU::writeMem(), and gem5::TimingSimpleCPU::writeMem().

getWritableVecPredReg()

TheISA::VecPredRegContainer& gem5::SimpleThread::getWritableVecPredReg ( const RegId &  reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 334 of file simple_thread.hh.

References DPRINTF, getWritableVecPredRegFlat(), isa, gem5::X86ISA::reg, and vecPredRegs.

Referenced by gem5::minor::ExecContext::getWritableVecPredRegOperand(), gem5::CheckerCPU::getWritableVecPredRegOperand(), and gem5::SimpleExecContext::getWritableVecPredRegOperand().

getWritableVecPredRegFlat()

TheISA::VecPredRegContainer& gem5::SimpleThread::getWritableVecPredRegFlat ( RegIndex  reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 540 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecPredRegs.

Referenced by getWritableVecPredReg().

getWritableVecReg()

TheISA::VecRegContainer& gem5::SimpleThread::getWritableVecReg ( const RegId &  reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 300 of file simple_thread.hh.

References DPRINTF, getWritableVecRegFlat(), isa, gem5::X86ISA::reg, and vecRegs.

Referenced by gem5::minor::ExecContext::getWritableVecRegOperand(), gem5::CheckerCPU::getWritableVecRegOperand(), and gem5::SimpleExecContext::getWritableVecRegOperand().

getWritableVecRegFlat()

TheISA::VecRegContainer& gem5::SimpleThread::getWritableVecRegFlat ( RegIndex  reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 509 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecRegs.

Referenced by getWritableVecReg().

halt()

void gem5::SimpleThread::halt ( )

overridevirtual

Set the status to Halted.

Implements gem5::ThreadContext.

Definition at line 157 of file simple_thread.cc.

References gem5::ThreadState::_status, gem5::ThreadState::_threadId, gem5::ThreadState::baseCpu, gem5::ThreadContext::Halted, and status().

htmAbortTransaction()

void gem5::SimpleThread::htmAbortTransaction ( uint64_t  htm_uid, HtmFailureFaultCause  cause  )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 174 of file simple_thread.cc.

References gem5::ThreadState::baseCpu, htmTransactionStarts, htmTransactionStops, and threadId().

name()

std::string gem5::SimpleThread::name ( ) const

inline

Definition at line 120 of file simple_thread.hh.

References gem5::ThreadState::baseCpu, gem5::csprintf(), and threadId().

pcState() [1/2]

const PCStateBase& gem5::SimpleThread::pcState ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 422 of file simple_thread.hh.

References _pcState.

Referenced by gem5::BaseSimpleCPU::advancePC(), gem5::AtomicSimpleCPU::amoMem(), gem5::minor::LSQ::LSQRequest::completeDisabledMemAccess(), gem5::CheckerCPU::dumpAndExit(), gem5::TimingSimpleCPU::fetch(), gem5::CheckerCPU::genMemFragmentRequest(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateHtmCmd(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::AtomicSimpleCPU::isCpuDrained(), gem5::TimingSimpleCPU::isCpuDrained(), gem5::minor::ExecContext::pcState(), gem5::CheckerThreadContext< TC >::pcState(), gem5::CheckerCPU::pcState(), gem5::SimpleExecContext::pcState(), gem5::BaseSimpleCPU::preExecute(), gem5::SimPoint::profile(), gem5::BaseSimpleCPU::setupFetchRequest(), gem5::TimingSimpleCPU::switchOut(), gem5::AtomicSimpleCPU::tick(), gem5::minor::LSQ::tryToSendToTransfers(), gem5::minor::LSQ::LSQRequest::tryToSuppressFault(), and gem5::TimingSimpleCPU::writeMem().

pcState() [2/2]

void gem5::SimpleThread::pcState ( const PCStateBase &  val )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 423 of file simple_thread.hh.

References _pcState, and gem5::X86ISA::val.

pcStateNoRecord()

void gem5::SimpleThread::pcStateNoRecord ( const PCStateBase &  val )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 426 of file simple_thread.hh.

References _pcState, and gem5::X86ISA::val.

readCCReg()

RegVal gem5::SimpleThread::readCCReg ( RegIndex  reg_idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 347 of file simple_thread.hh.

References ccRegs, DPRINTF, isa, and readCCRegFlat().

Referenced by gem5::CheckerCPU::readCCRegOperand(), gem5::minor::ExecContext::readCCRegOperand(), and gem5::SimpleExecContext::readCCRegOperand().

readCCRegFlat()

RegVal gem5::SimpleThread::readCCRegFlat ( RegIndex  idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 552 of file simple_thread.hh.

References ccRegs.

Referenced by readCCReg().

readFloatReg()

RegVal gem5::SimpleThread::readFloatReg ( RegIndex  reg_idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 278 of file simple_thread.hh.

References DPRINTF, floatRegs, isa, and readFloatRegFlat().

Referenced by gem5::minor::ExecContext::readFloatRegOperandBits(), gem5::CheckerCPU::readFloatRegOperandBits(), and gem5::SimpleExecContext::readFloatRegOperandBits().

readFloatRegFlat()

RegVal gem5::SimpleThread::readFloatRegFlat ( RegIndex  idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 492 of file simple_thread.hh.

References floatRegs.

Referenced by readFloatReg().

readIntReg()

RegVal gem5::SimpleThread::readIntReg ( RegIndex  reg_idx ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 267 of file simple_thread.hh.

References DPRINTF, intRegs, isa, and readIntRegFlat().

Referenced by gem5::minor::ExecContext::readIntRegOperand(), gem5::CheckerCPU::readIntRegOperand(), and gem5::SimpleExecContext::readIntRegOperand().

readIntRegFlat()

RegVal gem5::SimpleThread::readIntRegFlat ( RegIndex  idx ) const

inlineoverridevirtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Implements gem5::ThreadContext.

Definition at line 484 of file simple_thread.hh.

References intRegs.

Referenced by readIntReg().

readLastActivate()

Tick gem5::SimpleThread::readLastActivate ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 236 of file simple_thread.hh.

References gem5::ThreadState::readLastActivate().

readLastSuspend()

Tick gem5::SimpleThread::readLastSuspend ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 241 of file simple_thread.hh.

References gem5::ThreadState::readLastSuspend().

readMemAccPredicate()

bool gem5::SimpleThread::readMemAccPredicate ( )

inline

Definition at line 467 of file simple_thread.hh.

References memAccPredicate.

Referenced by gem5::minor::ExecContext::readMemAccPredicate(), gem5::CheckerCPU::readMemAccPredicate(), and gem5::SimpleExecContext::readMemAccPredicate().

readMiscReg()

RegVal gem5::SimpleThread::readMiscReg ( RegIndex  misc_reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 441 of file simple_thread.hh.

References isa.

Referenced by gem5::minor::ExecContext::readMiscReg(), gem5::CheckerCPU::readMiscReg(), gem5::SimpleExecContext::readMiscReg(), gem5::minor::ExecContext::readMiscRegOperand(), gem5::CheckerCPU::readMiscRegOperand(), and gem5::SimpleExecContext::readMiscRegOperand().

readMiscRegNoEffect()

RegVal gem5::SimpleThread::readMiscRegNoEffect ( RegIndex  misc_reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 435 of file simple_thread.hh.

References isa.

Referenced by gem5::minor::ExecContext::readMiscRegNoEffect(), and gem5::CheckerCPU::readMiscRegNoEffect().

readPredicate()

bool gem5::SimpleThread::readPredicate ( ) const

inline

Definition at line 431 of file simple_thread.hh.

References predicate.

Referenced by gem5::minor::ExecContext::readPredicate(), gem5::CheckerCPU::readPredicate(), and gem5::SimpleExecContext::readPredicate().

readStCondFailures()

unsigned gem5::SimpleThread::readStCondFailures ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 464 of file simple_thread.hh.

References gem5::ThreadState::storeCondFailures.

Referenced by gem5::CheckerCPU::readStCondFailures(), and gem5::SimpleExecContext::readStCondFailures().

readVecElem()

RegVal gem5::SimpleThread::readVecElem ( const RegId &  reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 311 of file simple_thread.hh.

References DPRINTF, isa, readVecElemFlat(), gem5::X86ISA::reg, and vecRegs.

Referenced by gem5::minor::ExecContext::readVecElemOperand(), gem5::CheckerCPU::readVecElemOperand(), and gem5::SimpleExecContext::readVecElemOperand().

readVecElemFlat()

RegVal gem5::SimpleThread::readVecElemFlat ( RegIndex  reg, const ElemIndex &  elemIndex  ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 521 of file simple_thread.hh.

References gem5::ArmISA::NumVecElemPerVecReg, gem5::X86ISA::reg, and vecElemRegs.

Referenced by readVecElem().

readVecPredReg()

const TheISA::VecPredRegContainer& gem5::SimpleThread::readVecPredReg ( const RegId &  reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 322 of file simple_thread.hh.

References DPRINTF, isa, readVecPredRegFlat(), gem5::X86ISA::reg, and vecPredRegs.

Referenced by gem5::minor::ExecContext::readVecPredRegOperand(), gem5::CheckerCPU::readVecPredRegOperand(), and gem5::SimpleExecContext::readVecPredRegOperand().

readVecPredRegFlat()

const TheISA::VecPredRegContainer& gem5::SimpleThread::readVecPredRegFlat ( RegIndex  reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 534 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecPredRegs.

Referenced by readVecPredReg().

readVecReg()

const TheISA::VecRegContainer& gem5::SimpleThread::readVecReg ( const RegId &  reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 289 of file simple_thread.hh.

References DPRINTF, isa, readVecRegFlat(), gem5::X86ISA::reg, and vecRegs.

Referenced by gem5::minor::ExecContext::readVecRegOperand(), gem5::CheckerCPU::readVecRegOperand(), and gem5::SimpleExecContext::readVecRegOperand().

readVecRegFlat()

const TheISA::VecRegContainer& gem5::SimpleThread::readVecRegFlat ( RegIndex  reg ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 503 of file simple_thread.hh.

References gem5::X86ISA::reg, and vecRegs.

Referenced by readVecReg().

remove()

bool gem5::SimpleThread::remove ( PCEvent *  e )

inlineoverridevirtual

Implements gem5::PCEventScope.

Definition at line 182 of file simple_thread.hh.

References gem5::ArmISA::e, pcEventQueue, and gem5::PCEventQueue::remove().

Referenced by gem5::CheckerThreadContext< TC >::remove().

schedule()

bool gem5::SimpleThread::schedule ( PCEvent *  e )

inlineoverridevirtual

Implements gem5::PCEventScope.

Definition at line 181 of file simple_thread.hh.

References gem5::ArmISA::e, pcEventQueue, and gem5::PCEventQueue::schedule().

Referenced by gem5::CheckerThreadContext< TC >::schedule().

scheduleInstCountEvent()

void gem5::SimpleThread::scheduleInstCountEvent ( Event *  event, Tick  count  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 185 of file simple_thread.hh.

References comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, and gem5::EventQueue::schedule().

serialize()

void gem5::SimpleThread::serialize ( CheckpointOut &  cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 118 of file simple_thread.cc.

References gem5::ThreadState::serialize(), and gem5::serialize().

Referenced by gem5::BaseKvmCPU::serializeThread().

setCCReg()

void gem5::SimpleThread::setCCReg ( RegIndex  reg_idx, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 413 of file simple_thread.hh.

References ccRegs, DPRINTF, isa, setCCRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::CheckerThreadContext< TC >::setCCReg(), gem5::CheckerCPU::setCCRegOperand(), gem5::minor::ExecContext::setCCRegOperand(), and gem5::SimpleExecContext::setCCRegOperand().

setCCRegFlat()

void gem5::SimpleThread::setCCRegFlat ( RegIndex  idx, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 553 of file simple_thread.hh.

References ccRegs, and gem5::X86ISA::val.

Referenced by setCCReg().

setContextId()

void gem5::SimpleThread::setContextId ( ContextID  id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 207 of file simple_thread.hh.

References gem5::ThreadState::setContextId().

Referenced by gem5::CheckerThreadContext< TC >::setContextId().

setFloatReg()

void gem5::SimpleThread::setFloatReg ( RegIndex  reg_idx, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 369 of file simple_thread.hh.

References DPRINTF, floatRegs, isa, setFloatRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::CheckerThreadContext< TC >::setFloatReg(), gem5::minor::ExecContext::setFloatRegOperandBits(), gem5::CheckerCPU::setFloatRegOperandBits(), and gem5::SimpleExecContext::setFloatRegOperandBits().

setFloatRegFlat()

void gem5::SimpleThread::setFloatRegFlat ( RegIndex  idx, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 497 of file simple_thread.hh.

References floatRegs, and gem5::X86ISA::val.

Referenced by setFloatReg().

setHtmCheckpointPtr()

void gem5::SimpleThread::setHtmCheckpointPtr ( BaseHTMCheckpointPtr  new_cpt )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 190 of file simple_thread.cc.

References _htmCheckpoint.

setIntReg()

void gem5::SimpleThread::setIntReg ( RegIndex  reg_idx, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 359 of file simple_thread.hh.

References DPRINTF, intRegs, isa, setIntRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::minor::ExecContext::ExecContext(), gem5::BaseSimpleCPU::preExecute(), gem5::CheckerThreadContext< TC >::setIntReg(), gem5::minor::ExecContext::setIntRegOperand(), gem5::CheckerCPU::setIntRegOperand(), and gem5::SimpleExecContext::setIntRegOperand().

setIntRegFlat()

void gem5::SimpleThread::setIntRegFlat ( RegIndex  idx, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 486 of file simple_thread.hh.

References intRegs, and gem5::X86ISA::val.

Referenced by setIntReg().

setMemAccPredicate()

void gem5::SimpleThread::setMemAccPredicate ( bool  val )

inline

Definition at line 473 of file simple_thread.hh.

References memAccPredicate, and gem5::X86ISA::val.

Referenced by gem5::minor::ExecContext::setMemAccPredicate(), gem5::CheckerCPU::setMemAccPredicate(), and gem5::SimpleExecContext::setMemAccPredicate().

setMiscReg()

void gem5::SimpleThread::setMiscReg ( RegIndex  misc_reg, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 453 of file simple_thread.hh.

References isa, and gem5::X86ISA::val.

Referenced by gem5::minor::ExecContext::setMiscReg(), gem5::CheckerThreadContext< TC >::setMiscReg(), gem5::CheckerCPU::setMiscReg(), gem5::SimpleExecContext::setMiscReg(), gem5::minor::ExecContext::setMiscRegOperand(), and gem5::SimpleExecContext::setMiscRegOperand().

setMiscRegNoEffect()

void gem5::SimpleThread::setMiscRegNoEffect ( RegIndex  misc_reg, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 447 of file simple_thread.hh.

References isa, and gem5::X86ISA::val.

Referenced by gem5::CheckerThreadContext< TC >::setMiscRegNoEffect(), and gem5::CheckerCPU::setMiscRegNoEffect().

setPredicate()

void gem5::SimpleThread::setPredicate ( bool  val )

inline

Definition at line 432 of file simple_thread.hh.

References predicate, and gem5::X86ISA::val.

Referenced by gem5::minor::ExecContext::setPredicate(), gem5::CheckerCPU::setPredicate(), and gem5::SimpleExecContext::setPredicate().

setProcessPtr()

void gem5::SimpleThread::setProcessPtr ( Process *  p )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 220 of file simple_thread.hh.

References gem5::MipsISA::p, and gem5::ThreadState::setProcessPtr().

setStatus()

void gem5::SimpleThread::setStatus ( Status  newStatus )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 224 of file simple_thread.hh.

References gem5::ThreadState::_status.

Referenced by gem5::MinorCPU::MinorCPU(), and gem5::CheckerThreadContext< TC >::setStatus().

setStCondFailures()

void gem5::SimpleThread::setStCondFailures ( unsigned  sc_failures )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 479 of file simple_thread.hh.

References gem5::ThreadState::storeCondFailures.

Referenced by gem5::SimpleExecContext::setStCondFailures().

setThreadId()

void gem5::SimpleThread::setThreadId ( int  id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 205 of file simple_thread.hh.

References gem5::ThreadState::setThreadId().

Referenced by gem5::CheckerThreadContext< TC >::setThreadId().

setVecElem()

void gem5::SimpleThread::setVecElem ( const RegId &  reg, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 392 of file simple_thread.hh.

References DPRINTF, isa, gem5::X86ISA::reg, setVecElemFlat(), gem5::X86ISA::val, and vecRegs.

Referenced by gem5::CheckerThreadContext< TC >::setVecElem(), gem5::minor::ExecContext::setVecElemOperand(), gem5::CheckerCPU::setVecElemOperand(), and gem5::SimpleExecContext::setVecElemOperand().

setVecElemFlat()

void gem5::SimpleThread::setVecElemFlat ( RegIndex  reg, const ElemIndex &  elemIndex, RegVal  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 527 of file simple_thread.hh.

References gem5::ArmISA::NumVecElemPerVecReg, gem5::X86ISA::reg, gem5::X86ISA::val, and vecElemRegs.

Referenced by setVecElem().

setVecPredReg()

void gem5::SimpleThread::setVecPredReg ( const RegId &  reg, const TheISA::VecPredRegContainer &  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 402 of file simple_thread.hh.

References DPRINTF, isa, gem5::X86ISA::reg, setVecPredRegFlat(), gem5::X86ISA::val, and vecPredRegs.

Referenced by gem5::CheckerThreadContext< TC >::setVecPredReg(), gem5::minor::ExecContext::setVecPredRegOperand(), gem5::CheckerCPU::setVecPredRegOperand(), and gem5::SimpleExecContext::setVecPredRegOperand().

setVecPredRegFlat()

void gem5::SimpleThread::setVecPredRegFlat ( RegIndex  reg, const TheISA::VecPredRegContainer &  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 546 of file simple_thread.hh.

References gem5::X86ISA::reg, gem5::X86ISA::val, and vecPredRegs.

Referenced by setVecPredReg().

setVecReg()

void gem5::SimpleThread::setVecReg ( const RegId &  reg, const TheISA::VecRegContainer &  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 382 of file simple_thread.hh.

References DPRINTF, isa, gem5::X86ISA::reg, setVecRegFlat(), gem5::X86ISA::val, and vecRegs.

Referenced by gem5::CheckerThreadContext< TC >::setVecReg(), gem5::minor::ExecContext::setVecRegOperand(), gem5::CheckerCPU::setVecRegOperand(), and gem5::SimpleExecContext::setVecRegOperand().

setVecRegFlat()

void gem5::SimpleThread::setVecRegFlat ( RegIndex  reg, const TheISA::VecRegContainer &  val  )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 515 of file simple_thread.hh.

References gem5::X86ISA::reg, gem5::X86ISA::val, and vecRegs.

Referenced by setVecReg().

socketId()

uint32_t gem5::SimpleThread::socketId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 203 of file simple_thread.hh.

References gem5::ThreadState::socketId().

status()

Status gem5::SimpleThread::status ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 222 of file simple_thread.hh.

References gem5::ThreadState::_status.

Referenced by activate(), halt(), suspend(), and gem5::BaseKvmCPU::wakeup().

suspend()

void gem5::SimpleThread::suspend ( )

overridevirtual

Set the status to Suspended.

Implements gem5::ThreadContext.

Definition at line 144 of file simple_thread.cc.

References gem5::ThreadState::_status, gem5::ThreadState::_threadId, gem5::ThreadState::baseCpu, gem5::curTick(), gem5::ThreadState::lastActivate, gem5::ThreadState::lastSuspend, status(), and gem5::ThreadContext::Suspended.

Referenced by gem5::X86KvmCPU::deliverInterrupts(), and gem5::BaseKvmCPU::handleKvmExit().

takeOverFrom()

void gem5::SimpleThread::takeOverFrom ( ThreadContext *  oldContext )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 96 of file simple_thread.cc.

References decoder, gem5::ThreadContext::getDecoderPtr(), isa, gem5::ThreadState::storeCondFailures, gem5::InstDecoder::takeOverFrom(), and gem5::takeOverFrom().

threadId()

int gem5::SimpleThread::threadId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 204 of file simple_thread.hh.

References gem5::ThreadState::threadId().

Referenced by gem5::SimpleExecContext::armMonitor(), gem5::SimpleExecContext::getAddrMonitor(), htmAbortTransaction(), gem5::SimpleExecContext::mwait(), gem5::SimpleExecContext::mwaitAtomic(), and name().

unserialize()

void gem5::SimpleThread::unserialize ( CheckpointIn &  cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 126 of file simple_thread.cc.

References gem5::ThreadState::unserialize(), and gem5::unserialize().

Referenced by gem5::BaseKvmCPU::unserializeThread().

Member Data Documentation

_htmCheckpoint

std::unique_ptr<BaseHTMCheckpoint> gem5::SimpleThread::_htmCheckpoint

protected

Definition at line 110 of file simple_thread.hh.

Referenced by getHtmCheckpointPtr(), and setHtmCheckpointPtr().

_pcState

std::unique_ptr<PCStateBase> gem5::SimpleThread::_pcState

protected

Definition at line 107 of file simple_thread.hh.

Referenced by clearArchRegs(), pcState(), and pcStateNoRecord().

ccRegs

std::vector<RegVal> gem5::SimpleThread::ccRegs

protected

Definition at line 104 of file simple_thread.hh.

Referenced by clearArchRegs(), readCCReg(), readCCRegFlat(), setCCReg(), setCCRegFlat(), and SimpleThread().

comInstEventQueue

EventQueue gem5::SimpleThread::comInstEventQueue

An instruction-based event queue.

Used for scheduling events based on number of instructions committed.

Definition at line 130 of file simple_thread.hh.

Referenced by descheduleInstCountEvent(), gem5::minor::Execute::doInstCommitAccounting(), getCurrentInstCount(), scheduleInstCountEvent(), gem5::BaseSimpleCPU::serviceInstCountEvents(), gem5::BaseKvmCPU::setupInstStop(), and gem5::BaseKvmCPU::tick().

decoder

InstDecoder* gem5::SimpleThread::decoder

Definition at line 136 of file simple_thread.hh.

Referenced by gem5::BaseSimpleCPU::advancePC(), gem5::BaseSimpleCPU::checkForInterrupts(), getDecoderPtr(), gem5::BaseSimpleCPU::preExecute(), gem5::BaseSimpleCPU::setupFetchRequest(), and takeOverFrom().

floatRegs

std::vector<RegVal> gem5::SimpleThread::floatRegs

protected

Definition at line 99 of file simple_thread.hh.

Referenced by clearArchRegs(), readFloatReg(), readFloatRegFlat(), setFloatReg(), setFloatRegFlat(), and SimpleThread().

htmTransactionStarts

int64_t gem5::SimpleThread::htmTransactionStarts

Definition at line 139 of file simple_thread.hh.

Referenced by gem5::TimingSimpleCPU::completeIfetch(), gem5::CheckerCPU::getHtmTransactionalDepth(), gem5::SimpleExecContext::getHtmTransactionalDepth(), and htmAbortTransaction().

htmTransactionStops

int64_t gem5::SimpleThread::htmTransactionStops

Definition at line 140 of file simple_thread.hh.

Referenced by gem5::TimingSimpleCPU::completeDataAccess(), gem5::CheckerCPU::getHtmTransactionalDepth(), gem5::SimpleExecContext::getHtmTransactionalDepth(), and htmAbortTransaction().

intRegs

std::vector<RegVal> gem5::SimpleThread::intRegs

protected

Definition at line 100 of file simple_thread.hh.

Referenced by clearArchRegs(), readIntReg(), readIntRegFlat(), setIntReg(), setIntRegFlat(), and SimpleThread().

isa

TheISA::ISA* const gem5::SimpleThread::isa

protected

Definition at line 105 of file simple_thread.hh.

Referenced by clearArchRegs(), flattenRegId(), getIsaPtr(), getWritableVecPredReg(), getWritableVecReg(), readCCReg(), readFloatReg(), readIntReg(), readMiscReg(), readMiscRegNoEffect(), readVecElem(), readVecPredReg(), readVecReg(), setCCReg(), setFloatReg(), setIntReg(), setMiscReg(), setMiscRegNoEffect(), setVecElem(), setVecPredReg(), setVecReg(), SimpleThread(), and takeOverFrom().

memAccPredicate

bool gem5::SimpleThread::memAccPredicate

protected

True if the memory access should be skipped for this instruction.

Definition at line 116 of file simple_thread.hh.

Referenced by readMemAccPredicate(), and setMemAccPredicate().

mmu

BaseMMU* gem5::SimpleThread::mmu

Definition at line 134 of file simple_thread.hh.

Referenced by gem5::AtomicSimpleCPU::amoMem(), demapPage(), gem5::TimingSimpleCPU::fetch(), getMMUPtr(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::minor::ExecContext::mwaitAtomic(), gem5::CheckerCPU::mwaitAtomic(), gem5::SimpleExecContext::mwaitAtomic(), gem5::AtomicSimpleCPU::readMem(), gem5::AtomicSimpleCPU::tick(), gem5::AtomicSimpleCPU::writeMem(), and gem5::TimingSimpleCPU::writeMem().

pcEventQueue

PCEventQueue gem5::SimpleThread::pcEventQueue

Definition at line 125 of file simple_thread.hh.

Referenced by remove(), and schedule().

predicate

bool gem5::SimpleThread::predicate

protected

Did this instruction execute or is it predicated false.

Definition at line 113 of file simple_thread.hh.

Referenced by readPredicate(), and setPredicate().

system

System* gem5::SimpleThread::system

Definition at line 132 of file simple_thread.hh.

Referenced by getSystemPtr().

vecElemRegs

std::vector<RegVal> gem5::SimpleThread::vecElemRegs

protected

Definition at line 102 of file simple_thread.hh.

Referenced by clearArchRegs(), readVecElemFlat(), setVecElemFlat(), and SimpleThread().

vecPredRegs

std::vector<TheISA::VecPredRegContainer> gem5::SimpleThread::vecPredRegs

protected

Definition at line 103 of file simple_thread.hh.

Referenced by clearArchRegs(), getWritableVecPredReg(), getWritableVecPredRegFlat(), readVecPredReg(), readVecPredRegFlat(), setVecPredReg(), setVecPredRegFlat(), and SimpleThread().

vecRegs

std::vector<TheISA::VecRegContainer> gem5::SimpleThread::vecRegs

protected

Definition at line 101 of file simple_thread.hh.

Referenced by clearArchRegs(), getWritableVecReg(), getWritableVecRegFlat(), readVecElem(), readVecReg(), readVecRegFlat(), setVecElem(), setVecReg(), setVecRegFlat(), and SimpleThread().

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The documentation for this class was generated from the following files:

• cpu/simple_thread.hh
• cpu/simple_thread.cc