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static_inst.cc
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28 
29 #include "cpu/static_inst.hh"
30 
31 #include <iostream>
32 
33 #include "cpu/thread_context.hh"
34 
35 namespace gem5
36 {
37 
38 StaticInstPtr
39 StaticInst::fetchMicroop(MicroPC upc) const
40 {
41  panic("StaticInst::fetchMicroop() called on instruction "
42  "that is not microcoded.");
43 }
44 
45 std::unique_ptr<PCStateBase>
46 StaticInst::branchTarget(const PCStateBase &pc) const
47 {
48  panic("StaticInst::branchTarget() called on instruction "
49  "that is not a PC-relative branch.");
50 }
51 
52 std::unique_ptr<PCStateBase>
53 StaticInst::branchTarget(ThreadContext *tc) const
54 {
55  panic("StaticInst::branchTarget() called on instruction "
56  "that is not an indirect branch.");
57 }
58 
59 const std::string &
60 StaticInst::disassemble(Addr pc, const loader::SymbolTable *symtab) const
61 {
62  if (!cachedDisassembly) {
63  cachedDisassembly =
64  std::make_unique<std::string>(generateDisassembly(pc, symtab));
65  }
66 
67  return *cachedDisassembly;
68 }
69 
70 void
71 StaticInst::printFlags(std::ostream &outs,
72  const std::string &separator) const
73 {
74  bool printed_a_flag = false;
75 
76  for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
77  if (flags[flag]) {
78  if (printed_a_flag)
79  outs << separator;
80 
81  outs << FlagsStrings[flag];
82  printed_a_flag = true;
83  }
84  }
85 }
86 
87 void
88 StaticInst::advancePC(ThreadContext *tc) const
89 {
90  std::unique_ptr<PCStateBase> pc(tc->pcState().clone());
91  advancePC(*pc);
92  tc->pcState(*pc);
93 }
94 
95 } // namespace gem5
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::StaticInstPtr
RefCountingPtr< StaticInst > StaticInstPtr
Definition: static_inst_fwd.hh:37
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
static_inst.hh
gem5::StaticInst::generateDisassembly
virtual std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::StaticInst::cachedDisassembly
std::unique_ptr< std::string > cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:286
gem5::StaticInst::branchTarget
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:71
thread_context.hh
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
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