iob.cc File Reference

#include "dev/sparc/iob.hh"
#include <cstring>
#include "arch/sparc/faults.hh"
#include "arch/sparc/interrupts.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Iob.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/faults.hh"
#include "sim/system.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

Detailed Description

This device implemetns the niagara I/O bridge chip. It manages incomming interrupts and posts them to the CPU when needed. It holds mask registers and various status registers for CPUs to check what interrupts are pending as well as facilities to send IPIs to other cpus.

Definition in file iob.cc.