gic.hh

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/*
 * Copyright (c) 2015-2017 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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#ifndef __ARCH_ARM_KVM_GIC_HH__
#define __ARCH_ARM_KVM_GIC_HH__
 
#include "arch/arm/system.hh"
#include "cpu/kvm/device.hh"
#include "cpu/kvm/vm.hh"
#include "dev/arm/gic_v2.hh"
#include "dev/platform.hh"
 
namespace gem5
{
 
class KvmKernelGicV2 : public BaseGicRegisters
{
  public:
    KvmKernelGicV2(KvmVM &vm, Addr cpu_addr, Addr dist_addr,
                   unsigned it_lines);
    virtual ~KvmKernelGicV2();
 
    KvmKernelGicV2(const KvmKernelGicV2 &other) = delete;
    KvmKernelGicV2(const KvmKernelGicV2 &&other) = delete;
    KvmKernelGicV2 &operator=(const KvmKernelGicV2 &&rhs) = delete;
    KvmKernelGicV2 &operator=(const KvmKernelGicV2 &rhs) = delete;
 
  public:
    void setSPI(unsigned spi);
    void clearSPI(unsigned spi);
 
    void setPPI(unsigned vcpu, unsigned ppi);
 
    void clearPPI(unsigned vcpu, unsigned ppi);
 
    const AddrRange cpuRange;
    const AddrRange distRange;
 
    uint32_t readDistributor(ContextID ctx, Addr daddr) override;
    uint32_t readCpu(ContextID ctx, Addr daddr) override;
 
    void writeDistributor(ContextID ctx, Addr daddr,
                          uint32_t data) override;
    void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
 
    /* @} */
 
  protected:
    void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
 
    uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset);
 
    void setGicReg(unsigned group, unsigned vcpu, unsigned offset,
                   unsigned value);
 
    KvmVM &vm;
 
    KvmDevice kdev;
};
 
 
struct MuxingKvmGicParams;
 
class MuxingKvmGic : public GicV2
{
  public: // SimObject / Serializable / Drainable
    MuxingKvmGic(const MuxingKvmGicParams &p);
    ~MuxingKvmGic();
 
    void startup() override;
    DrainState drain() override;
    void drainResume() override;
 
  public: // PioDevice
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
 
  public: // GicV2
    void sendInt(uint32_t num) override;
    void clearInt(uint32_t num) override;
 
    void sendPPInt(uint32_t num, uint32_t cpu) override;
    void clearPPInt(uint32_t num, uint32_t cpu) override;
 
  protected: // GicV2
    void updateIntState(int hint) override;
 
  protected:
    System &system;
 
    KvmKernelGicV2 *kernelGic;
 
  private:
    bool usingKvm;
 
    void fromGicV2ToKvm();
    void fromKvmToGicV2();
 
    void copyGicState(BaseGicRegisters* from, BaseGicRegisters* to);
 
    void copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
                          ContextID ctx, Addr daddr);
    void copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
                         ContextID ctx, Addr daddr);
 
    void copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
                             Addr daddr, size_t size);
    void clearBankedDistRange(BaseGicRegisters* to,
                              Addr daddr, size_t size);
    void copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
                       Addr daddr, size_t size);
    void clearDistRange(BaseGicRegisters* to,
                        Addr daddr, size_t size);
};
 
} // namespace gem5
 
#endif // __ARCH_ARM_KVM_GIC_HH__