regfile.hh

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#ifndef __CPU_O3_REGFILE_HH__
#define __CPU_O3_REGFILE_HH__
 
#include <vector>
 
#include "arch/generic/isa.hh"
#include "arch/vecregs.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "debug/IEW.hh"
 
namespace gem5
{
 
namespace o3
{
 
class UnifiedFreeList;
 
class PhysRegFile
{
  private:
 
    using PhysIds = std::vector<PhysRegId>;
  public:
    using IdRange = std::pair<PhysIds::iterator,
                              PhysIds::iterator>;
  private:
    std::vector<RegVal> intRegFile;
    std::vector<PhysRegId> intRegIds;
    RegId zeroReg;
 
    std::vector<RegVal> floatRegFile;
    std::vector<PhysRegId> floatRegIds;
 
    std::vector<TheISA::VecRegContainer> vectorRegFile;
    std::vector<PhysRegId> vecRegIds;
 
    std::vector<RegVal> vectorElemRegFile;
    std::vector<PhysRegId> vecElemIds;
 
    std::vector<TheISA::VecPredRegContainer> vecPredRegFile;
    std::vector<PhysRegId> vecPredRegIds;
 
    std::vector<RegVal> ccRegFile;
    std::vector<PhysRegId> ccRegIds;
 
    std::vector<PhysRegId> miscRegIds;
 
    unsigned numPhysicalIntRegs;
 
    unsigned numPhysicalFloatRegs;
 
    unsigned numPhysicalVecRegs;
 
    unsigned numPhysicalVecElemRegs;
 
    unsigned numPhysicalVecPredRegs;
 
    unsigned numPhysicalCCRegs;
 
    unsigned totalNumRegs;
 
  public:
    PhysRegFile(unsigned _numPhysicalIntRegs,
                unsigned _numPhysicalFloatRegs,
                unsigned _numPhysicalVecRegs,
                unsigned _numPhysicalVecPredRegs,
                unsigned _numPhysicalCCRegs,
                const BaseISA::RegClasses &regClasses);
 
    ~PhysRegFile() {}
 
    void initFreeList(UnifiedFreeList *freeList);
 
    unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
 
    unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
    unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
    unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
 
    unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
 
    unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
 
    unsigned totalNumPhysRegs() const { return totalNumRegs; }
 
    PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
        return &miscRegIds[reg_idx];
    }
 
    RegVal
    readIntReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->is(IntRegClass));
 
        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
                "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
        return intRegFile[phys_reg->index()];
    }
 
    RegVal
    readFloatReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->is(FloatRegClass));
 
        RegVal floatRegBits = floatRegFile[phys_reg->index()];
 
        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
                "has data %#x\n", phys_reg->index(), floatRegBits);
 
        return floatRegBits;
    }
 
    const TheISA::VecRegContainer &
    readVecReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->is(VecRegClass));
 
        DPRINTF(IEW, "RegFile: Access to vector register %i, has "
                "data %s\n", int(phys_reg->index()),
                vectorRegFile[phys_reg->index()]);
 
        return vectorRegFile[phys_reg->index()];
    }
 
    TheISA::VecRegContainer &
    getWritableVecReg(PhysRegIdPtr phys_reg)
    {
        /* const_cast for not duplicating code above. */
        return const_cast<TheISA::VecRegContainer&>(readVecReg(phys_reg));
    }
 
    RegVal
    readVecElem(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->is(VecElemClass));
        RegVal val = vectorElemRegFile[
                phys_reg->index() * TheISA::NumVecElemPerVecReg +
                phys_reg->elemIndex()];
        DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
                " has data %#x\n", phys_reg->elemIndex(),
                phys_reg->index(), val);
 
        return val;
    }
 
    const TheISA::VecPredRegContainer&
    readVecPredReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->is(VecPredRegClass));
 
        DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
                "data %s\n", int(phys_reg->index()),
                vecPredRegFile[phys_reg->index()]);
 
        return vecPredRegFile[phys_reg->index()];
    }
 
    TheISA::VecPredRegContainer&
    getWritableVecPredReg(PhysRegIdPtr phys_reg)
    {
        /* const_cast for not duplicating code above. */
        return const_cast<TheISA::VecPredRegContainer&>(
                readVecPredReg(phys_reg));
    }
 
    RegVal
    readCCReg(PhysRegIdPtr phys_reg)
    {
        assert(phys_reg->is(CCRegClass));
 
        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
                "data %#x\n", phys_reg->index(),
                ccRegFile[phys_reg->index()]);
 
        return ccRegFile[phys_reg->index()];
    }
 
    void
    setIntReg(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->is(IntRegClass));
 
        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
                phys_reg->index(), val);
 
        if (phys_reg->index() != zeroReg.index())
            intRegFile[phys_reg->index()] = val;
    }
 
    void
    setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->is(FloatRegClass));
 
        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
                phys_reg->index(), (uint64_t)val);
 
        floatRegFile[phys_reg->index()] = val;
    }
 
    void
    setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer& val)
    {
        assert(phys_reg->is(VecRegClass));
 
        DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
                int(phys_reg->index()), val);
 
        vectorRegFile[phys_reg->index()] = val;
    }
 
    void
    setVecElem(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->is(VecElemClass));
 
        DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
                " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
 
        vectorElemRegFile[phys_reg->index() * TheISA::NumVecElemPerVecReg +
                phys_reg->elemIndex()] = val;
    }
 
    void
    setVecPredReg(PhysRegIdPtr phys_reg,
            const TheISA::VecPredRegContainer& val)
    {
        assert(phys_reg->is(VecPredRegClass));
 
        DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
                int(phys_reg->index()), val);
 
        vecPredRegFile[phys_reg->index()] = val;
    }
 
    void
    setCCReg(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->is(CCRegClass));
 
        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
                phys_reg->index(), (uint64_t)val);
 
        ccRegFile[phys_reg->index()] = val;
    }
 
    IdRange getRegIds(RegClassType cls);
 
    PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_REGFILE_HH__