gem5  v21.2.0.0
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vecregs.hh
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28 
29 #ifndef __ARCH_SPARC_VECREGS_HH__
30 #define __ARCH_SPARC_VECREGS_HH__
31 
32 #include "arch/generic/vec_pred_reg.hh"
33 #include "arch/generic/vec_reg.hh"
34 
35 namespace gem5
36 {
37 
38 namespace SparcISA
39 {
40 
41 // Not applicable to SPARC
42 using VecElem = ::gem5::DummyVecElem;
43 using VecRegContainer = ::gem5::DummyVecRegContainer;
44 constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg;
45 
46 // Not applicable to SPARC
47 using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
48 
49 } // namespace SparcISA
50 } // namespace gem5
51 
52 #endif
gem5::VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:53
gem5::DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:266
gem5::SparcISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vecregs.hh:44
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecRegContainer
VecRegContainer< DummyNumVecElemPerVecReg *sizeof(DummyVecElem)> DummyVecRegContainer
Definition: vec_reg.hh:269
gem5::SparcISA::VecElem
::gem5::DummyVecElem VecElem
Definition: vecregs.hh:42
gem5::DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:267
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::DummyVecPredRegContainer
VecPredRegContainer< 8, false > DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:397
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