gem5  v21.2.1.0
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
Public Member Functions | Public Attributes | List of all members
gem5::o3::ThreadContext Class Reference

Derived ThreadContext class for use with the O3CPU. More...

#include <thread_context.hh>

Inheritance diagram for gem5::o3::ThreadContext:
gem5::ThreadContext gem5::PCEventScope

Public Member Functions

bool schedule (PCEvent *e) override
 
bool remove (PCEvent *e) override
 
void scheduleInstCountEvent (Event *event, Tick count) override
 
void descheduleInstCountEvent (Event *event) override
 
Tick getCurrentInstCount () override
 
BaseMMU * getMMUPtr () override
 Returns a pointer to the MMU. More...
 
CheckerCPU * getCheckerCpuPtr () override
 
BaseISA * getIsaPtr () override
 
InstDecoder * getDecoderPtr () override
 
BaseCPU * getCpuPtr () override
 Returns a pointer to this CPU. More...
 
int cpuId () const override
 Reads this CPU's ID. More...
 
uint32_t socketId () const override
 Reads this CPU's Socket ID. More...
 
ContextID contextId () const override
 
void setContextId (ContextID id) override
 
int threadId () const override
 Returns this thread's ID number. More...
 
void setThreadId (int id) override
 
System * getSystemPtr () override
 Returns a pointer to the system. More...
 
Process * getProcessPtr () override
 Returns a pointer to this thread's process. More...
 
void setProcessPtr (Process *p) override
 
Status status () const override
 Returns this thread's status. More...
 
void setStatus (Status new_status) override
 Sets this thread's status. More...
 
void activate () override
 Set the status to Active. More...
 
void suspend () override
 Set the status to Suspended. More...
 
void halt () override
 Set the status to Halted. More...
 
void takeOverFrom (gem5::ThreadContext *old_context) override
 Takes over execution of a thread from another CPU. More...
 
Tick readLastActivate () override
 Reads the last tick that this thread was activated on. More...
 
Tick readLastSuspend () override
 Reads the last tick that this thread was suspended on. More...
 
void copyArchRegs (gem5::ThreadContext *tc) override
 Copies the architectural registers from another TC into this TC. More...
 
void clearArchRegs () override
 Resets all architectural registers to 0. More...
 
RegVal readReg (RegIndex reg_idx)
 Reads an integer register. More...
 
RegVal readIntReg (RegIndex reg_idx) const override
 
RegVal readFloatReg (RegIndex reg_idx) const override
 
const TheISA::VecRegContainer & readVecReg (const RegId &id) const override
 
TheISA::VecRegContainer & getWritableVecReg (const RegId &id) override
 Read vector register operand for modification, hierarchical indexing. More...
 
RegVal readVecElem (const RegId &reg) const override
 
const TheISA::VecPredRegContainer & readVecPredReg (const RegId &id) const override
 
TheISA::VecPredRegContainer & getWritableVecPredReg (const RegId &id) override
 
RegVal readCCReg (RegIndex reg_idx) const override
 
void setIntReg (RegIndex reg_idx, RegVal val) override
 Sets an integer register to a value. More...
 
void setFloatReg (RegIndex reg_idx, RegVal val) override
 
void setVecReg (const RegId &reg, const TheISA::VecRegContainer &val) override
 
void setVecElem (const RegId &reg, RegVal val) override
 
void setVecPredReg (const RegId &reg, const TheISA::VecPredRegContainer &val) override
 
void setCCReg (RegIndex reg_idx, RegVal val) override
 
const PCStateBase & pcState () const override
 Reads this thread's PC state. More...
 
void pcState (const PCStateBase &val) override
 Sets this thread's PC state. More...
 
void pcStateNoRecord (const PCStateBase &val) override
 
RegVal readMiscRegNoEffect (RegIndex misc_reg) const override
 Reads a miscellaneous register. More...
 
RegVal readMiscReg (RegIndex misc_reg) override
 Reads a misc. More...
 
void setMiscRegNoEffect (RegIndex misc_reg, RegVal val) override
 Sets a misc. More...
 
void setMiscReg (RegIndex misc_reg, RegVal val) override
 Sets a misc. More...
 
RegId flattenRegId (const RegId &regId) const override
 
unsigned readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
void setStCondFailures (unsigned sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
void conditionalSquash ()
 check if the cpu is currently in state update mode and squash if not. More...
 
RegVal readIntRegFlat (RegIndex idx) const override
 Flat register interfaces. More...
 
void setIntRegFlat (RegIndex idx, RegVal val) override
 
RegVal readFloatRegFlat (RegIndex idx) const override
 
void setFloatRegFlat (RegIndex idx, RegVal val) override
 
const TheISA::VecRegContainer & readVecRegFlat (RegIndex idx) const override
 
TheISA::VecRegContainer & getWritableVecRegFlat (RegIndex idx) override
 Read vector register operand for modification, flat indexing. More...
 
void setVecRegFlat (RegIndex idx, const TheISA::VecRegContainer &val) override
 
RegVal readVecElemFlat (RegIndex idx, const ElemIndex &elemIndex) const override
 
void setVecElemFlat (RegIndex idx, const ElemIndex &elemIdx, RegVal val) override
 
const TheISA::VecPredRegContainer & readVecPredRegFlat (RegIndex idx) const override
 
TheISA::VecPredRegContainer & getWritableVecPredRegFlat (RegIndex idx) override
 
void setVecPredRegFlat (RegIndex idx, const TheISA::VecPredRegContainer &val) override
 
RegVal readCCRegFlat (RegIndex idx) const override
 
void setCCRegFlat (RegIndex idx, RegVal val) override
 
void htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override
 
BaseHTMCheckpointPtr & getHtmCheckpointPtr () override
 
void setHtmCheckpointPtr (BaseHTMCheckpointPtr new_cpt) override
 
- Public Member Functions inherited from gem5::ThreadContext
bool getUseForClone ()
 
void setUseForClone (bool new_val)
 
virtual ~ThreadContext ()
 
virtual void sendFunctional (PacketPtr pkt)
 
void quiesce ()
 Quiesce thread context. More...
 
void quiesceTick (Tick resume)
 Quiesce, suspend, and schedule activate at resume. More...
 
virtual void regStats (const std::string &name)
 
void pcState (Addr addr)
 
virtual int exit ()
 

Public Attributes

CPU * cpu
 Pointer to the CPU. More...
 
ThreadState * thread
 Pointer to the thread state that this TC corrseponds to. More...
 
- Public Attributes inherited from gem5::ThreadContext
int intResult = DefaultIntResult
 
double floatResult = DefaultFloatResult
 
int intOffset = 0
 

Additional Inherited Members

- Public Types inherited from gem5::ThreadContext
enum  Status { Active, Suspended, Halting, Halted }
 
- Static Public Member Functions inherited from gem5::ThreadContext
static void compare (ThreadContext *one, ThreadContext *two)
 function to compare two thread contexts (for debugging) More...
 
- Static Public Attributes inherited from gem5::ThreadContext
static const int ints []
 
static const double floats []
 
static const int DefaultIntResult = 0
 
static const double DefaultFloatResult = 0.0
 
- Protected Attributes inherited from gem5::ThreadContext
bool useForClone = false
 

Detailed Description

Derived ThreadContext class for use with the O3CPU.

It provides the interface for any external objects to access a single thread's state and some general CPU state. Any time external objects try to update state through this interface, the CPU will create an event to squash all in-flight instructions in order to ensure state is maintained correctly. It must be defined specifically for the O3CPU because not all architectural state is located within the ThreadState (such as the commit PC, and registers), and specific actions must be taken when using this interface (such as squashing all in-flight instructions when doing a write to this interface).

Definition at line 68 of file thread_context.hh.

Member Function Documentation

◆ activate()

void gem5::o3::ThreadContext::activate ( )
overridevirtual

Set the status to Active.

Implements gem5::ThreadContext.

Definition at line 70 of file thread_context.cc.

References gem5::o3::CPU::activateContext(), gem5::ThreadContext::Active, cpu, gem5::curTick(), DPRINTF, gem5::ThreadState::lastActivate, gem5::ThreadState::setStatus(), gem5::ThreadState::status(), thread, gem5::ThreadState::threadId(), and threadId().

◆ clearArchRegs()

void gem5::o3::ThreadContext::clearArchRegs ( )
overridevirtual

Resets all architectural registers to 0.

Implements gem5::ThreadContext.

Definition at line 147 of file thread_context.cc.

References cpu, gem5::o3::CPU::isa, thread, and gem5::ThreadState::threadId().

◆ conditionalSquash()

void gem5::o3::ThreadContext::conditionalSquash ( )
inline

check if the cpu is currently in state update mode and squash if not.

This function will return true if a trap is pending or if a fault or similar is currently writing to the thread context and doesn't want reset all the state (see noSquashFromTC).

Definition at line 336 of file thread_context.hh.

References cpu, gem5::o3::ThreadState::noSquashFromTC, gem5::o3::CPU::squashFromTC(), thread, gem5::ThreadState::threadId(), and gem5::o3::ThreadState::trapPending.

Referenced by htmAbortTransaction(), pcState(), pcStateNoRecord(), setCCRegFlat(), setFloatRegFlat(), setIntRegFlat(), setMiscReg(), setMiscRegNoEffect(), setVecElemFlat(), setVecPredRegFlat(), and setVecRegFlat().

◆ contextId()

ContextID gem5::o3::ThreadContext::contextId ( ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 130 of file thread_context.hh.

References gem5::ThreadState::contextId(), and thread.

◆ copyArchRegs()

void gem5::o3::ThreadContext::copyArchRegs ( gem5::ThreadContext *  tc)
overridevirtual

Copies the architectural registers from another TC into this TC.

Implements gem5::ThreadContext.

Definition at line 138 of file thread_context.cc.

References gem5::BaseISA::copyRegsFrom(), getIsaPtr(), gem5::o3::ThreadState::noSquashFromTC, and thread.

◆ cpuId()

int gem5::o3::ThreadContext::cpuId ( ) const
inlineoverridevirtual

Reads this CPU's ID.

Implements gem5::ThreadContext.

Definition at line 125 of file thread_context.hh.

References cpu.

◆ descheduleInstCountEvent()

void gem5::o3::ThreadContext::descheduleInstCountEvent ( Event *  event)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 91 of file thread_context.hh.

References gem5::o3::ThreadState::comInstEventQueue, gem5::EventQueue::deschedule(), gem5::MipsISA::event, and thread.

◆ flattenRegId()

RegId gem5::o3::ThreadContext::flattenRegId ( const RegId &  regId) const
overridevirtual

Implements gem5::ThreadContext.

Definition at line 267 of file thread_context.cc.

References cpu, gem5::o3::CPU::isa, thread, and gem5::ThreadState::threadId().

Referenced by getWritableVecPredReg(), getWritableVecReg(), readCCReg(), readFloatReg(), readIntReg(), readReg(), readVecElem(), readVecPredReg(), readVecReg(), setCCReg(), setFloatReg(), setIntReg(), setVecElem(), setVecPredReg(), and setVecReg().

◆ getCheckerCpuPtr()

CheckerCPU* gem5::o3::ThreadContext::getCheckerCpuPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 107 of file thread_context.hh.

◆ getCpuPtr()

BaseCPU* gem5::o3::ThreadContext::getCpuPtr ( )
inlineoverridevirtual

Returns a pointer to this CPU.

Implements gem5::ThreadContext.

Definition at line 122 of file thread_context.hh.

References cpu.

◆ getCurrentInstCount()

Tick gem5::o3::ThreadContext::getCurrentInstCount ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 96 of file thread_context.hh.

References gem5::o3::ThreadState::comInstEventQueue, gem5::EventQueue::getCurTick(), and thread.

◆ getDecoderPtr()

InstDecoder* gem5::o3::ThreadContext::getDecoderPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 116 of file thread_context.hh.

References cpu, gem5::o3::Fetch::decoder, gem5::o3::CPU::fetch, thread, and gem5::ThreadState::threadId().

Referenced by takeOverFrom().

◆ getHtmCheckpointPtr()

BaseHTMCheckpointPtr & gem5::o3::ThreadContext::getHtmCheckpointPtr ( )
overridevirtual

Implements gem5::ThreadContext.

Definition at line 299 of file thread_context.cc.

References gem5::o3::ThreadState::htmCheckpoint, and thread.

◆ getIsaPtr()

BaseISA* gem5::o3::ThreadContext::getIsaPtr ( )
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 110 of file thread_context.hh.

References cpu, gem5::o3::CPU::isa, thread, and gem5::ThreadState::threadId().

Referenced by copyArchRegs(), and takeOverFrom().

◆ getMMUPtr()

BaseMMU* gem5::o3::ThreadContext::getMMUPtr ( )
inlineoverridevirtual

Returns a pointer to the MMU.

Implements gem5::ThreadContext.

Definition at line 105 of file thread_context.hh.

References cpu, and gem5::o3::CPU::mmu.

◆ getProcessPtr()

Process* gem5::o3::ThreadContext::getProcessPtr ( )
inlineoverridevirtual

Returns a pointer to this thread's process.

Implements gem5::ThreadContext.

Definition at line 142 of file thread_context.hh.

References gem5::ThreadState::getProcessPtr(), and thread.

◆ getSystemPtr()

System* gem5::o3::ThreadContext::getSystemPtr ( )
inlineoverridevirtual

Returns a pointer to the system.

Implements gem5::ThreadContext.

Definition at line 139 of file thread_context.hh.

References cpu, and gem5::o3::CPU::system.

◆ getWritableVecPredReg()

TheISA::VecPredRegContainer& gem5::o3::ThreadContext::getWritableVecPredReg ( const RegId &  id)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 228 of file thread_context.hh.

References flattenRegId(), getWritableVecPredRegFlat(), and gem5::MipsISA::index.

◆ getWritableVecPredRegFlat()

TheISA::VecPredRegContainer & gem5::o3::ThreadContext::getWritableVecPredRegFlat ( RegIndex  idx)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 189 of file thread_context.cc.

References cpu, gem5::o3::CPU::getWritableArchVecPredReg(), thread, and gem5::ThreadState::threadId().

Referenced by getWritableVecPredReg().

◆ getWritableVecReg()

TheISA::VecRegContainer& gem5::o3::ThreadContext::getWritableVecReg ( const RegId &  id)
inlineoverridevirtual

Read vector register operand for modification, hierarchical indexing.

Implements gem5::ThreadContext.

Definition at line 210 of file thread_context.hh.

References flattenRegId(), getWritableVecRegFlat(), and gem5::MipsISA::index.

◆ getWritableVecRegFlat()

TheISA::VecRegContainer & gem5::o3::ThreadContext::getWritableVecRegFlat ( RegIndex  idx)
overridevirtual

Read vector register operand for modification, flat indexing.

Implements gem5::ThreadContext.

Definition at line 171 of file thread_context.cc.

References cpu, gem5::o3::CPU::getWritableArchVecReg(), thread, and gem5::ThreadState::threadId().

Referenced by getWritableVecReg().

◆ halt()

void gem5::o3::ThreadContext::halt ( )
overridevirtual

Set the status to Halted.

Implements gem5::ThreadContext.

Definition at line 107 of file thread_context.cc.

References gem5::o3::CPU::addThreadToExitingList(), cpu, DPRINTF, gem5::ThreadContext::Halted, gem5::ThreadContext::Halting, gem5::ThreadState::setStatus(), gem5::ThreadState::status(), thread, gem5::ThreadState::threadId(), and threadId().

◆ htmAbortTransaction()

void gem5::o3::ThreadContext::htmAbortTransaction ( uint64_t  htm_uid,
HtmFailureFaultCause  cause 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 290 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::htmSendAbortSignal(), thread, and gem5::ThreadState::threadId().

◆ pcState() [1/2]

const PCStateBase& gem5::o3::ThreadContext::pcState ( ) const
inlineoverridevirtual

Reads this thread's PC state.

Implements gem5::ThreadContext.

Definition at line 281 of file thread_context.hh.

References cpu, gem5::o3::CPU::pcState(), thread, and gem5::ThreadState::threadId().

◆ pcState() [2/2]

void gem5::o3::ThreadContext::pcState ( const PCStateBase &  val)
overridevirtual

Sets this thread's PC state.

Implements gem5::ThreadContext.

Definition at line 251 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::pcState(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

◆ pcStateNoRecord()

void gem5::o3::ThreadContext::pcStateNoRecord ( const PCStateBase &  val)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 259 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::pcState(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

◆ readCCReg()

RegVal gem5::o3::ThreadContext::readCCReg ( RegIndex  reg_idx) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 234 of file thread_context.hh.

References gem5::CCRegClass, flattenRegId(), gem5::MipsISA::index, and readCCRegFlat().

◆ readCCRegFlat()

RegVal gem5::o3::ThreadContext::readCCRegFlat ( RegIndex  idx) const
overridevirtual

Implements gem5::ThreadContext.

Definition at line 195 of file thread_context.cc.

References cpu, gem5::o3::CPU::readArchCCReg(), thread, and gem5::ThreadState::threadId().

Referenced by readCCReg().

◆ readFloatReg()

RegVal gem5::o3::ThreadContext::readFloatReg ( RegIndex  reg_idx) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 194 of file thread_context.hh.

References flattenRegId(), gem5::FloatRegClass, gem5::MipsISA::index, and readFloatRegFlat().

◆ readFloatRegFlat()

RegVal gem5::o3::ThreadContext::readFloatRegFlat ( RegIndex  idx) const
overridevirtual

Implements gem5::ThreadContext.

Definition at line 159 of file thread_context.cc.

References cpu, gem5::o3::CPU::readArchFloatReg(), thread, and gem5::ThreadState::threadId().

Referenced by readFloatReg().

◆ readIntReg()

RegVal gem5::o3::ThreadContext::readIntReg ( RegIndex  reg_idx) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 187 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, gem5::IntRegClass, and readIntRegFlat().

◆ readIntRegFlat()

RegVal gem5::o3::ThreadContext::readIntRegFlat ( RegIndex  idx) const
overridevirtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Implements gem5::ThreadContext.

Definition at line 153 of file thread_context.cc.

References cpu, gem5::o3::CPU::readArchIntReg(), thread, and gem5::ThreadState::threadId().

Referenced by readIntReg(), and readReg().

◆ readLastActivate()

Tick gem5::o3::ThreadContext::readLastActivate ( )
overridevirtual

Reads the last tick that this thread was activated on.

Implements gem5::ThreadContext.

Definition at line 126 of file thread_context.cc.

References gem5::ThreadState::lastActivate, and thread.

◆ readLastSuspend()

Tick gem5::o3::ThreadContext::readLastSuspend ( )
overridevirtual

Reads the last tick that this thread was suspended on.

Implements gem5::ThreadContext.

Definition at line 132 of file thread_context.cc.

References gem5::ThreadState::lastSuspend, and thread.

◆ readMiscReg()

RegVal gem5::o3::ThreadContext::readMiscReg ( RegIndex  misc_reg)
inlineoverridevirtual

Reads a misc.

register, including any side-effects the read might have as defined by the architecture.

Implements gem5::ThreadContext.

Definition at line 301 of file thread_context.hh.

References cpu, gem5::o3::CPU::readMiscReg(), thread, and gem5::ThreadState::threadId().

◆ readMiscRegNoEffect()

RegVal gem5::o3::ThreadContext::readMiscRegNoEffect ( RegIndex  misc_reg) const
inlineoverridevirtual

Reads a miscellaneous register.

Implements gem5::ThreadContext.

Definition at line 293 of file thread_context.hh.

References cpu, gem5::o3::CPU::readMiscRegNoEffect(), thread, and gem5::ThreadState::threadId().

◆ readReg()

RegVal gem5::o3::ThreadContext::readReg ( RegIndex  reg_idx)
inline

Reads an integer register.

Definition at line 181 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, gem5::IntRegClass, and readIntRegFlat().

◆ readStCondFailures()

unsigned gem5::o3::ThreadContext::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements gem5::ThreadContext.

Definition at line 318 of file thread_context.hh.

References gem5::ThreadState::storeCondFailures, and thread.

◆ readVecElem()

RegVal gem5::o3::ThreadContext::readVecElem ( const RegId &  reg) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 216 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, readVecElemFlat(), and gem5::X86ISA::reg.

◆ readVecElemFlat()

RegVal gem5::o3::ThreadContext::readVecElemFlat ( RegIndex  idx,
const ElemIndex &  elemIndex 
) const
overridevirtual

Implements gem5::ThreadContext.

Definition at line 177 of file thread_context.cc.

References cpu, gem5::o3::CPU::readArchVecElem(), thread, and gem5::ThreadState::threadId().

Referenced by readVecElem().

◆ readVecPredReg()

const TheISA::VecPredRegContainer& gem5::o3::ThreadContext::readVecPredReg ( const RegId &  id) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 222 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, and readVecPredRegFlat().

◆ readVecPredRegFlat()

const TheISA::VecPredRegContainer & gem5::o3::ThreadContext::readVecPredRegFlat ( RegIndex  idx) const
overridevirtual

Implements gem5::ThreadContext.

Definition at line 183 of file thread_context.cc.

References cpu, gem5::o3::CPU::readArchVecPredReg(), thread, and gem5::ThreadState::threadId().

Referenced by readVecPredReg().

◆ readVecReg()

const TheISA::VecRegContainer& gem5::o3::ThreadContext::readVecReg ( const RegId &  id) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 201 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, and readVecRegFlat().

◆ readVecRegFlat()

const TheISA::VecRegContainer & gem5::o3::ThreadContext::readVecRegFlat ( RegIndex  idx) const
overridevirtual

Implements gem5::ThreadContext.

Definition at line 165 of file thread_context.cc.

References cpu, gem5::o3::CPU::readArchVecReg(), thread, and gem5::ThreadState::threadId().

Referenced by readVecReg().

◆ remove()

bool gem5::o3::ThreadContext::remove ( PCEvent *  e)
inlineoverridevirtual

Implements gem5::PCEventScope.

Definition at line 80 of file thread_context.hh.

References gem5::ArmISA::e, gem5::o3::ThreadState::pcEventQueue, gem5::PCEventQueue::remove(), and thread.

◆ schedule()

bool gem5::o3::ThreadContext::schedule ( PCEvent *  e)
inlineoverridevirtual

Implements gem5::PCEventScope.

Definition at line 75 of file thread_context.hh.

References gem5::ArmISA::e, gem5::o3::ThreadState::pcEventQueue, gem5::PCEventQueue::schedule(), and thread.

◆ scheduleInstCountEvent()

void gem5::o3::ThreadContext::scheduleInstCountEvent ( Event *  event,
Tick  count 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 86 of file thread_context.hh.

References gem5::o3::ThreadState::comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, gem5::EventQueue::schedule(), and thread.

◆ setCCReg()

void gem5::o3::ThreadContext::setCCReg ( RegIndex  reg_idx,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 274 of file thread_context.hh.

References gem5::CCRegClass, flattenRegId(), gem5::MipsISA::index, setCCRegFlat(), and gem5::X86ISA::val.

◆ setCCRegFlat()

void gem5::o3::ThreadContext::setCCRegFlat ( RegIndex  idx,
RegVal  val 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 243 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setArchCCReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

Referenced by setCCReg().

◆ setContextId()

void gem5::o3::ThreadContext::setContextId ( ContextID  id)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 132 of file thread_context.hh.

References gem5::ThreadState::setContextId(), and thread.

◆ setFloatReg()

void gem5::o3::ThreadContext::setFloatReg ( RegIndex  reg_idx,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 248 of file thread_context.hh.

References flattenRegId(), gem5::FloatRegClass, gem5::MipsISA::index, setFloatRegFlat(), and gem5::X86ISA::val.

◆ setFloatRegFlat()

void gem5::o3::ThreadContext::setFloatRegFlat ( RegIndex  idx,
RegVal  val 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 209 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setArchFloatReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

Referenced by setFloatReg().

◆ setHtmCheckpointPtr()

void gem5::o3::ThreadContext::setHtmCheckpointPtr ( BaseHTMCheckpointPtr  new_cpt)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 305 of file thread_context.cc.

References gem5::o3::ThreadState::htmCheckpoint, and thread.

◆ setIntReg()

void gem5::o3::ThreadContext::setIntReg ( RegIndex  reg_idx,
RegVal  val 
)
inlineoverridevirtual

Sets an integer register to a value.

Implements gem5::ThreadContext.

Definition at line 242 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, gem5::IntRegClass, setIntRegFlat(), and gem5::X86ISA::val.

◆ setIntRegFlat()

void gem5::o3::ThreadContext::setIntRegFlat ( RegIndex  idx,
RegVal  val 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 201 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setArchIntReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

Referenced by setIntReg().

◆ setMiscReg()

void gem5::o3::ThreadContext::setMiscReg ( RegIndex  misc_reg,
RegVal  val 
)
overridevirtual

Sets a misc.

register, including any side-effects the write might have as defined by the architecture.

Implements gem5::ThreadContext.

Definition at line 281 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setMiscReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

◆ setMiscRegNoEffect()

void gem5::o3::ThreadContext::setMiscRegNoEffect ( RegIndex  misc_reg,
RegVal  val 
)
overridevirtual

Sets a misc.

register.

Implements gem5::ThreadContext.

Definition at line 273 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setMiscRegNoEffect(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

◆ setProcessPtr()

void gem5::o3::ThreadContext::setProcessPtr ( Process *  p)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 144 of file thread_context.hh.

References gem5::MipsISA::p, gem5::ThreadState::setProcessPtr(), and thread.

◆ setStatus()

void gem5::o3::ThreadContext::setStatus ( Status  new_status)
inlineoverridevirtual

Sets this thread's status.

Implements gem5::ThreadContext.

Definition at line 151 of file thread_context.hh.

References gem5::ThreadState::setStatus(), and thread.

◆ setStCondFailures()

void gem5::o3::ThreadContext::setStCondFailures ( unsigned  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements gem5::ThreadContext.

Definition at line 325 of file thread_context.hh.

References gem5::ThreadState::storeCondFailures, and thread.

◆ setThreadId()

void gem5::o3::ThreadContext::setThreadId ( int  id)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 136 of file thread_context.hh.

References gem5::ThreadState::setThreadId(), and thread.

◆ setVecElem()

void gem5::o3::ThreadContext::setVecElem ( const RegId &  reg,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 261 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, gem5::X86ISA::reg, setVecElemFlat(), and gem5::X86ISA::val.

◆ setVecElemFlat()

void gem5::o3::ThreadContext::setVecElemFlat ( RegIndex  idx,
const ElemIndex &  elemIdx,
RegVal  val 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 226 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setArchVecElem(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

Referenced by setVecElem().

◆ setVecPredReg()

void gem5::o3::ThreadContext::setVecPredReg ( const RegId &  reg,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 267 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, gem5::X86ISA::reg, setVecPredRegFlat(), and gem5::X86ISA::val.

◆ setVecPredRegFlat()

void gem5::o3::ThreadContext::setVecPredRegFlat ( RegIndex  idx,
const TheISA::VecPredRegContainer &  val 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 234 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setArchVecPredReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

Referenced by setVecPredReg().

◆ setVecReg()

void gem5::o3::ThreadContext::setVecReg ( const RegId &  reg,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 255 of file thread_context.hh.

References flattenRegId(), gem5::MipsISA::index, gem5::X86ISA::reg, setVecRegFlat(), and gem5::X86ISA::val.

◆ setVecRegFlat()

void gem5::o3::ThreadContext::setVecRegFlat ( RegIndex  idx,
const TheISA::VecRegContainer &  val 
)
overridevirtual

Implements gem5::ThreadContext.

Definition at line 217 of file thread_context.cc.

References conditionalSquash(), cpu, gem5::o3::CPU::setArchVecReg(), thread, gem5::ThreadState::threadId(), and gem5::X86ISA::val.

Referenced by setVecReg().

◆ socketId()

uint32_t gem5::o3::ThreadContext::socketId ( ) const
inlineoverridevirtual

Reads this CPU's Socket ID.

Implements gem5::ThreadContext.

Definition at line 128 of file thread_context.hh.

References cpu.

◆ status()

Status gem5::o3::ThreadContext::status ( ) const
inlineoverridevirtual

Returns this thread's status.

Implements gem5::ThreadContext.

Definition at line 147 of file thread_context.hh.

References gem5::ThreadState::status(), and thread.

◆ suspend()

void gem5::o3::ThreadContext::suspend ( )
overridevirtual

Set the status to Suspended.

Implements gem5::ThreadContext.

Definition at line 86 of file thread_context.cc.

References cpu, gem5::curTick(), DPRINTF, gem5::o3::CPU::isDraining(), gem5::ThreadState::lastActivate, gem5::ThreadState::lastSuspend, gem5::ThreadState::setStatus(), gem5::ThreadState::status(), gem5::o3::CPU::suspendContext(), gem5::ThreadContext::Suspended, thread, gem5::ThreadState::threadId(), and threadId().

◆ takeOverFrom()

void gem5::o3::ThreadContext::takeOverFrom ( gem5::ThreadContext *  old_context)
overridevirtual

Takes over execution of a thread from another CPU.

Implements gem5::ThreadContext.

Definition at line 55 of file thread_context.cc.

References getDecoderPtr(), gem5::ThreadContext::getDecoderPtr(), getIsaPtr(), gem5::o3::ThreadState::noSquashFromTC, gem5::BaseISA::takeOverFrom(), gem5::InstDecoder::takeOverFrom(), gem5::takeOverFrom(), thread, and gem5::o3::ThreadState::trapPending.

◆ threadId()

int gem5::o3::ThreadContext::threadId ( ) const
inlineoverridevirtual

Returns this thread's ID number.

Implements gem5::ThreadContext.

Definition at line 135 of file thread_context.hh.

References thread, and gem5::ThreadState::threadId().

Referenced by activate(), halt(), and suspend().

Member Data Documentation

◆ cpu

CPU* gem5::o3::ThreadContext::cpu

Pointer to the CPU.

Definition at line 72 of file thread_context.hh.

Referenced by activate(), clearArchRegs(), conditionalSquash(), cpuId(), flattenRegId(), getCpuPtr(), getDecoderPtr(), getIsaPtr(), getMMUPtr(), getSystemPtr(), getWritableVecPredRegFlat(), getWritableVecRegFlat(), halt(), htmAbortTransaction(), pcState(), pcStateNoRecord(), readCCRegFlat(), readFloatRegFlat(), readIntRegFlat(), readMiscReg(), readMiscRegNoEffect(), readVecElemFlat(), readVecPredRegFlat(), readVecRegFlat(), setCCRegFlat(), setFloatRegFlat(), setIntRegFlat(), setMiscReg(), setMiscRegNoEffect(), setVecElemFlat(), setVecPredRegFlat(), setVecRegFlat(), socketId(), and suspend().

◆ thread

ThreadState* gem5::o3::ThreadContext::thread

Pointer to the thread state that this TC corrseponds to.

Definition at line 102 of file thread_context.hh.

Referenced by activate(), clearArchRegs(), conditionalSquash(), contextId(), copyArchRegs(), descheduleInstCountEvent(), flattenRegId(), getCurrentInstCount(), getDecoderPtr(), getHtmCheckpointPtr(), getIsaPtr(), getProcessPtr(), getWritableVecPredRegFlat(), getWritableVecRegFlat(), halt(), htmAbortTransaction(), pcState(), pcStateNoRecord(), readCCRegFlat(), readFloatRegFlat(), readIntRegFlat(), readLastActivate(), readLastSuspend(), readMiscReg(), readMiscRegNoEffect(), readStCondFailures(), readVecElemFlat(), readVecPredRegFlat(), readVecRegFlat(), remove(), schedule(), scheduleInstCountEvent(), setCCRegFlat(), setContextId(), setFloatRegFlat(), setHtmCheckpointPtr(), setIntRegFlat(), setMiscReg(), setMiscRegNoEffect(), setProcessPtr(), setStatus(), setStCondFailures(), setThreadId(), setVecElemFlat(), setVecPredRegFlat(), setVecRegFlat(), status(), suspend(), takeOverFrom(), and threadId().

The documentation for this class was generated from the following files:
Generated on Tue Feb 8 2022 11:49:06 for gem5 by doxygen 1.8.17