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46 #include "debug/DynInst.hh"
47 #include "debug/IQ.hh"
48 #include "debug/O3PipeView.hh"
58 : seqNum(seq_num), staticInst(static_inst), cpu(_cpu),
59 _numSrcs(arrays.numSrcs), _numDests(arrays.numDests),
60 _flatDestIdx(arrays.flatDestIdx), _destIdx(arrays.destIdx),
61 _prevDestIdx(arrays.prevDestIdx), _srcIdx(arrays.srcIdx),
62 _readySrcIdx(arrays.readySrcIdx), macroop(_macroop)
85 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
98 :
DynInst(arrays, static_inst, _macroop, seq_num, _cpu)
106 :
DynInst(arrays, _staticInst, _macroop, 0, nullptr)
140 const auto num_dests = arrays.
numDests;
141 const auto num_srcs = arrays.numSrcs;
145 size_t inst_size =
count;
147 uintptr_t flat_dest_idx =
roundUp(inst + inst_size,
alignof(
RegId));
148 size_t flat_dest_idx_size =
sizeof(*arrays.flatDestIdx) * num_dests;
152 size_t dest_idx_size =
sizeof(*arrays.destIdx) * num_dests;
154 uintptr_t prev_dest_idx =
156 size_t prev_dest_idx_size =
sizeof(*arrays.prevDestIdx) * num_dests;
160 size_t src_idx_size =
sizeof(*arrays.srcIdx) * num_srcs;
162 uintptr_t ready_src_idx =
163 roundUp(src_idx + src_idx_size,
alignof(uint8_t));
164 size_t ready_src_idx_size =
165 sizeof(*arrays.readySrcIdx) * ((num_srcs + 7) / 8);
168 size_t total_size = ready_src_idx + ready_src_idx_size;
171 uint8_t *buf = (uint8_t *)::
operator new(total_size);
174 arrays.flatDestIdx = (
RegId *)(buf + flat_dest_idx);
176 arrays.prevDestIdx = (
PhysRegIdPtr *)(buf + prev_dest_idx);
178 arrays.readySrcIdx = (uint8_t *)(buf + ready_src_idx);
181 new (arrays.flatDestIdx)
RegId[num_dests];
185 new (arrays.readySrcIdx) uint8_t[num_srcs];
212 if (debug::O3PipeView) {
213 Tick fetch = fetchTick;
219 DPRINTFR(O3PipeView,
"O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
226 val = (decodeTick == -1) ? 0 : fetch + decodeTick;
227 DPRINTFR(O3PipeView,
"O3PipeView:decode:%llu\n",
val);
228 val = (renameTick == -1) ? 0 : fetch + renameTick;
229 DPRINTFR(O3PipeView,
"O3PipeView:rename:%llu\n",
val);
230 val = (dispatchTick == -1) ? 0 : fetch + dispatchTick;
231 DPRINTFR(O3PipeView,
"O3PipeView:dispatch:%llu\n",
val);
232 val = (issueTick == -1) ? 0 : fetch + issueTick;
233 DPRINTFR(O3PipeView,
"O3PipeView:issue:%llu\n",
val);
234 val = (completeTick == -1) ? 0 : fetch + completeTick;
235 DPRINTFR(O3PipeView,
"O3PipeView:complete:%llu\n",
val);
236 val = (commitTick == -1) ? 0 : fetch + commitTick;
238 Tick valS = (storeTick == -1) ? 0 : fetch + storeTick;
239 DPRINTFR(O3PipeView,
"O3PipeView:retire:%llu:store:%llu\n",
253 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
264 DynInst::dumpSNList()
266 std::set<InstSeqNum>::iterator sn_it =
cpu->snList.begin();
269 while (sn_it !=
cpu->snList.end()) {
270 cprintf(
"%i: [sn:%lli] not destroyed\n",
count, (*sn_it));
288 std::ostringstream
s;
298 DPRINTF(IQ,
"[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
405 assert(byte_enable.size() == size);
408 true,
nullptr, size,
addr, flags,
nullptr,
nullptr,
415 const unsigned int size = 8;
418 true,
nullptr, size, 0x0ul, flags,
nullptr,
nullptr,
427 assert(byte_enable.size() == size);
430 false,
data, size,
addr, flags, res,
nullptr,
445 false,
nullptr, size,
addr, flags,
nullptr,
void dumpInsts()
Debug function to print all instructions on the list.
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
CPU pushRequest function, forwards request to LSQ.
constexpr decltype(nullptr) NoFault
std::unique_ptr< PCStateBase > predPC
Predicted PC state after this instruction.
@ Squashed
Instruction has committed.
Fault initiateAcc()
Initiates the access.
void cprintf(const char *format, const Args &...args)
bool readySrcIdx(int idx) const
ThreadID threadNumber
The thread this instruction is from.
size_t numSrcRegs() const
Returns the number of source registers.
void setCanIssue()
Sets this instruction as ready to issue.
RequestPtr req
A pointer to the original request.
std::unique_ptr< PCStateBase > pc
PC state for this instruction.
bool isStoreConditional() const
std::bitset< NumStatus > status
The status of this BaseDynInst.
std::bitset< MaxFlags > instFlags
bool isPinnedRegsRenamed() const
Returns whether pinned registers are renamed.
InstSeqNum seqNum
The sequence number of the instruction.
size_t numDestRegs() const
Returns the number of destination registers.
const PCStateBase & pcState() const override
Read the PC state of this instruction.
PhysRegIdPtr * _prevDestIdx
ThreadState * thread
Pointer to the thread state.
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
void dump()
Dumps out contents of this BaseDynInst.
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
CPU * cpu
Pointer to the Impl's CPU object.
bool readyToIssue() const
Returns whether or not this instruction is ready to issue.
void markSrcRegReady()
Records that one of the source registers is ready.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
std::shared_ptr< FaultBase > Fault
void trap(const Fault &fault)
Traps to handle specified fault.
void incrNumPinnedWritesToComplete()
void setPinnedRegsSquashDone()
Sets dest registers' status updated after squash.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Fault execute()
Executes the instruction.
uint64_t Tick
Tick count type.
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
uint8_t readyRegs
How many source registers are ready.
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, InstSeqNum seq_num, CPU *cpu)
Fault completeAcc(PacketPtr pkt)
Completes the access.
void setSquashed()
Sets this instruction as squashed.
bool isPinnedRegsSquashDone() const
Return whether dest registers' pinning status updated after squash.
int instcount
Count of total number of dynamic instructions in flight.
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
void incrNumPinnedWrites()
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Trace::InstRecord * traceData
InstRecord that tracks this instructions.
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override
Fault initiateHtmCmd(Request::Flags flags) override
Initiate an HTM command, e.g.
bool isPinnedRegsWritten() const
Returns whether destination registers are written.
PhysRegIdPtr renamedDestIdx(int idx) const
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Fault fault
The kind of fault this instruction has generated.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint8_t * memData
Pointer to the data for the memory access.
Register ID: describe an architectural register with its class and index.
Generated on Tue Feb 8 2022 11:47:03 for gem5 by doxygen 1.8.17