dyn_inst.hh

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 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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#ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__
 
#include <algorithm>
#include <array>
#include <deque>
#include <list>
#include <string>
 
#include "base/refcnt.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exec_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/lsq_unit.hh"
#include "cpu/op_class.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "debug/HtmCpu.hh"
 
namespace gem5
{
 
class Packet;
 
namespace o3
{
 
class DynInst : public ExecContext, public RefCounted
{
  private:
    DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
            InstSeqNum seq_num, CPU *cpu);
 
  public:
    // The list of instructions iterator type.
    typedef typename std::list<DynInstPtr>::iterator ListIt;
 
    struct Arrays
    {
        size_t numSrcs;
        size_t numDests;
 
        RegId *flatDestIdx;
        PhysRegIdPtr *destIdx;
        PhysRegIdPtr *prevDestIdx;
        PhysRegIdPtr *srcIdx;
        uint8_t *readySrcIdx;
    };
 
    static void *operator new(size_t count, Arrays &arrays);
 
    DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
            const StaticInstPtr &macroop, InstSeqNum seq_num, CPU *cpu);
 
    DynInst(const Arrays &arrays, const StaticInstPtr &staticInst,
            const StaticInstPtr &macroop, const PCStateBase &pc,
            const PCStateBase &pred_pc, InstSeqNum seq_num, CPU *cpu);
 
    DynInst(const Arrays &arrays, const StaticInstPtr &_staticInst,
            const StaticInstPtr &_macroop);
 
    ~DynInst();
 
    Fault execute();
 
    Fault initiateAcc();
 
    Fault completeAcc(PacketPtr pkt);
 
    InstSeqNum seqNum = 0;
 
    const StaticInstPtr staticInst;
 
    CPU *cpu = nullptr;
 
    BaseCPU *getCpuPtr() { return cpu; }
 
    ThreadState *thread = nullptr;
 
    Fault fault = NoFault;
 
    Trace::InstRecord *traceData = nullptr;
 
  protected:
    enum Status
    {
        IqEntry,                 
        RobEntry,                
        LsqEntry,                
        Completed,               
        ResultReady,             
        CanIssue,                
        Issued,                  
        Executed,                
        CanCommit,               
        AtCommit,                
        Committed,               
        Squashed,                
        SquashedInIQ,            
        SquashedInLSQ,           
        SquashedInROB,           
        PinnedRegsRenamed,       
        PinnedRegsWritten,       
        PinnedRegsSquashDone,    
        RecoverInst,             
        BlockingInst,            
        ThreadsyncWait,          
        SerializeBefore,         
        SerializeAfter,          
        SerializeHandled,        
        NumStatus
    };
 
    enum Flags
    {
        NotAnInst,
        TranslationStarted,
        TranslationCompleted,
        PossibleLoadViolation,
        HitExternalSnoop,
        EffAddrValid,
        RecordResult,
        Predicate,
        MemAccPredicate,
        PredTaken,
        IsStrictlyOrdered,
        ReqMade,
        MemOpDone,
        HtmFromTransaction,
        MaxFlags
    };
 
  private:
    /* An amalgamation of a lot of boolean values into one */
    std::bitset<MaxFlags> instFlags;
 
    std::bitset<NumStatus> status;
 
  protected:
    std::queue<InstResult> instResult;
 
    std::unique_ptr<PCStateBase> pc;
 
    std::vector<RegVal> _destMiscRegVal;
 
    std::vector<short> _destMiscRegIdx;
 
    size_t _numSrcs;
    size_t _numDests;
 
    // Flattened register index of the destination registers of this
    // instruction.
    RegId *_flatDestIdx;
 
    // Physical register index of the destination registers of this
    // instruction.
    PhysRegIdPtr *_destIdx;
 
    // Physical register index of the previous producers of the
    // architected destinations.
    PhysRegIdPtr *_prevDestIdx;
 
    // Physical register index of the source registers of this instruction.
    PhysRegIdPtr *_srcIdx;
 
    // Whether or not the source register is ready, one bit per register.
    uint8_t *_readySrcIdx;
 
  public:
    size_t numSrcs() const { return _numSrcs; }
    size_t numDests() const { return _numDests; }
 
    // Returns the flattened register index of the idx'th destination
    // register.
    const RegId &
    flattenedDestIdx(int idx) const
    {
        return _flatDestIdx[idx];
    }
 
    // Flattens a destination architectural register index into a logical
    // index.
    void
    flattenedDestIdx(int idx, const RegId &reg_id)
    {
        _flatDestIdx[idx] = reg_id;
    }
 
    // Returns the physical register index of the idx'th destination
    // register.
    PhysRegIdPtr
    renamedDestIdx(int idx) const
    {
        return _destIdx[idx];
    }
 
    // Set the renamed dest register id.
    void
    renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
    {
        _destIdx[idx] = phys_reg_id;
    }
 
    // Returns the physical register index of the previous physical
    // register that remapped to the same logical register index.
    PhysRegIdPtr
    prevDestIdx(int idx) const
    {
        return _prevDestIdx[idx];
    }
 
    // Set the previous renamed dest register id.
    void
    prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
    {
        _prevDestIdx[idx] = phys_reg_id;
    }
 
    // Returns the physical register index of the i'th source register.
    PhysRegIdPtr
    renamedSrcIdx(int idx) const
    {
        return _srcIdx[idx];
    }
 
    void
    renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
    {
        _srcIdx[idx] = phys_reg_id;
    }
 
    bool
    readySrcIdx(int idx) const
    {
        uint8_t &byte = _readySrcIdx[idx / 8];
        return bits(byte, idx % 8);
    }
 
    void
    readySrcIdx(int idx, bool ready)
    {
        uint8_t &byte = _readySrcIdx[idx / 8];
        replaceBits(byte, idx % 8, ready ? 1 : 0);
    }
 
    ThreadID threadNumber = 0;
 
    ListIt instListIt;
 
 
    std::unique_ptr<PCStateBase> predPC;
 
    const StaticInstPtr macroop;
 
    uint8_t readyRegs = 0;
 
  public:
 
    Addr effAddr = 0;
 
    Addr physEffAddr = 0;
 
    unsigned memReqFlags = 0;
 
    unsigned effSize;
 
    uint8_t *memData = nullptr;
 
    ssize_t lqIdx = -1;
    typename LSQUnit::LQIterator lqIt;
 
    ssize_t sqIdx = -1;
    typename LSQUnit::SQIterator sqIt;
 
 
 
    LSQ::LSQRequest *savedRequest;
 
    // Need a copy of main request pointer to verify on writes.
    RequestPtr reqToVerify;
 
  public:
    void recordResult(bool f) { instFlags[RecordResult] = f; }
 
    bool effAddrValid() const { return instFlags[EffAddrValid]; }
    void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
 
    bool memOpDone() const { return instFlags[MemOpDone]; }
    void memOpDone(bool f) { instFlags[MemOpDone] = f; }
 
    bool notAnInst() const { return instFlags[NotAnInst]; }
    void setNotAnInst() { instFlags[NotAnInst] = true; }
 
 
    //
    // INSTRUCTION EXECUTION
    //
 
    void
    demapPage(Addr vaddr, uint64_t asn) override
    {
        cpu->demapPage(vaddr, asn);
    }
 
    Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
            const std::vector<bool> &byte_enable) override;
 
    Fault initiateHtmCmd(Request::Flags flags) override;
 
    Fault writeMem(uint8_t *data, unsigned size, Addr addr,
                   Request::Flags flags, uint64_t *res,
                   const std::vector<bool> &byte_enable) override;
 
    Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
                         AtomicOpFunctorPtr amo_op) override;
 
    bool translationStarted() const { return instFlags[TranslationStarted]; }
    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
 
    bool
    translationCompleted() const
    {
        return instFlags[TranslationCompleted];
    }
    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
 
    bool
    possibleLoadViolation() const
    {
        return instFlags[PossibleLoadViolation];
    }
    void
    possibleLoadViolation(bool f)
    {
        instFlags[PossibleLoadViolation] = f;
    }
 
    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
 
    bool
    isTranslationDelayed() const
    {
        return (translationStarted() && !translationCompleted());
    }
 
  public:
#ifdef DEBUG
    void dumpSNList();
#endif
 
    void
    renameDestReg(int idx, PhysRegIdPtr renamed_dest,
                  PhysRegIdPtr previous_rename)
    {
        renamedDestIdx(idx, renamed_dest);
        prevDestIdx(idx, previous_rename);
        if (renamed_dest->isPinned())
            setPinnedRegsRenamed();
    }
 
    void
    renameSrcReg(int idx, PhysRegIdPtr renamed_src)
    {
        renamedSrcIdx(idx, renamed_src);
    }
 
    void dump();
 
    void dump(std::string &outstring);
 
    int cpuId() const { return cpu->cpuId(); }
 
    uint32_t socketId() const { return cpu->socketId(); }
 
    RequestorID requestorId() const { return cpu->dataRequestorId(); }
 
    ContextID contextId() const { return thread->contextId(); }
 
    Fault getFault() const { return fault; }
    Fault& getFault() { return fault; }
 
    bool doneTargCalc() { return false; }
 
    void setPredTarg(const PCStateBase &pred_pc) { set(predPC, pred_pc); }
 
    const PCStateBase &readPredTarg() { return *predPC; }
 
    bool readPredTaken() { return instFlags[PredTaken]; }
 
    void
    setPredTaken(bool predicted_taken)
    {
        instFlags[PredTaken] = predicted_taken;
    }
 
    bool
    mispredicted()
    {
        std::unique_ptr<PCStateBase> next_pc(pc->clone());
        staticInst->advancePC(*next_pc);
        return *next_pc != *predPC;
    }
 
    //
    //  Instruction types.  Forward checks to StaticInst object.
    //
    bool isNop()          const { return staticInst->isNop(); }
    bool isMemRef()       const { return staticInst->isMemRef(); }
    bool isLoad()         const { return staticInst->isLoad(); }
    bool isStore()        const { return staticInst->isStore(); }
    bool isAtomic()       const { return staticInst->isAtomic(); }
    bool isStoreConditional() const
    { return staticInst->isStoreConditional(); }
    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
    bool isInteger()      const { return staticInst->isInteger(); }
    bool isFloating()     const { return staticInst->isFloating(); }
    bool isVector()       const { return staticInst->isVector(); }
    bool isControl()      const { return staticInst->isControl(); }
    bool isCall()         const { return staticInst->isCall(); }
    bool isReturn()       const { return staticInst->isReturn(); }
    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
    bool isSerializing()  const { return staticInst->isSerializing(); }
    bool
    isSerializeBefore() const
    {
        return staticInst->isSerializeBefore() || status[SerializeBefore];
    }
    bool
    isSerializeAfter() const
    {
        return staticInst->isSerializeAfter() || status[SerializeAfter];
    }
    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
    bool isFullMemBarrier()   const { return staticInst->isFullMemBarrier(); }
    bool isReadBarrier() const { return staticInst->isReadBarrier(); }
    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
    bool isQuiesce() const { return staticInst->isQuiesce(); }
    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
    bool isSyscall() const { return staticInst->isSyscall(); }
    bool isMacroop() const { return staticInst->isMacroop(); }
    bool isMicroop() const { return staticInst->isMicroop(); }
    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
    // hardware transactional memory
    bool isHtmStart() const { return staticInst->isHtmStart(); }
    bool isHtmStop() const { return staticInst->isHtmStop(); }
    bool isHtmCancel() const { return staticInst->isHtmCancel(); }
    bool isHtmCmd() const { return staticInst->isHtmCmd(); }
 
    uint64_t
    getHtmTransactionUid() const override
    {
        assert(instFlags[HtmFromTransaction]);
        return htmUid;
    }
 
    uint64_t
    newHtmTransactionUid() const override
    {
        panic("Not yet implemented\n");
        return 0;
    }
 
    bool
    inHtmTransactionalState() const override
    {
        return instFlags[HtmFromTransaction];
    }
 
    uint64_t
    getHtmTransactionalDepth() const override
    {
        if (inHtmTransactionalState())
            return htmDepth;
        else
            return 0;
    }
 
    void
    setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
    {
        instFlags.set(HtmFromTransaction);
        htmUid = htm_uid;
        htmDepth = htm_depth;
    }
 
    void
    clearHtmTransactionalState()
    {
        if (inHtmTransactionalState()) {
            DPRINTF(HtmCpu,
                "clearing instuction's transactional state htmUid=%u\n",
                getHtmTransactionUid());
 
            instFlags.reset(HtmFromTransaction);
            htmUid = -1;
            htmDepth = 0;
        }
    }
 
    void setSerializeBefore() { status.set(SerializeBefore); }
 
    void clearSerializeBefore() { status.reset(SerializeBefore); }
 
    bool isTempSerializeBefore() { return status[SerializeBefore]; }
 
    void setSerializeAfter() { status.set(SerializeAfter); }
 
    void clearSerializeAfter() { status.reset(SerializeAfter); }
 
    bool isTempSerializeAfter() { return status[SerializeAfter]; }
 
    void setSerializeHandled() { status.set(SerializeHandled); }
 
    bool isSerializeHandled() { return status[SerializeHandled]; }
 
    OpClass opClass() const { return staticInst->opClass(); }
 
    std::unique_ptr<PCStateBase>
    branchTarget() const
    {
        return staticInst->branchTarget(*pc);
    }
 
    size_t numSrcRegs() const { return numSrcs(); }
 
    size_t numDestRegs() const { return numDests(); }
 
    // the following are used to track physical register usage
    // for machines with separate int & FP reg files
    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
    int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
    int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
    int8_t
    numVecElemDestRegs() const
    {
        return staticInst->numVecElemDestRegs();
    }
    int8_t
    numVecPredDestRegs() const
    {
        return staticInst->numVecPredDestRegs();
    }
 
    const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
 
    const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
 
    uint8_t resultSize() { return instResult.size(); }
 
    InstResult
    popResult(InstResult dflt=InstResult())
    {
        if (!instResult.empty()) {
            InstResult t = instResult.front();
            instResult.pop();
            return t;
        }
        return dflt;
    }
 
    template<typename T>
    void
    setResult(T &&t)
    {
        if (instFlags[RecordResult]) {
            instResult.emplace(std::forward<T>(t));
        }
    }
    void markSrcRegReady();
 
    void markSrcRegReady(RegIndex src_idx);
 
    void setCompleted() { status.set(Completed); }
 
    bool isCompleted() const { return status[Completed]; }
 
    void setResultReady() { status.set(ResultReady); }
 
    bool isResultReady() const { return status[ResultReady]; }
 
    void setCanIssue() { status.set(CanIssue); }
 
    bool readyToIssue() const { return status[CanIssue]; }
 
    void clearCanIssue() { status.reset(CanIssue); }
 
    void setIssued() { status.set(Issued); }
 
    bool isIssued() const { return status[Issued]; }
 
    void clearIssued() { status.reset(Issued); }
 
    void setExecuted() { status.set(Executed); }
 
    bool isExecuted() const { return status[Executed]; }
 
    void setCanCommit() { status.set(CanCommit); }
 
    void clearCanCommit() { status.reset(CanCommit); }
 
    bool readyToCommit() const { return status[CanCommit]; }
 
    void setAtCommit() { status.set(AtCommit); }
 
    bool isAtCommit() { return status[AtCommit]; }
 
    void setCommitted() { status.set(Committed); }
 
    bool isCommitted() const { return status[Committed]; }
 
    void setSquashed();
 
    bool isSquashed() const { return status[Squashed]; }
 
    //Instruction Queue Entry
    //-----------------------
    void setInIQ() { status.set(IqEntry); }
 
    void clearInIQ() { status.reset(IqEntry); }
 
    bool isInIQ() const { return status[IqEntry]; }
 
    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
 
    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
 
 
    //Load / Store Queue Functions
    //-----------------------
    void setInLSQ() { status.set(LsqEntry); }
 
    void removeInLSQ() { status.reset(LsqEntry); }
 
    bool isInLSQ() const { return status[LsqEntry]; }
 
    void setSquashedInLSQ() { status.set(SquashedInLSQ); status.set(Squashed);}
 
    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
 
 
    //Reorder Buffer Functions
    //-----------------------
    void setInROB() { status.set(RobEntry); }
 
    void clearInROB() { status.reset(RobEntry); }
 
    bool isInROB() const { return status[RobEntry]; }
 
    void setSquashedInROB() { status.set(SquashedInROB); }
 
    bool isSquashedInROB() const { return status[SquashedInROB]; }
 
    bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
 
    void
    setPinnedRegsRenamed()
    {
        assert(!status[PinnedRegsSquashDone]);
        assert(!status[PinnedRegsWritten]);
        status.set(PinnedRegsRenamed);
    }
 
    bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
 
    void
    setPinnedRegsWritten()
    {
        assert(!status[PinnedRegsSquashDone]);
        assert(status[PinnedRegsRenamed]);
        status.set(PinnedRegsWritten);
    }
 
    bool
    isPinnedRegsSquashDone() const
    {
        return status[PinnedRegsSquashDone];
    }
 
    void
    setPinnedRegsSquashDone()
    {
        assert(!status[PinnedRegsSquashDone]);
        status.set(PinnedRegsSquashDone);
    }
 
    const PCStateBase &
    pcState() const override
    {
        return *pc;
    }
 
    void pcState(const PCStateBase &val) override { set(pc, val); }
 
    bool readPredicate() const override { return instFlags[Predicate]; }
 
    void
    setPredicate(bool val) override
    {
        instFlags[Predicate] = val;
 
        if (traceData) {
            traceData->setPredicate(val);
        }
    }
 
    bool
    readMemAccPredicate() const override
    {
        return instFlags[MemAccPredicate];
    }
 
    void
    setMemAccPredicate(bool val) override
    {
        instFlags[MemAccPredicate] = val;
    }
 
    void setTid(ThreadID tid) { threadNumber = tid; }
 
    void setThreadState(ThreadState *state) { thread = state; }
 
    gem5::ThreadContext *tcBase() const override { return thread->getTC(); }
 
  public:
    bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
    void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
 
    bool hasRequest() const { return instFlags[ReqMade]; }
    void setRequest() { instFlags[ReqMade] = true; }
 
    ListIt &getInstListIt() { return instListIt; }
 
    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
 
  public:
    unsigned int
    readStCondFailures() const override
    {
        return thread->storeCondFailures;
    }
 
    void
    setStCondFailures(unsigned int sc_failures) override
    {
        thread->storeCondFailures = sc_failures;
    }
 
  public:
    // monitor/mwait funtions
    void
    armMonitor(Addr address) override
    {
        cpu->armMonitor(threadNumber, address);
    }
    bool
    mwait(PacketPtr pkt) override
    {
        return cpu->mwait(threadNumber, pkt);
    }
    void
    mwaitAtomic(gem5::ThreadContext *tc) override
    {
        return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
    }
    AddressMonitor *
    getAddrMonitor() override
    {
        return cpu->getCpuAddrMonitor(threadNumber);
    }
 
  private:
    // hardware transactional memory
    uint64_t htmUid = -1;
    uint64_t htmDepth = 0;
 
  public:
#if TRACING_ON
    // Value -1 indicates that particular phase
    // hasn't happened (yet).
    Tick fetchTick = -1;      // instruction fetch is completed.
    int32_t decodeTick = -1;  // instruction enters decode phase
    int32_t renameTick = -1;  // instruction enters rename phase
    int32_t dispatchTick = -1;
    int32_t issueTick = -1;
    int32_t completeTick = -1;
    int32_t commitTick = -1;
    int32_t storeTick = -1;
#endif
 
    /* Values used by LoadToUse stat */
    Tick firstIssue = -1;
    Tick lastWakeDependents = -1;
 
    RegVal
    readMiscReg(int misc_reg) override
    {
        return cpu->readMiscReg(misc_reg, threadNumber);
    }
 
    void
    setMiscReg(int misc_reg, RegVal val) override
    {
        for (auto &idx: _destMiscRegIdx) {
            if (idx == misc_reg)
                return;
        }
 
        _destMiscRegIdx.push_back(misc_reg);
        _destMiscRegVal.push_back(val);
    }
 
    RegVal
    readMiscRegOperand(const StaticInst *si, int idx) override
    {
        const RegId& reg = si->srcRegIdx(idx);
        assert(reg.is(MiscRegClass));
        return cpu->readMiscReg(reg.index(), threadNumber);
    }
 
    void
    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
    {
        const RegId& reg = si->destRegIdx(idx);
        assert(reg.is(MiscRegClass));
        setMiscReg(reg.index(), val);
    }
 
    void
    updateMiscRegs()
    {
        // @todo: Pretty convoluted way to avoid squashing from happening when
        // using the TC during an instruction's execution (specifically for
        // instructions that have side-effects that use the TC).  Fix this.
        // See cpu/o3/dyn_inst_impl.hh.
        bool no_squash_from_TC = thread->noSquashFromTC;
        thread->noSquashFromTC = true;
 
        for (int i = 0; i < _destMiscRegIdx.size(); i++)
            cpu->setMiscReg(
                _destMiscRegIdx[i], _destMiscRegVal[i], threadNumber);
 
        thread->noSquashFromTC = no_squash_from_TC;
    }
 
    void
    forwardOldRegs()
    {
 
        for (int idx = 0; idx < numDestRegs(); idx++) {
            PhysRegIdPtr prev_phys_reg = prevDestIdx(idx);
            const RegId& original_dest_reg = staticInst->destRegIdx(idx);
            switch (original_dest_reg.classValue()) {
              case IntRegClass:
                setIntRegOperand(staticInst.get(), idx,
                        cpu->readIntReg(prev_phys_reg));
                break;
              case FloatRegClass:
                setFloatRegOperandBits(staticInst.get(), idx,
                        cpu->readFloatReg(prev_phys_reg));
                break;
              case VecRegClass:
                setVecRegOperand(staticInst.get(), idx,
                        cpu->readVecReg(prev_phys_reg));
                break;
              case VecElemClass:
                setVecElemOperand(staticInst.get(), idx,
                        cpu->readVecElem(prev_phys_reg));
                break;
              case VecPredRegClass:
                setVecPredRegOperand(staticInst.get(), idx,
                        cpu->readVecPredReg(prev_phys_reg));
                break;
              case CCRegClass:
                setCCRegOperand(staticInst.get(), idx,
                        cpu->readCCReg(prev_phys_reg));
                break;
              case MiscRegClass:
                // no need to forward misc reg values
                break;
              default:
                panic("Unknown register class: %d",
                        (int)original_dest_reg.classValue());
            }
        }
    }
    void trap(const Fault &fault);
 
  public:
 
    // The register accessor methods provide the index of the
    // instruction's operand (e.g., 0 or 1), not the architectural
    // register index, to simplify the implementation of register
    // renaming.  We find the architectural register index by indexing
    // into the instruction's own operand index table.  Note that a
    // raw pointer to the StaticInst is provided instead of a
    // ref-counted StaticInstPtr to redice overhead.  This is fine as
    // long as these methods don't copy the pointer into any long-term
    // storage (which is pretty hard to imagine they would have reason
    // to do).
 
    RegVal
    readIntRegOperand(const StaticInst *si, int idx) override
    {
        return cpu->readIntReg(renamedSrcIdx(idx));
    }
 
    RegVal
    readFloatRegOperandBits(const StaticInst *si, int idx) override
    {
        return cpu->readFloatReg(renamedSrcIdx(idx));
    }
 
    const TheISA::VecRegContainer&
    readVecRegOperand(const StaticInst *si, int idx) const override
    {
        return cpu->readVecReg(renamedSrcIdx(idx));
    }
 
    TheISA::VecRegContainer&
    getWritableVecRegOperand(const StaticInst *si, int idx) override
    {
        return cpu->getWritableVecReg(renamedDestIdx(idx));
    }
 
    RegVal
    readVecElemOperand(const StaticInst *si, int idx) const override
    {
        return cpu->readVecElem(renamedSrcIdx(idx));
    }
 
    const TheISA::VecPredRegContainer&
    readVecPredRegOperand(const StaticInst *si, int idx) const override
    {
        return cpu->readVecPredReg(renamedSrcIdx(idx));
    }
 
    TheISA::VecPredRegContainer&
    getWritableVecPredRegOperand(const StaticInst *si, int idx) override
    {
        return cpu->getWritableVecPredReg(renamedDestIdx(idx));
    }
 
    RegVal
    readCCRegOperand(const StaticInst *si, int idx) override
    {
        return cpu->readCCReg(renamedSrcIdx(idx));
    }
 
    void
    setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
    {
        cpu->setIntReg(renamedDestIdx(idx), val);
        setResult(val);
    }
 
    void
    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
    {
        cpu->setFloatReg(renamedDestIdx(idx), val);
        setResult(val);
    }
 
    void
    setVecRegOperand(const StaticInst *si, int idx,
                     const TheISA::VecRegContainer& val) override
    {
        cpu->setVecReg(renamedDestIdx(idx), val);
        setResult(val);
    }
 
    void
    setVecElemOperand(const StaticInst *si, int idx, RegVal val) override
    {
        int reg_idx = idx;
        cpu->setVecElem(renamedDestIdx(reg_idx), val);
        setResult(val);
    }
 
    void
    setVecPredRegOperand(const StaticInst *si, int idx,
                         const TheISA::VecPredRegContainer& val) override
    {
        cpu->setVecPredReg(renamedDestIdx(idx), val);
        setResult(val);
    }
 
    void
    setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
    {
        cpu->setCCReg(renamedDestIdx(idx), val);
        setResult(val);
    }
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_DYN_INST_HH__