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decoder.hh
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40 
41 #ifndef __ARCH_ARM_DECODER_HH__
42 #define __ARCH_ARM_DECODER_HH__
43 
44 #include <cassert>
45 
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/types.hh"
49 #include "arch/generic/decoder.hh"
50 #include "base/types.hh"
51 #include "cpu/static_inst.hh"
52 #include "debug/Decode.hh"
53 #include "enums/DecoderFlavor.hh"
54 #include "params/ArmDecoder.hh"
55 
56 namespace gem5
57 {
58 
59 namespace ArmISA
60 {
61 
62 class ISA;
63 class Decoder : public InstDecoder
64 {
65  protected:
66  //The extended machine instruction being generated
68  uint32_t data;
69  bool bigThumb;
70  int offset;
71  bool foundIt;
72  ITSTATE itBits;
73 
74  int fpscrLen;
76 
81  int sveLen;
82 
83  enums::DecoderFlavor decoderFlavor;
84 
88 
93  void process();
94 
99  void consumeBytes(int numBytes);
100 
114 
126  {
127  StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
128  DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
129  si->getName(), mach_inst);
130  return si;
131  }
132 
133  public: // Decoder API
134  Decoder(const ArmDecoderParams &params);
135 
137  void reset() override;
138 
139  void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
140 
141  StaticInstPtr decode(PCStateBase &pc) override;
142 
143  public: // ARM-specific decoder state manipulation
144  void
145  setContext(FPSCR fpscr)
146  {
147  fpscrLen = fpscr.len;
148  fpscrStride = fpscr.stride;
149  }
150 
151  void
152  setSveLen(uint8_t len)
153  {
154  sveLen = len;
155  }
156 };
157 
158 } // namespace ArmISA
159 } // namespace gem5
160 
161 #endif // __ARCH_ARM_DECODER_HH__
gem5::ArmISA::Decoder::data
uint32_t data
Definition: decoder.hh:68
gem5::ArmISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decode a machine instruction without calling the cache.
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:445
gem5::ArmISA::Decoder::setContext
void setContext(FPSCR fpscr)
Definition: decoder.hh:145
decode_cache.hh
gem5::ArmISA::Decoder::offset
int offset
Definition: decoder.hh:70
gem5::ArmISA::Decoder::fpscrLen
int fpscrLen
Definition: decoder.hh:74
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::ArmISA::Decoder::setSveLen
void setSveLen(uint8_t len)
Definition: decoder.hh:152
gem5::ArmISA::Decoder::foundIt
bool foundIt
Definition: decoder.hh:71
gem5::ArmISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:86
types.hh
gem5::ArmISA::Decoder::moreBytes
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.cc:155
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::Decoder::reset
void reset() override
Reset the decoders internal state.
Definition: decoder.cc:69
decoder.hh
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::Decoder::sveLen
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:81
gem5::ArmISA::Decoder::consumeBytes
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:146
gem5::ArmISA::Decoder::decoderFlavor
enums::DecoderFlavor decoderFlavor
Definition: decoder.hh:83
gem5::ArmISA::Decoder::fpscrStride
int fpscrStride
Definition: decoder.hh:75
gem5::ArmISA::Decoder
Definition: decoder.hh:63
gem5::ArmISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:67
static_inst.hh
gem5::ArmISA::Decoder::process
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:79
gem5::ArmISA::si
Bitfield< 6 > si
Definition: misc_types.hh:773
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::Decoder::bigThumb
bool bigThumb
Definition: decoder.hh:69
gem5::ArmISA::Decoder::Decoder
Decoder(const ArmDecoderParams &params)
Definition: decoder.cc:57
types.hh
misc.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:125
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::Decoder::itBits
ITSTATE itBits
Definition: decoder.hh:72
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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