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decoder.cc
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40 
41 #include "arch/arm/decoder.hh"
42 
43 #include "arch/arm/isa.hh"
44 #include "arch/arm/utility.hh"
45 #include "base/trace.hh"
46 #include "debug/Decoder.hh"
47 #include "sim/full_system.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 
56 
57 Decoder::Decoder(const ArmDecoderParams &params)
58  : InstDecoder(params, &data),
59  dvmEnabled(params.dvm_enabled),
60  data(0), fpscrLen(0), fpscrStride(0),
61  decoderFlavor(dynamic_cast<ISA *>(params.isa)->decoderFlavor())
62 {
63  reset();
64 
65  // Initialize SVE vector length
66  sveLen = (dynamic_cast<ISA *>(params.isa)
67  ->getCurSveVecLenInBitsAtReset() >> 7) - 1;
68 
69  if (dvmEnabled) {
70  warn_once(
71  "DVM Ops instructions are micro-architecturally "
72  "modelled as loads. This will tamper the effective "
73  "number of loads stat\n");
74  }
75 }
76 
77 void
79 {
81  bigThumb = false;
82  offset = 0;
83  emi = 0;
84  foundIt = false;
85 }
86 
87 void
89 {
90  // emi is typically ready, with some caveats below...
91  instDone = true;
92 
93  if (!emi.thumb) {
94  emi.instBits = data;
95  if (!emi.aarch64) {
96  emi.sevenAndFour = bits(data, 7) && bits(data, 4);
97  emi.isMisc = (bits(data, 24, 23) == 0x2 &&
98  bits(data, 20) == 0);
99  }
100  consumeBytes(4);
101  DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi);
102  } else {
103  uint16_t word = (data >> (offset * 8));
104  if (bigThumb) {
105  // A 32 bit thumb inst is half collected.
106  emi.instBits = emi.instBits | word;
107  bigThumb = false;
108  consumeBytes(2);
109  DPRINTF(Decoder, "Second half of 32 bit Thumb: %#x.\n",
110  emi.instBits);
111  } else {
112  uint16_t highBits = word & 0xF800;
113  if (highBits == 0xE800 || highBits == 0xF000 ||
114  highBits == 0xF800) {
115  // The start of a 32 bit thumb inst.
116  emi.bigThumb = 1;
117  if (offset == 0) {
118  // We've got the whole thing.
119  emi.instBits = (data >> 16) | (data << 16);
120  DPRINTF(Decoder, "All of 32 bit Thumb: %#x.\n",
121  emi.instBits);
122  consumeBytes(4);
123  } else {
124  // We only have the first half word.
126  "First half of 32 bit Thumb.\n");
127  emi.instBits = (uint32_t)word << 16;
128  bigThumb = true;
129  consumeBytes(2);
130  // emi not ready yet.
131  instDone = false;
132  }
133  } else {
134  // A 16 bit thumb inst.
135  consumeBytes(2);
136  emi.instBits = word;
137  // Set the condition code field artificially.
138  emi.condCode = COND_UC;
139  DPRINTF(Decoder, "16 bit Thumb: %#x.\n",
140  emi.instBits);
141  if (bits(word, 15, 8) == 0xbf &&
142  bits(word, 3, 0) != 0x0) {
143  foundIt = true;
144  itBits = bits(word, 7, 0);
146  "IT detected, cond = %#x, mask = %#x\n",
147  itBits.cond, itBits.mask);
148  }
149  }
150  }
151  }
152 }
153 
154 void
156 {
157  offset += numBytes;
158  assert(offset <= sizeof(data) || emi.decoderFault);
159  if (offset == sizeof(data))
160  outOfBytes = true;
161 }
162 
163 void
164 Decoder::moreBytes(const PCStateBase &_pc, Addr fetchPC)
165 {
166  auto &pc = _pc.as<PCState>();
167  data = letoh(data);
168  offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
169  emi.thumb = pc.thumb();
170  emi.aarch64 = pc.aarch64();
171  emi.fpscrLen = fpscrLen;
172  emi.fpscrStride = fpscrStride;
173  emi.sveLen = sveLen;
174 
175  const Addr alignment(pc.thumb() ? 0x1 : 0x3);
176  emi.decoderFault = static_cast<uint8_t>(
177  pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK);
178 
179  outOfBytes = false;
180  process();
181 }
182 
185 {
186  if (!instDone)
187  return NULL;
188 
189  auto &pc = _pc.as<PCState>();
190 
191  const int inst_size((!emi.thumb || emi.bigThumb) ? 4 : 2);
192  ExtMachInst this_emi(emi);
193 
194  pc.npc(pc.pc() + inst_size);
195  if (foundIt)
196  pc.nextItstate(itBits);
197  this_emi.itstate = pc.itstate();
198  this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
199  this_emi.debugStep = pc.debugStep() ? 1 : 0;
200  pc.size(inst_size);
201 
202  emi = 0;
203  instDone = false;
204  foundIt = false;
205 
206  return decode(this_emi, pc.instAddr());
207 }
208 
209 } // namespace ArmISA
210 } // namespace gem5
gem5::ArmISA::fpscrLen
Bitfield< 39, 37 > fpscrLen
Definition: types.hh:76
gem5::ArmISA::fpscrStride
Bitfield< 41, 40 > fpscrStride
Definition: types.hh:75
gem5::ArmISA::Decoder::data
uint32_t data
Definition: decoder.hh:72
gem5::ArmISA::UNALIGNED
@ UNALIGNED
Unaligned instruction fault.
Definition: types.hh:359
sc_dt::word
unsigned int word
Definition: scfx_mant.hh:96
data
const char data[]
Definition: circlebuf.test.cc:48
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::Decoder::offset
int offset
Definition: decoder.hh:74
gem5::ArmISA::Decoder::fpscrLen
int fpscrLen
Definition: decoder.hh:78
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::ArmISA::Decoder::foundIt
bool foundIt
Definition: decoder.hh:75
gem5::ArmISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:90
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::Decoder::moreBytes
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.cc:164
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::ArmISA::Decoder::reset
void reset() override
Reset the decoders internal state.
Definition: decoder.cc:78
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::Decoder::sveLen
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:85
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:99
isa.hh
gem5::ArmISA::Decoder::consumeBytes
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:155
gem5::ArmISA::Decoder::fpscrStride
int fpscrStride
Definition: decoder.hh:79
gem5::ArmISA::Decoder
Definition: decoder.hh:63
gem5::ArmISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:71
gem5::InstDecoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:50
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::Decoder::dvmEnabled
const bool dvmEnabled
True if the decoder should emit DVM Ops (treated as Loads)
Definition: decoder.hh:67
gem5::ArmISA::Decoder::process
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:88
gem5::InstDecoder::reset
virtual void reset()
Definition: decoder.hh:63
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
utility.hh
full_system.hh
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::Decoder::bigThumb
bool bigThumb
Definition: decoder.hh:73
gem5::ArmISA::Decoder::Decoder
Decoder(const ArmDecoderParams &params)
Definition: decoder.cc:57
gem5::InstDecoder::instDone
bool instDone
Definition: decoder.hh:49
gem5::ArmISA::OK
@ OK
No fault.
Definition: types.hh:358
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
trace.hh
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ArmISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:129
decoder.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::Decoder::itBits
ITSTATE itBits
Definition: decoder.hh:76

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