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46 #include "debug/Decoder.hh"
59 dvmEnabled(params.dvm_enabled),
61 decoderFlavor(dynamic_cast<
ISA *>(params.isa)->decoderFlavor())
67 ->getCurSveVecLenInBitsAtReset() >> 7) - 1;
71 "DVM Ops instructions are micro-architecturally "
72 "modelled as loads. This will tamper the effective "
73 "number of loads stat\n");
112 uint16_t highBits =
word & 0xF800;
113 if (highBits == 0xE800 || highBits == 0xF000 ||
114 highBits == 0xF800) {
126 "First half of 32 bit Thumb.\n");
127 emi.instBits = (uint32_t)
word << 16;
146 "IT detected, cond = %#x, mask = %#x\n",
168 offset = (fetchPC >=
pc.instAddr()) ? 0 :
pc.instAddr() - fetchPC;
169 emi.thumb =
pc.thumb();
170 emi.aarch64 =
pc.aarch64();
175 const Addr alignment(
pc.thumb() ? 0x1 : 0x3);
176 emi.decoderFault =
static_cast<uint8_t
>(
191 const int inst_size((!
emi.thumb ||
emi.bigThumb) ? 4 : 2);
194 pc.npc(
pc.pc() + inst_size);
197 this_emi.itstate =
pc.itstate();
198 this_emi.illegalExecution =
pc.illegalExec() ? 1 : 0;
199 this_emi.debugStep =
pc.debugStep() ? 1 : 0;
206 return decode(this_emi,
pc.instAddr());
Bitfield< 39, 37 > fpscrLen
Bitfield< 41, 40 > fpscrStride
@ UNALIGNED
Unaligned instruction fault.
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
void reset() override
Reset the decoders internal state.
const Params & params() const
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
const bool dvmEnabled
True if the decoder should emit DVM Ops (treated as Loads)
void process()
Pre-decode an instruction from the current state of the decoder.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Decoder(const ArmDecoderParams ¶ms)
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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