cc.hh

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/*
 * Copyright (c) 2014 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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#ifndef __ARCH_ARM_REGS_CC_HH__
#define __ARCH_ARM_REGS_CC_HH__
 
#include "cpu/reg_class.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
namespace cc_reg
{
 
enum : RegIndex
{
    _NzIdx,
    _CIdx,
    _VIdx,
    _GeIdx,
    _FpIdx,
    _ZeroIdx,
    NumRegs
};
 
inline constexpr RegId
    Nz(CCRegClass, _NzIdx),
    C(CCRegClass, _CIdx),
    V(CCRegClass, _VIdx),
    Ge(CCRegClass, _GeIdx),
    Fp(CCRegClass, _FpIdx),
    Zero(CCRegClass, _ZeroIdx);
 
const char * const RegName[NumRegs] = {
    "nz",
    "c",
    "v",
    "ge",
    "fp",
    "zero"
};
 
} // namespace cc_reg
 
enum ConditionCode
{
    COND_EQ  =   0,
    COND_NE, //  1
    COND_CS, //  2
    COND_CC, //  3
    COND_MI, //  4
    COND_PL, //  5
    COND_VS, //  6
    COND_VC, //  7
    COND_HI, //  8
    COND_LS, //  9
    COND_GE, // 10
    COND_LT, // 11
    COND_GT, // 12
    COND_LE, // 13
    COND_AL, // 14
    COND_UC  // 15
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif // __ARCH_ARM_REGS_CC_HH__