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misc.cc
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1 /*
2  * Copyright (c) 2010-2013, 2015-2022 Arm Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
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8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
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36  */
37 
38 #include "arch/arm/regs/misc.hh"
39 
40 #include <tuple>
41 
42 #include "arch/arm/isa.hh"
43 #include "base/logging.hh"
44 #include "cpu/thread_context.hh"
45 #include "sim/full_system.hh"
46 
47 namespace gem5
48 {
49 
50 namespace ArmISA
51 {
52 
53 namespace
54 {
55 
56 std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
57  // MCR/MRC regs
58  { MiscRegNum32(14, 0, 0, 0, 0), MISCREG_DBGDIDR },
59  { MiscRegNum32(14, 0, 0, 0, 2), MISCREG_DBGDTRRXext },
60  { MiscRegNum32(14, 0, 0, 0, 4), MISCREG_DBGBVR0 },
61  { MiscRegNum32(14, 0, 0, 0, 5), MISCREG_DBGBCR0 },
62  { MiscRegNum32(14, 0, 0, 0, 6), MISCREG_DBGWVR0 },
63  { MiscRegNum32(14, 0, 0, 0, 7), MISCREG_DBGWCR0 },
64  { MiscRegNum32(14, 0, 0, 1, 0), MISCREG_DBGDSCRint },
65  { MiscRegNum32(14, 0, 0, 1, 4), MISCREG_DBGBVR1 },
66  { MiscRegNum32(14, 0, 0, 1, 5), MISCREG_DBGBCR1 },
67  { MiscRegNum32(14, 0, 0, 1, 6), MISCREG_DBGWVR1 },
68  { MiscRegNum32(14, 0, 0, 1, 7), MISCREG_DBGWCR1 },
69  { MiscRegNum32(14, 0, 0, 2, 2), MISCREG_DBGDSCRext },
70  { MiscRegNum32(14, 0, 0, 2, 4), MISCREG_DBGBVR2 },
71  { MiscRegNum32(14, 0, 0, 2, 5), MISCREG_DBGBCR2 },
72  { MiscRegNum32(14, 0, 0, 2, 6), MISCREG_DBGWVR2 },
73  { MiscRegNum32(14, 0, 0, 2, 7), MISCREG_DBGWCR2 },
74  { MiscRegNum32(14, 0, 0, 3, 2), MISCREG_DBGDTRTXext },
75  { MiscRegNum32(14, 0, 0, 3, 4), MISCREG_DBGBVR3 },
76  { MiscRegNum32(14, 0, 0, 3, 5), MISCREG_DBGBCR3 },
77  { MiscRegNum32(14, 0, 0, 3, 6), MISCREG_DBGWVR3 },
78  { MiscRegNum32(14, 0, 0, 3, 7), MISCREG_DBGWCR3 },
79  { MiscRegNum32(14, 0, 0, 4, 4), MISCREG_DBGBVR4 },
80  { MiscRegNum32(14, 0, 0, 4, 5), MISCREG_DBGBCR4 },
81  { MiscRegNum32(14, 0, 0, 4, 6), MISCREG_DBGWVR4 },
82  { MiscRegNum32(14, 0, 0, 4, 7), MISCREG_DBGWCR4 },
83  { MiscRegNum32(14, 0, 0, 5, 4), MISCREG_DBGBVR5 },
84  { MiscRegNum32(14, 0, 0, 5, 5), MISCREG_DBGBCR5 },
85  { MiscRegNum32(14, 0, 0, 5, 6), MISCREG_DBGWVR5 },
86  { MiscRegNum32(14, 0, 0, 5, 7), MISCREG_DBGWCR5 },
87  { MiscRegNum32(14, 0, 0, 6, 2), MISCREG_DBGOSECCR },
88  { MiscRegNum32(14, 0, 0, 6, 4), MISCREG_DBGBVR6 },
89  { MiscRegNum32(14, 0, 0, 6, 5), MISCREG_DBGBCR6 },
90  { MiscRegNum32(14, 0, 0, 6, 6), MISCREG_DBGWVR6 },
91  { MiscRegNum32(14, 0, 0, 6, 7), MISCREG_DBGWCR6 },
92  { MiscRegNum32(14, 0, 0, 7, 0), MISCREG_DBGVCR },
93  { MiscRegNum32(14, 0, 0, 7, 4), MISCREG_DBGBVR7 },
94  { MiscRegNum32(14, 0, 0, 7, 5), MISCREG_DBGBCR7 },
95  { MiscRegNum32(14, 0, 0, 7, 6), MISCREG_DBGWVR7 },
96  { MiscRegNum32(14, 0, 0, 7, 7), MISCREG_DBGWCR7 },
97  { MiscRegNum32(14, 0, 0, 8, 4), MISCREG_DBGBVR8 },
98  { MiscRegNum32(14, 0, 0, 8, 5), MISCREG_DBGBCR8 },
99  { MiscRegNum32(14, 0, 0, 8, 6), MISCREG_DBGWVR8 },
100  { MiscRegNum32(14, 0, 0, 8, 7), MISCREG_DBGWCR8 },
101  { MiscRegNum32(14, 0, 0, 9, 4), MISCREG_DBGBVR9 },
102  { MiscRegNum32(14, 0, 0, 9, 5), MISCREG_DBGBCR9 },
103  { MiscRegNum32(14, 0, 0, 9, 6), MISCREG_DBGWVR9 },
104  { MiscRegNum32(14, 0, 0, 9, 7), MISCREG_DBGWCR9 },
105  { MiscRegNum32(14, 0, 0, 10, 4), MISCREG_DBGBVR10 },
106  { MiscRegNum32(14, 0, 0, 10, 5), MISCREG_DBGBCR10 },
107  { MiscRegNum32(14, 0, 0, 10, 6), MISCREG_DBGWVR10 },
108  { MiscRegNum32(14, 0, 0, 10, 7), MISCREG_DBGWCR10 },
109  { MiscRegNum32(14, 0, 0, 11, 4), MISCREG_DBGBVR11 },
110  { MiscRegNum32(14, 0, 0, 11, 5), MISCREG_DBGBCR11 },
111  { MiscRegNum32(14, 0, 0, 11, 6), MISCREG_DBGWVR11 },
112  { MiscRegNum32(14, 0, 0, 11, 7), MISCREG_DBGWCR11 },
113  { MiscRegNum32(14, 0, 0, 12, 4), MISCREG_DBGBVR12 },
114  { MiscRegNum32(14, 0, 0, 12, 5), MISCREG_DBGBCR12 },
115  { MiscRegNum32(14, 0, 0, 12, 6), MISCREG_DBGWVR12 },
116  { MiscRegNum32(14, 0, 0, 12, 7), MISCREG_DBGWCR12 },
117  { MiscRegNum32(14, 0, 0, 13, 4), MISCREG_DBGBVR13 },
118  { MiscRegNum32(14, 0, 0, 13, 5), MISCREG_DBGBCR13 },
119  { MiscRegNum32(14, 0, 0, 13, 6), MISCREG_DBGWVR13 },
120  { MiscRegNum32(14, 0, 0, 13, 7), MISCREG_DBGWCR13 },
121  { MiscRegNum32(14, 0, 0, 14, 4), MISCREG_DBGBVR14 },
122  { MiscRegNum32(14, 0, 0, 14, 5), MISCREG_DBGBCR14 },
123  { MiscRegNum32(14, 0, 0, 14, 6), MISCREG_DBGWVR14 },
124  { MiscRegNum32(14, 0, 0, 14, 7), MISCREG_DBGWCR14 },
125  { MiscRegNum32(14, 0, 0, 15, 4), MISCREG_DBGBVR15 },
126  { MiscRegNum32(14, 0, 0, 15, 5), MISCREG_DBGBCR15 },
127  { MiscRegNum32(14, 0, 0, 15, 6), MISCREG_DBGWVR15 },
128  { MiscRegNum32(14, 0, 0, 15, 7), MISCREG_DBGWCR15 },
129  { MiscRegNum32(14, 0, 1, 0, 1), MISCREG_DBGBXVR0 },
130  { MiscRegNum32(14, 0, 1, 0, 4), MISCREG_DBGOSLAR },
131  { MiscRegNum32(14, 0, 1, 1, 1), MISCREG_DBGBXVR1 },
132  { MiscRegNum32(14, 0, 1, 1, 4), MISCREG_DBGOSLSR },
133  { MiscRegNum32(14, 0, 1, 2, 1), MISCREG_DBGBXVR2 },
134  { MiscRegNum32(14, 0, 1, 3, 1), MISCREG_DBGBXVR3 },
135  { MiscRegNum32(14, 0, 1, 3, 4), MISCREG_DBGOSDLR },
136  { MiscRegNum32(14, 0, 1, 4, 1), MISCREG_DBGBXVR4 },
137  { MiscRegNum32(14, 0, 1, 4, 4), MISCREG_DBGPRCR },
138  { MiscRegNum32(14, 0, 1, 5, 1), MISCREG_DBGBXVR5 },
139  { MiscRegNum32(14, 0, 1, 6, 1), MISCREG_DBGBXVR6 },
140  { MiscRegNum32(14, 0, 1, 7, 1), MISCREG_DBGBXVR7 },
141  { MiscRegNum32(14, 0, 1, 8, 1), MISCREG_DBGBXVR8 },
142  { MiscRegNum32(14, 0, 1, 9, 1), MISCREG_DBGBXVR9 },
143  { MiscRegNum32(14, 0, 1, 10, 1), MISCREG_DBGBXVR10 },
144  { MiscRegNum32(14, 0, 1, 11, 1), MISCREG_DBGBXVR11 },
145  { MiscRegNum32(14, 0, 1, 12, 1), MISCREG_DBGBXVR12 },
146  { MiscRegNum32(14, 0, 1, 13, 1), MISCREG_DBGBXVR13 },
147  { MiscRegNum32(14, 0, 1, 14, 1), MISCREG_DBGBXVR14 },
148  { MiscRegNum32(14, 0, 1, 15, 1), MISCREG_DBGBXVR15 },
149  { MiscRegNum32(14, 6, 1, 0, 0), MISCREG_TEEHBR },
150  { MiscRegNum32(14, 7, 0, 0, 0), MISCREG_JIDR },
151  { MiscRegNum32(14, 7, 1, 0, 0), MISCREG_JOSCR },
152  { MiscRegNum32(14, 7, 2, 0, 0), MISCREG_JMCR },
153  { MiscRegNum32(15, 0, 0, 0, 0), MISCREG_MIDR },
154  { MiscRegNum32(15, 0, 0, 0, 1), MISCREG_CTR },
155  { MiscRegNum32(15, 0, 0, 0, 2), MISCREG_TCMTR },
156  { MiscRegNum32(15, 0, 0, 0, 3), MISCREG_TLBTR },
157  { MiscRegNum32(15, 0, 0, 0, 4), MISCREG_MIDR },
158  { MiscRegNum32(15, 0, 0, 0, 5), MISCREG_MPIDR },
159  { MiscRegNum32(15, 0, 0, 0, 6), MISCREG_REVIDR },
160  { MiscRegNum32(15, 0, 0, 0, 7), MISCREG_MIDR },
161  { MiscRegNum32(15, 0, 0, 1, 0), MISCREG_ID_PFR0 },
162  { MiscRegNum32(15, 0, 0, 1, 1), MISCREG_ID_PFR1 },
163  { MiscRegNum32(15, 0, 0, 1, 2), MISCREG_ID_DFR0 },
164  { MiscRegNum32(15, 0, 0, 1, 3), MISCREG_ID_AFR0 },
165  { MiscRegNum32(15, 0, 0, 1, 4), MISCREG_ID_MMFR0 },
166  { MiscRegNum32(15, 0, 0, 1, 5), MISCREG_ID_MMFR1 },
167  { MiscRegNum32(15, 0, 0, 1, 6), MISCREG_ID_MMFR2 },
168  { MiscRegNum32(15, 0, 0, 1, 7), MISCREG_ID_MMFR3 },
169  { MiscRegNum32(15, 0, 0, 2, 0), MISCREG_ID_ISAR0 },
170  { MiscRegNum32(15, 0, 0, 2, 1), MISCREG_ID_ISAR1 },
171  { MiscRegNum32(15, 0, 0, 2, 2), MISCREG_ID_ISAR2 },
172  { MiscRegNum32(15, 0, 0, 2, 3), MISCREG_ID_ISAR3 },
173  { MiscRegNum32(15, 0, 0, 2, 4), MISCREG_ID_ISAR4 },
174  { MiscRegNum32(15, 0, 0, 2, 5), MISCREG_ID_ISAR5 },
175  { MiscRegNum32(15, 0, 0, 2, 6), MISCREG_ID_MMFR4 },
176  { MiscRegNum32(15, 0, 0, 2, 7), MISCREG_ID_ISAR6 },
177  { MiscRegNum32(15, 0, 0, 3, 0), MISCREG_RAZ },
178  { MiscRegNum32(15, 0, 0, 3, 1), MISCREG_RAZ },
179  { MiscRegNum32(15, 0, 0, 3, 2), MISCREG_RAZ },
180  { MiscRegNum32(15, 0, 0, 3, 3), MISCREG_RAZ },
181  { MiscRegNum32(15, 0, 0, 3, 4), MISCREG_RAZ },
182  { MiscRegNum32(15, 0, 0, 3, 5), MISCREG_RAZ },
183  { MiscRegNum32(15, 0, 0, 3, 6), MISCREG_RAZ },
184  { MiscRegNum32(15, 0, 0, 3, 7), MISCREG_RAZ },
185  { MiscRegNum32(15, 0, 0, 4, 0), MISCREG_RAZ },
186  { MiscRegNum32(15, 0, 0, 4, 1), MISCREG_RAZ },
187  { MiscRegNum32(15, 0, 0, 4, 2), MISCREG_RAZ },
188  { MiscRegNum32(15, 0, 0, 4, 3), MISCREG_RAZ },
189  { MiscRegNum32(15, 0, 0, 4, 4), MISCREG_RAZ },
190  { MiscRegNum32(15, 0, 0, 4, 5), MISCREG_RAZ },
191  { MiscRegNum32(15, 0, 0, 4, 6), MISCREG_RAZ },
192  { MiscRegNum32(15, 0, 0, 4, 7), MISCREG_RAZ },
193  { MiscRegNum32(15, 0, 0, 5, 0), MISCREG_RAZ },
194  { MiscRegNum32(15, 0, 0, 5, 1), MISCREG_RAZ },
195  { MiscRegNum32(15, 0, 0, 5, 2), MISCREG_RAZ },
196  { MiscRegNum32(15, 0, 0, 5, 3), MISCREG_RAZ },
197  { MiscRegNum32(15, 0, 0, 5, 4), MISCREG_RAZ },
198  { MiscRegNum32(15, 0, 0, 5, 5), MISCREG_RAZ },
199  { MiscRegNum32(15, 0, 0, 5, 6), MISCREG_RAZ },
200  { MiscRegNum32(15, 0, 0, 5, 7), MISCREG_RAZ },
201  { MiscRegNum32(15, 0, 0, 6, 0), MISCREG_RAZ },
202  { MiscRegNum32(15, 0, 0, 6, 1), MISCREG_RAZ },
203  { MiscRegNum32(15, 0, 0, 6, 2), MISCREG_RAZ },
204  { MiscRegNum32(15, 0, 0, 6, 3), MISCREG_RAZ },
205  { MiscRegNum32(15, 0, 0, 6, 4), MISCREG_RAZ },
206  { MiscRegNum32(15, 0, 0, 6, 5), MISCREG_RAZ },
207  { MiscRegNum32(15, 0, 0, 6, 6), MISCREG_RAZ },
208  { MiscRegNum32(15, 0, 0, 6, 7), MISCREG_RAZ },
209  { MiscRegNum32(15, 0, 0, 7, 0), MISCREG_RAZ },
210  { MiscRegNum32(15, 0, 0, 7, 1), MISCREG_RAZ },
211  { MiscRegNum32(15, 0, 0, 7, 2), MISCREG_RAZ },
212  { MiscRegNum32(15, 0, 0, 7, 3), MISCREG_RAZ },
213  { MiscRegNum32(15, 0, 0, 7, 4), MISCREG_RAZ },
214  { MiscRegNum32(15, 0, 0, 7, 5), MISCREG_RAZ },
215  { MiscRegNum32(15, 0, 0, 7, 6), MISCREG_RAZ },
216  { MiscRegNum32(15, 0, 0, 7, 7), MISCREG_RAZ },
217  { MiscRegNum32(15, 0, 0, 8, 0), MISCREG_RAZ },
218  { MiscRegNum32(15, 0, 0, 8, 1), MISCREG_RAZ },
219  { MiscRegNum32(15, 0, 0, 8, 2), MISCREG_RAZ },
220  { MiscRegNum32(15, 0, 0, 8, 3), MISCREG_RAZ },
221  { MiscRegNum32(15, 0, 0, 8, 4), MISCREG_RAZ },
222  { MiscRegNum32(15, 0, 0, 8, 5), MISCREG_RAZ },
223  { MiscRegNum32(15, 0, 0, 8, 6), MISCREG_RAZ },
224  { MiscRegNum32(15, 0, 0, 8, 7), MISCREG_RAZ },
225  { MiscRegNum32(15, 0, 0, 9, 0), MISCREG_RAZ },
226  { MiscRegNum32(15, 0, 0, 9, 1), MISCREG_RAZ },
227  { MiscRegNum32(15, 0, 0, 9, 2), MISCREG_RAZ },
228  { MiscRegNum32(15, 0, 0, 9, 3), MISCREG_RAZ },
229  { MiscRegNum32(15, 0, 0, 9, 4), MISCREG_RAZ },
230  { MiscRegNum32(15, 0, 0, 9, 5), MISCREG_RAZ },
231  { MiscRegNum32(15, 0, 0, 9, 6), MISCREG_RAZ },
232  { MiscRegNum32(15, 0, 0, 9, 7), MISCREG_RAZ },
233  { MiscRegNum32(15, 0, 0, 10, 0), MISCREG_RAZ },
234  { MiscRegNum32(15, 0, 0, 10, 1), MISCREG_RAZ },
235  { MiscRegNum32(15, 0, 0, 10, 2), MISCREG_RAZ },
236  { MiscRegNum32(15, 0, 0, 10, 3), MISCREG_RAZ },
237  { MiscRegNum32(15, 0, 0, 10, 4), MISCREG_RAZ },
238  { MiscRegNum32(15, 0, 0, 10, 5), MISCREG_RAZ },
239  { MiscRegNum32(15, 0, 0, 10, 6), MISCREG_RAZ },
240  { MiscRegNum32(15, 0, 0, 10, 7), MISCREG_RAZ },
241  { MiscRegNum32(15, 0, 0, 11, 0), MISCREG_RAZ },
242  { MiscRegNum32(15, 0, 0, 11, 1), MISCREG_RAZ },
243  { MiscRegNum32(15, 0, 0, 11, 2), MISCREG_RAZ },
244  { MiscRegNum32(15, 0, 0, 11, 3), MISCREG_RAZ },
245  { MiscRegNum32(15, 0, 0, 11, 4), MISCREG_RAZ },
246  { MiscRegNum32(15, 0, 0, 11, 5), MISCREG_RAZ },
247  { MiscRegNum32(15, 0, 0, 11, 6), MISCREG_RAZ },
248  { MiscRegNum32(15, 0, 0, 11, 7), MISCREG_RAZ },
249  { MiscRegNum32(15, 0, 0, 12, 0), MISCREG_RAZ },
250  { MiscRegNum32(15, 0, 0, 12, 1), MISCREG_RAZ },
251  { MiscRegNum32(15, 0, 0, 12, 2), MISCREG_RAZ },
252  { MiscRegNum32(15, 0, 0, 12, 3), MISCREG_RAZ },
253  { MiscRegNum32(15, 0, 0, 12, 4), MISCREG_RAZ },
254  { MiscRegNum32(15, 0, 0, 12, 5), MISCREG_RAZ },
255  { MiscRegNum32(15, 0, 0, 12, 6), MISCREG_RAZ },
256  { MiscRegNum32(15, 0, 0, 12, 7), MISCREG_RAZ },
257  { MiscRegNum32(15, 0, 0, 13, 0), MISCREG_RAZ },
258  { MiscRegNum32(15, 0, 0, 13, 1), MISCREG_RAZ },
259  { MiscRegNum32(15, 0, 0, 13, 2), MISCREG_RAZ },
260  { MiscRegNum32(15, 0, 0, 13, 3), MISCREG_RAZ },
261  { MiscRegNum32(15, 0, 0, 13, 4), MISCREG_RAZ },
262  { MiscRegNum32(15, 0, 0, 13, 5), MISCREG_RAZ },
263  { MiscRegNum32(15, 0, 0, 13, 6), MISCREG_RAZ },
264  { MiscRegNum32(15, 0, 0, 13, 7), MISCREG_RAZ },
265  { MiscRegNum32(15, 0, 0, 14, 0), MISCREG_RAZ },
266  { MiscRegNum32(15, 0, 0, 14, 1), MISCREG_RAZ },
267  { MiscRegNum32(15, 0, 0, 14, 2), MISCREG_RAZ },
268  { MiscRegNum32(15, 0, 0, 14, 3), MISCREG_RAZ },
269  { MiscRegNum32(15, 0, 0, 14, 4), MISCREG_RAZ },
270  { MiscRegNum32(15, 0, 0, 14, 5), MISCREG_RAZ },
271  { MiscRegNum32(15, 0, 0, 14, 6), MISCREG_RAZ },
272  { MiscRegNum32(15, 0, 0, 14, 7), MISCREG_RAZ },
273  { MiscRegNum32(15, 0, 0, 15, 0), MISCREG_RAZ },
274  { MiscRegNum32(15, 0, 0, 15, 1), MISCREG_RAZ },
275  { MiscRegNum32(15, 0, 0, 15, 2), MISCREG_RAZ },
276  { MiscRegNum32(15, 0, 0, 15, 3), MISCREG_RAZ },
277  { MiscRegNum32(15, 0, 0, 15, 4), MISCREG_RAZ },
278  { MiscRegNum32(15, 0, 0, 15, 5), MISCREG_RAZ },
279  { MiscRegNum32(15, 0, 0, 15, 6), MISCREG_RAZ },
280  { MiscRegNum32(15, 0, 0, 15, 7), MISCREG_RAZ },
281  { MiscRegNum32(15, 0, 1, 0, 0), MISCREG_SCTLR },
282  { MiscRegNum32(15, 0, 1, 0, 1), MISCREG_ACTLR },
283  { MiscRegNum32(15, 0, 1, 0, 2), MISCREG_CPACR },
284  { MiscRegNum32(15, 0, 1, 1, 0), MISCREG_SCR },
285  { MiscRegNum32(15, 0, 1, 1, 1), MISCREG_SDER },
286  { MiscRegNum32(15, 0, 1, 1, 2), MISCREG_NSACR },
287  { MiscRegNum32(15, 0, 1, 3, 1), MISCREG_SDCR },
288  { MiscRegNum32(15, 0, 2, 0, 0), MISCREG_TTBR0 },
289  { MiscRegNum32(15, 0, 2, 0, 1), MISCREG_TTBR1 },
290  { MiscRegNum32(15, 0, 2, 0, 2), MISCREG_TTBCR },
291  { MiscRegNum32(15, 0, 3, 0, 0), MISCREG_DACR },
292  { MiscRegNum32(15, 0, 4, 6, 0), MISCREG_ICC_PMR },
293  { MiscRegNum32(15, 0, 5, 0, 0), MISCREG_DFSR },
294  { MiscRegNum32(15, 0, 5, 0, 1), MISCREG_IFSR },
295  { MiscRegNum32(15, 0, 5, 1, 0), MISCREG_ADFSR },
296  { MiscRegNum32(15, 0, 5, 1, 1), MISCREG_AIFSR },
297  { MiscRegNum32(15, 0, 6, 0, 0), MISCREG_DFAR },
298  { MiscRegNum32(15, 0, 6, 0, 2), MISCREG_IFAR },
299  { MiscRegNum32(15, 0, 7, 0, 4), MISCREG_NOP },
300  { MiscRegNum32(15, 0, 7, 1, 0), MISCREG_ICIALLUIS },
301  { MiscRegNum32(15, 0, 7, 1, 6), MISCREG_BPIALLIS },
302  { MiscRegNum32(15, 0, 7, 2, 7), MISCREG_DBGDEVID0 },
303  { MiscRegNum32(15, 0, 7, 4, 0), MISCREG_PAR },
304  { MiscRegNum32(15, 0, 7, 5, 0), MISCREG_ICIALLU },
305  { MiscRegNum32(15, 0, 7, 5, 1), MISCREG_ICIMVAU },
306  { MiscRegNum32(15, 0, 7, 5, 4), MISCREG_CP15ISB },
307  { MiscRegNum32(15, 0, 7, 5, 6), MISCREG_BPIALL },
308  { MiscRegNum32(15, 0, 7, 5, 7), MISCREG_BPIMVA },
309  { MiscRegNum32(15, 0, 7, 6, 1), MISCREG_DCIMVAC },
310  { MiscRegNum32(15, 0, 7, 6, 2), MISCREG_DCISW },
311  { MiscRegNum32(15, 0, 7, 8, 0), MISCREG_ATS1CPR },
312  { MiscRegNum32(15, 0, 7, 8, 1), MISCREG_ATS1CPW },
313  { MiscRegNum32(15, 0, 7, 8, 2), MISCREG_ATS1CUR },
314  { MiscRegNum32(15, 0, 7, 8, 3), MISCREG_ATS1CUW },
315  { MiscRegNum32(15, 0, 7, 8, 4), MISCREG_ATS12NSOPR },
316  { MiscRegNum32(15, 0, 7, 8, 5), MISCREG_ATS12NSOPW },
317  { MiscRegNum32(15, 0, 7, 8, 6), MISCREG_ATS12NSOUR },
318  { MiscRegNum32(15, 0, 7, 8, 7), MISCREG_ATS12NSOUW },
319  { MiscRegNum32(15, 0, 7, 10, 1), MISCREG_DCCMVAC },
320  { MiscRegNum32(15, 0, 7, 10, 2), MISCREG_DCCSW },
321  { MiscRegNum32(15, 0, 7, 10, 4), MISCREG_CP15DSB },
322  { MiscRegNum32(15, 0, 7, 10, 5), MISCREG_CP15DMB },
323  { MiscRegNum32(15, 0, 7, 11, 1), MISCREG_DCCMVAU },
324  { MiscRegNum32(15, 0, 7, 13, 1), MISCREG_NOP },
325  { MiscRegNum32(15, 0, 7, 14, 1), MISCREG_DCCIMVAC },
326  { MiscRegNum32(15, 0, 7, 14, 2), MISCREG_DCCISW },
327  { MiscRegNum32(15, 0, 8, 3, 0), MISCREG_TLBIALLIS },
328  { MiscRegNum32(15, 0, 8, 3, 1), MISCREG_TLBIMVAIS },
329  { MiscRegNum32(15, 0, 8, 3, 2), MISCREG_TLBIASIDIS },
330  { MiscRegNum32(15, 0, 8, 3, 3), MISCREG_TLBIMVAAIS },
331  { MiscRegNum32(15, 0, 8, 3, 5), MISCREG_TLBIMVALIS },
332  { MiscRegNum32(15, 0, 8, 3, 7), MISCREG_TLBIMVAALIS },
333  { MiscRegNum32(15, 0, 8, 5, 0), MISCREG_ITLBIALL },
334  { MiscRegNum32(15, 0, 8, 5, 1), MISCREG_ITLBIMVA },
335  { MiscRegNum32(15, 0, 8, 5, 2), MISCREG_ITLBIASID },
336  { MiscRegNum32(15, 0, 8, 6, 0), MISCREG_DTLBIALL },
337  { MiscRegNum32(15, 0, 8, 6, 1), MISCREG_DTLBIMVA },
338  { MiscRegNum32(15, 0, 8, 6, 2), MISCREG_DTLBIASID },
339  { MiscRegNum32(15, 0, 8, 7, 0), MISCREG_TLBIALL },
340  { MiscRegNum32(15, 0, 8, 7, 1), MISCREG_TLBIMVA },
341  { MiscRegNum32(15, 0, 8, 7, 2), MISCREG_TLBIASID },
342  { MiscRegNum32(15, 0, 8, 7, 3), MISCREG_TLBIMVAA },
343  { MiscRegNum32(15, 0, 8, 7, 5), MISCREG_TLBIMVAL },
344  { MiscRegNum32(15, 0, 8, 7, 7), MISCREG_TLBIMVAAL },
345  { MiscRegNum32(15, 0, 9, 12, 0), MISCREG_PMCR },
346  { MiscRegNum32(15, 0, 9, 12, 1), MISCREG_PMCNTENSET },
347  { MiscRegNum32(15, 0, 9, 12, 2), MISCREG_PMCNTENCLR },
348  { MiscRegNum32(15, 0, 9, 12, 3), MISCREG_PMOVSR },
349  { MiscRegNum32(15, 0, 9, 12, 4), MISCREG_PMSWINC },
350  { MiscRegNum32(15, 0, 9, 12, 5), MISCREG_PMSELR },
351  { MiscRegNum32(15, 0, 9, 12, 6), MISCREG_PMCEID0 },
352  { MiscRegNum32(15, 0, 9, 12, 7), MISCREG_PMCEID1 },
353  { MiscRegNum32(15, 0, 9, 13, 0), MISCREG_PMCCNTR },
354  { MiscRegNum32(15, 0, 9, 13, 1), MISCREG_PMXEVTYPER_PMCCFILTR },
355  { MiscRegNum32(15, 0, 9, 13, 2), MISCREG_PMXEVCNTR },
356  { MiscRegNum32(15, 0, 9, 14, 0), MISCREG_PMUSERENR },
357  { MiscRegNum32(15, 0, 9, 14, 1), MISCREG_PMINTENSET },
358  { MiscRegNum32(15, 0, 9, 14, 2), MISCREG_PMINTENCLR },
359  { MiscRegNum32(15, 0, 9, 14, 3), MISCREG_PMOVSSET },
360  { MiscRegNum32(15, 0, 10, 2, 0), MISCREG_PRRR_MAIR0 },
361  { MiscRegNum32(15, 0, 10, 2, 1), MISCREG_NMRR_MAIR1 },
362  { MiscRegNum32(15, 0, 10, 3, 0), MISCREG_AMAIR0 },
363  { MiscRegNum32(15, 0, 10, 3, 1), MISCREG_AMAIR1 },
364  { MiscRegNum32(15, 0, 12, 0, 0), MISCREG_VBAR },
365  { MiscRegNum32(15, 0, 12, 0, 1), MISCREG_MVBAR },
366  { MiscRegNum32(15, 0, 12, 1, 0), MISCREG_ISR },
367  { MiscRegNum32(15, 0, 12, 8, 0), MISCREG_ICC_IAR0 },
368  { MiscRegNum32(15, 0, 12, 8, 1), MISCREG_ICC_EOIR0 },
369  { MiscRegNum32(15, 0, 12, 8, 2), MISCREG_ICC_HPPIR0 },
370  { MiscRegNum32(15, 0, 12, 8, 3), MISCREG_ICC_BPR0 },
371  { MiscRegNum32(15, 0, 12, 8, 4), MISCREG_ICC_AP0R0 },
372  { MiscRegNum32(15, 0, 12, 8, 5), MISCREG_ICC_AP0R1 },
373  { MiscRegNum32(15, 0, 12, 8, 6), MISCREG_ICC_AP0R2 },
374  { MiscRegNum32(15, 0, 12, 8, 7), MISCREG_ICC_AP0R3 },
375  { MiscRegNum32(15, 0, 12, 9, 0), MISCREG_ICC_AP1R0 },
376  { MiscRegNum32(15, 0, 12, 9, 1), MISCREG_ICC_AP1R1 },
377  { MiscRegNum32(15, 0, 12, 9, 2), MISCREG_ICC_AP1R2 },
378  { MiscRegNum32(15, 0, 12, 9, 3), MISCREG_ICC_AP1R3 },
379  { MiscRegNum32(15, 0, 12, 11, 1), MISCREG_ICC_DIR },
380  { MiscRegNum32(15, 0, 12, 11, 3), MISCREG_ICC_RPR },
381  { MiscRegNum32(15, 0, 12, 12, 0), MISCREG_ICC_IAR1 },
382  { MiscRegNum32(15, 0, 12, 12, 1), MISCREG_ICC_EOIR1 },
383  { MiscRegNum32(15, 0, 12, 12, 2), MISCREG_ICC_HPPIR1 },
384  { MiscRegNum32(15, 0, 12, 12, 3), MISCREG_ICC_BPR1 },
385  { MiscRegNum32(15, 0, 12, 12, 4), MISCREG_ICC_CTLR },
386  { MiscRegNum32(15, 0, 12, 12, 5), MISCREG_ICC_SRE },
387  { MiscRegNum32(15, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0 },
388  { MiscRegNum32(15, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1 },
389  { MiscRegNum32(15, 0, 13, 0, 0), MISCREG_FCSEIDR },
390  { MiscRegNum32(15, 0, 13, 0, 1), MISCREG_CONTEXTIDR },
391  { MiscRegNum32(15, 0, 13, 0, 2), MISCREG_TPIDRURW },
392  { MiscRegNum32(15, 0, 13, 0, 3), MISCREG_TPIDRURO },
393  { MiscRegNum32(15, 0, 13, 0, 4), MISCREG_TPIDRPRW },
394  { MiscRegNum32(15, 0, 14, 0, 0), MISCREG_CNTFRQ },
395  { MiscRegNum32(15, 0, 14, 1, 0), MISCREG_CNTKCTL },
396  { MiscRegNum32(15, 0, 14, 2, 0), MISCREG_CNTP_TVAL },
397  { MiscRegNum32(15, 0, 14, 2, 1), MISCREG_CNTP_CTL },
398  { MiscRegNum32(15, 0, 14, 3, 0), MISCREG_CNTV_TVAL },
399  { MiscRegNum32(15, 0, 14, 3, 1), MISCREG_CNTV_CTL },
400  { MiscRegNum32(15, 1, 0, 0, 0), MISCREG_CCSIDR },
401  { MiscRegNum32(15, 1, 0, 0, 1), MISCREG_CLIDR },
402  { MiscRegNum32(15, 1, 0, 0, 7), MISCREG_AIDR },
403  { MiscRegNum32(15, 2, 0, 0, 0), MISCREG_CSSELR },
404  { MiscRegNum32(15, 4, 0, 0, 0), MISCREG_VPIDR },
405  { MiscRegNum32(15, 4, 0, 0, 5), MISCREG_VMPIDR },
406  { MiscRegNum32(15, 4, 1, 0, 0), MISCREG_HSCTLR },
407  { MiscRegNum32(15, 4, 1, 0, 1), MISCREG_HACTLR },
408  { MiscRegNum32(15, 4, 1, 1, 0), MISCREG_HCR },
409  { MiscRegNum32(15, 4, 1, 1, 1), MISCREG_HDCR },
410  { MiscRegNum32(15, 4, 1, 1, 2), MISCREG_HCPTR },
411  { MiscRegNum32(15, 4, 1, 1, 3), MISCREG_HSTR },
412  { MiscRegNum32(15, 4, 1, 1, 4), MISCREG_HCR2 },
413  { MiscRegNum32(15, 4, 1, 1, 7), MISCREG_HACR },
414  { MiscRegNum32(15, 4, 2, 0, 2), MISCREG_HTCR },
415  { MiscRegNum32(15, 4, 2, 1, 2), MISCREG_VTCR },
416  { MiscRegNum32(15, 4, 5, 1, 0), MISCREG_HADFSR },
417  { MiscRegNum32(15, 4, 5, 1, 1), MISCREG_HAIFSR },
418  { MiscRegNum32(15, 4, 5, 2, 0), MISCREG_HSR },
419  { MiscRegNum32(15, 4, 6, 0, 0), MISCREG_HDFAR },
420  { MiscRegNum32(15, 4, 6, 0, 2), MISCREG_HIFAR },
421  { MiscRegNum32(15, 4, 6, 0, 4), MISCREG_HPFAR },
422  { MiscRegNum32(15, 4, 7, 8, 0), MISCREG_ATS1HR },
423  { MiscRegNum32(15, 4, 7, 8, 1), MISCREG_ATS1HW },
424  { MiscRegNum32(15, 4, 8, 0, 1), MISCREG_TLBIIPAS2IS },
425  { MiscRegNum32(15, 4, 8, 0, 5), MISCREG_TLBIIPAS2LIS },
426  { MiscRegNum32(15, 4, 8, 3, 0), MISCREG_TLBIALLHIS },
427  { MiscRegNum32(15, 4, 8, 3, 1), MISCREG_TLBIMVAHIS },
428  { MiscRegNum32(15, 4, 8, 3, 4), MISCREG_TLBIALLNSNHIS },
429  { MiscRegNum32(15, 4, 8, 3, 5), MISCREG_TLBIMVALHIS },
430  { MiscRegNum32(15, 4, 8, 4, 1), MISCREG_TLBIIPAS2 },
431  { MiscRegNum32(15, 4, 8, 4, 5), MISCREG_TLBIIPAS2L },
432  { MiscRegNum32(15, 4, 8, 7, 0), MISCREG_TLBIALLH },
433  { MiscRegNum32(15, 4, 8, 7, 1), MISCREG_TLBIMVAH },
434  { MiscRegNum32(15, 4, 8, 7, 4), MISCREG_TLBIALLNSNH },
435  { MiscRegNum32(15, 4, 8, 7, 5), MISCREG_TLBIMVALH },
436  { MiscRegNum32(15, 4, 10, 2, 0), MISCREG_HMAIR0 },
437  { MiscRegNum32(15, 4, 10, 2, 1), MISCREG_HMAIR1 },
438  { MiscRegNum32(15, 4, 10, 3, 0), MISCREG_HAMAIR0 },
439  { MiscRegNum32(15, 4, 10, 3, 1), MISCREG_HAMAIR1 },
440  { MiscRegNum32(15, 4, 12, 0, 0), MISCREG_HVBAR },
441  { MiscRegNum32(15, 4, 12, 8, 0), MISCREG_ICH_AP0R0 },
442  { MiscRegNum32(15, 4, 12, 8, 1), MISCREG_ICH_AP0R1 },
443  { MiscRegNum32(15, 4, 12, 8, 2), MISCREG_ICH_AP0R2 },
444  { MiscRegNum32(15, 4, 12, 8, 3), MISCREG_ICH_AP0R3 },
445  { MiscRegNum32(15, 4, 12, 9, 0), MISCREG_ICH_AP1R0 },
446  { MiscRegNum32(15, 4, 12, 9, 1), MISCREG_ICH_AP1R1 },
447  { MiscRegNum32(15, 4, 12, 9, 2), MISCREG_ICH_AP1R2 },
448  { MiscRegNum32(15, 4, 12, 9, 3), MISCREG_ICH_AP1R3 },
449  { MiscRegNum32(15, 4, 12, 9, 5), MISCREG_ICC_HSRE },
450  { MiscRegNum32(15, 4, 12, 11, 0), MISCREG_ICH_HCR },
451  { MiscRegNum32(15, 4, 12, 11, 1), MISCREG_ICH_VTR },
452  { MiscRegNum32(15, 4, 12, 11, 2), MISCREG_ICH_MISR },
453  { MiscRegNum32(15, 4, 12, 11, 3), MISCREG_ICH_EISR },
454  { MiscRegNum32(15, 4, 12, 11, 5), MISCREG_ICH_ELRSR },
455  { MiscRegNum32(15, 4, 12, 11, 7), MISCREG_ICH_VMCR },
456  { MiscRegNum32(15, 4, 12, 12, 0), MISCREG_ICH_LR0 },
457  { MiscRegNum32(15, 4, 12, 12, 1), MISCREG_ICH_LR1 },
458  { MiscRegNum32(15, 4, 12, 12, 2), MISCREG_ICH_LR2 },
459  { MiscRegNum32(15, 4, 12, 12, 3), MISCREG_ICH_LR3 },
460  { MiscRegNum32(15, 4, 12, 12, 4), MISCREG_ICH_LR4 },
461  { MiscRegNum32(15, 4, 12, 12, 5), MISCREG_ICH_LR5 },
462  { MiscRegNum32(15, 4, 12, 12, 6), MISCREG_ICH_LR6 },
463  { MiscRegNum32(15, 4, 12, 12, 7), MISCREG_ICH_LR7 },
464  { MiscRegNum32(15, 4, 12, 13, 0), MISCREG_ICH_LR8 },
465  { MiscRegNum32(15, 4, 12, 13, 1), MISCREG_ICH_LR9 },
466  { MiscRegNum32(15, 4, 12, 13, 2), MISCREG_ICH_LR10 },
467  { MiscRegNum32(15, 4, 12, 13, 3), MISCREG_ICH_LR11 },
468  { MiscRegNum32(15, 4, 12, 13, 4), MISCREG_ICH_LR12 },
469  { MiscRegNum32(15, 4, 12, 13, 5), MISCREG_ICH_LR13 },
470  { MiscRegNum32(15, 4, 12, 13, 6), MISCREG_ICH_LR14 },
471  { MiscRegNum32(15, 4, 12, 13, 7), MISCREG_ICH_LR15 },
472  { MiscRegNum32(15, 4, 12, 14, 0), MISCREG_ICH_LRC0 },
473  { MiscRegNum32(15, 4, 12, 14, 1), MISCREG_ICH_LRC1 },
474  { MiscRegNum32(15, 4, 12, 14, 2), MISCREG_ICH_LRC2 },
475  { MiscRegNum32(15, 4, 12, 14, 3), MISCREG_ICH_LRC3 },
476  { MiscRegNum32(15, 4, 12, 14, 4), MISCREG_ICH_LRC4 },
477  { MiscRegNum32(15, 4, 12, 14, 5), MISCREG_ICH_LRC5 },
478  { MiscRegNum32(15, 4, 12, 14, 6), MISCREG_ICH_LRC6 },
479  { MiscRegNum32(15, 4, 12, 14, 7), MISCREG_ICH_LRC7 },
480  { MiscRegNum32(15, 4, 12, 15, 0), MISCREG_ICH_LRC8 },
481  { MiscRegNum32(15, 4, 12, 15, 1), MISCREG_ICH_LRC9 },
482  { MiscRegNum32(15, 4, 12, 15, 2), MISCREG_ICH_LRC10 },
483  { MiscRegNum32(15, 4, 12, 15, 3), MISCREG_ICH_LRC11 },
484  { MiscRegNum32(15, 4, 12, 15, 4), MISCREG_ICH_LRC12 },
485  { MiscRegNum32(15, 4, 12, 15, 5), MISCREG_ICH_LRC13 },
486  { MiscRegNum32(15, 4, 12, 15, 6), MISCREG_ICH_LRC14 },
487  { MiscRegNum32(15, 4, 12, 15, 7), MISCREG_ICH_LRC15 },
488  { MiscRegNum32(15, 4, 13, 0, 2), MISCREG_HTPIDR },
489  { MiscRegNum32(15, 4, 14, 1, 0), MISCREG_CNTHCTL },
490  { MiscRegNum32(15, 4, 14, 2, 0), MISCREG_CNTHP_TVAL },
491  { MiscRegNum32(15, 4, 14, 2, 1), MISCREG_CNTHP_CTL },
492  { MiscRegNum32(15, 6, 12, 12, 4), MISCREG_ICC_MCTLR },
493  { MiscRegNum32(15, 6, 12, 12, 5), MISCREG_ICC_MSRE },
494  { MiscRegNum32(15, 6, 12, 12, 7), MISCREG_ICC_MGRPEN1 },
495  // MCRR/MRRC regs
496  { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 },
497  { MiscRegNum32(15, 0, 7), MISCREG_PAR },
498  { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R },
499  { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT },
500  { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },
501  { MiscRegNum32(15, 1, 2), MISCREG_TTBR1 },
502  { MiscRegNum32(15, 1, 12), MISCREG_ICC_ASGI1R },
503  { MiscRegNum32(15, 1, 14), MISCREG_CNTVCT },
504  { MiscRegNum32(15, 1, 15), MISCREG_L2MERRSR },
505  { MiscRegNum32(15, 2, 12), MISCREG_ICC_SGI0R },
506  { MiscRegNum32(15, 2, 14), MISCREG_CNTP_CVAL },
507  { MiscRegNum32(15, 3, 14), MISCREG_CNTV_CVAL },
508  { MiscRegNum32(15, 4, 2), MISCREG_HTTBR },
509  { MiscRegNum32(15, 4, 14), MISCREG_CNTVOFF },
510  { MiscRegNum32(15, 6, 2), MISCREG_VTTBR },
511  { MiscRegNum32(15, 6, 14), MISCREG_CNTHP_CVAL },
512 };
513 
514 }
515 
516 MiscRegIndex
517 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
518 {
519  MiscRegNum32 cop_reg(14, opc1, crn, crm, opc2);
520  auto it = miscRegNum32ToIdx.find(cop_reg);
521  if (it != miscRegNum32ToIdx.end()) {
522  return it->second;
523  } else {
524  warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
525  crn, opc1, crm, opc2);
526  return MISCREG_UNKNOWN;
527  }
528 }
529 
530 MiscRegIndex
531 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
532 {
533  MiscRegNum32 cop_reg(15, opc1, crn, crm, opc2);
534  auto it = miscRegNum32ToIdx.find(cop_reg);
535  if (it != miscRegNum32ToIdx.end()) {
536  return it->second;
537  } else {
538  if ((crn == 15) ||
539  (crn == 9 && (crm <= 2 || crm >= 5)) ||
540  (crn == 10 && opc1 == 0 && crm <= 1) ||
541  (crn == 11 && opc1 <= 7 && (crm <= 8 || crm ==15))) {
542  return MISCREG_IMPDEF_UNIMPL;
543  } else {
544  return MISCREG_UNKNOWN;
545  }
546  }
547 }
548 
549 MiscRegIndex
550 decodeCP15Reg64(unsigned crm, unsigned opc1)
551 {
552  MiscRegNum32 cop_reg(15, opc1, crm);
553  auto it = miscRegNum32ToIdx.find(cop_reg);
554  if (it != miscRegNum32ToIdx.end()) {
555  return it->second;
556  } else {
557  return MISCREG_UNKNOWN;
558  }
559 }
560 
561 std::tuple<bool, bool>
562 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
563 {
564  bool secure = !scr.ns;
565  bool canRead = false;
566  bool undefined = false;
567 
568  switch (cpsr.mode) {
569  case MODE_USER:
570  canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
571  miscRegInfo[reg][MISCREG_USR_NS_RD];
572  break;
573  case MODE_FIQ:
574  case MODE_IRQ:
575  case MODE_SVC:
576  case MODE_ABORT:
577  case MODE_UNDEFINED:
578  case MODE_SYSTEM:
579  canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
580  miscRegInfo[reg][MISCREG_PRI_NS_RD];
581  break;
582  case MODE_MON:
583  canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
584  miscRegInfo[reg][MISCREG_MON_NS1_RD];
585  break;
586  case MODE_HYP:
587  canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
588  break;
589  default:
590  undefined = true;
591  }
592 
593  switch (reg) {
594  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
595  if (!undefined)
596  undefined = AArch32isUndefinedGenericTimer(reg, tc);
597  break;
598  default:
599  break;
600  }
601 
602  // can't do permissions checkes on the root of a banked pair of regs
603  assert(!miscRegInfo[reg][MISCREG_BANKED]);
604  return std::make_tuple(canRead, undefined);
605 }
606 
607 std::tuple<bool, bool>
608 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
609 {
610  bool secure = !scr.ns;
611  bool canWrite = false;
612  bool undefined = false;
613 
614  switch (cpsr.mode) {
615  case MODE_USER:
616  canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
617  miscRegInfo[reg][MISCREG_USR_NS_WR];
618  break;
619  case MODE_FIQ:
620  case MODE_IRQ:
621  case MODE_SVC:
622  case MODE_ABORT:
623  case MODE_UNDEFINED:
624  case MODE_SYSTEM:
625  canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
626  miscRegInfo[reg][MISCREG_PRI_NS_WR];
627  break;
628  case MODE_MON:
629  canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
630  miscRegInfo[reg][MISCREG_MON_NS1_WR];
631  break;
632  case MODE_HYP:
633  canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
634  break;
635  default:
636  undefined = true;
637  }
638 
639  switch (reg) {
640  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
641  if (!undefined)
642  undefined = AArch32isUndefinedGenericTimer(reg, tc);
643  break;
644  default:
645  break;
646  }
647 
648  // can't do permissions checkes on the root of a banked pair of regs
649  assert(!miscRegInfo[reg][MISCREG_BANKED]);
650  return std::make_tuple(canWrite, undefined);
651 }
652 
653 bool
654 AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
655 {
656  if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
657  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
658  bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
659  if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
660  return true;
661  }
662  return false;
663 }
664 
665 int
666 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
667 {
668  SCR scr = tc->readMiscReg(MISCREG_SCR);
669  return snsBankedIndex(reg, tc, scr.ns);
670 }
671 
672 int
673 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
674 {
675  int reg_as_int = static_cast<int>(reg);
676  if (miscRegInfo[reg][MISCREG_BANKED]) {
677  reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
678  !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
679  }
680  return reg_as_int;
681 }
682 
683 int
684 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
685 {
686  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
687  SCR scr = tc->readMiscReg(MISCREG_SCR);
688  return isa->snsBankedIndex64(reg, scr.ns);
689 }
690 
699 int unflattenResultMiscReg[NUM_MISCREGS];
700 
701 void
702 preUnflattenMiscReg()
703 {
704  int reg = -1;
705  for (int i = 0 ; i < NUM_MISCREGS; i++){
706  if (miscRegInfo[i][MISCREG_BANKED])
707  reg = i;
708  if (miscRegInfo[i][MISCREG_BANKED_CHILD])
709  unflattenResultMiscReg[i] = reg;
710  else
711  unflattenResultMiscReg[i] = i;
712  // if this assert fails, no parent was found, and something is broken
713  assert(unflattenResultMiscReg[i] > -1);
714  }
715 }
716 
717 int
718 unflattenMiscReg(int reg)
719 {
720  return unflattenResultMiscReg[reg];
721 }
722 
723 bool
724 canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
725  ThreadContext *tc)
726 {
727  // Check for SP_EL0 access while SPSEL == 0
728  if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
729  return false;
730 
731  // Check for RVBAR access
732  if (reg == MISCREG_RVBAR_EL1) {
733  ExceptionLevel highest_el = ArmSystem::highestEL(tc);
734  if (highest_el == EL2 || highest_el == EL3)
735  return false;
736  }
737  if (reg == MISCREG_RVBAR_EL2) {
738  ExceptionLevel highest_el = ArmSystem::highestEL(tc);
739  if (highest_el == EL3)
740  return false;
741  }
742 
743  bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
744  bool el2_host = EL2Enabled(tc) && hcr.e2h;
745 
746  switch (currEL(cpsr)) {
747  case EL0:
748  return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
749  miscRegInfo[reg][MISCREG_USR_NS_RD];
750  case EL1:
751  return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
752  miscRegInfo[reg][MISCREG_PRI_NS_RD];
753  case EL2:
754  if (el2_host) {
755  return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
756  miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
757  } else {
758  return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
759  miscRegInfo[reg][MISCREG_HYP_NS_RD];
760  }
761  case EL3:
762  return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
763  secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
764  miscRegInfo[reg][MISCREG_MON_NS1_RD];
765  default:
766  panic("Invalid exception level");
767  }
768 }
769 
770 bool
771 canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
772  ThreadContext *tc)
773 {
774  // Check for SP_EL0 access while SPSEL == 0
775  if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
776  return false;
777  ExceptionLevel el = currEL(cpsr);
778 
779  bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
780  bool el2_host = EL2Enabled(tc) && hcr.e2h;
781 
782  switch (el) {
783  case EL0:
784  return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
785  miscRegInfo[reg][MISCREG_USR_NS_WR];
786  case EL1:
787  return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
788  miscRegInfo[reg][MISCREG_PRI_NS_WR];
789  case EL2:
790  if (el2_host) {
791  return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
792  miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
793  } else {
794  return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
795  miscRegInfo[reg][MISCREG_HYP_NS_WR];
796  }
797  case EL3:
798  return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
799  secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
800  miscRegInfo[reg][MISCREG_MON_NS1_WR];
801  default:
802  panic("Invalid exception level");
803  }
804 }
805 
806 std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
807 
808 namespace {
809 
810 // The map is translating a MiscRegIndex into AArch64 system register
811 // numbers (op0, op1, crn, crm, op2)
812 std::unordered_map<MiscRegIndex, MiscRegNum64> idxToMiscRegNum;
813 
814 // The map is translating AArch64 system register numbers
815 // (op0, op1, crn, crm, op2) into a MiscRegIndex
816 std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
817  { MiscRegNum64(1, 0, 7, 1, 0), MISCREG_IC_IALLUIS },
818  { MiscRegNum64(1, 0, 7, 5, 0), MISCREG_IC_IALLU },
819  { MiscRegNum64(1, 0, 7, 6, 1), MISCREG_DC_IVAC_Xt },
820  { MiscRegNum64(1, 0, 7, 6, 2), MISCREG_DC_ISW_Xt },
821  { MiscRegNum64(1, 0, 7, 8, 0), MISCREG_AT_S1E1R_Xt },
822  { MiscRegNum64(1, 0, 7, 8, 1), MISCREG_AT_S1E1W_Xt },
823  { MiscRegNum64(1, 0, 7, 8, 2), MISCREG_AT_S1E0R_Xt },
824  { MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt },
825  { MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
826  { MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
827  { MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
828  { MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
829  { MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
830  { MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
831  { MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
832  { MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
833  { MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
834  { MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
835  { MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
836  { MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
837  { MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
838  { MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
839  { MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
840  { MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
841  { MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
842  { MiscRegNum64(1, 3, 7, 11, 1), MISCREG_DC_CVAU_Xt },
843  { MiscRegNum64(1, 3, 7, 14, 1), MISCREG_DC_CIVAC_Xt },
844  { MiscRegNum64(1, 4, 7, 8, 0), MISCREG_AT_S1E2R_Xt },
845  { MiscRegNum64(1, 4, 7, 8, 1), MISCREG_AT_S1E2W_Xt },
846  { MiscRegNum64(1, 4, 7, 8, 4), MISCREG_AT_S12E1R_Xt },
847  { MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
848  { MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
849  { MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
850  { MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
851  { MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
852  { MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
853  { MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
854  { MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
855  { MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
856  { MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
857  { MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
858  { MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
859  { MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
860  { MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
861  { MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
862  { MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
863  { MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
864  { MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
865  { MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
866  { MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
867  { MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
868  { MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
869  { MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
870  { MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
871  { MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
872  { MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
873  { MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
874  { MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
875  { MiscRegNum64(2, 0, 0, 0, 6), MISCREG_DBGWVR0_EL1 },
876  { MiscRegNum64(2, 0, 0, 0, 7), MISCREG_DBGWCR0_EL1 },
877  { MiscRegNum64(2, 0, 0, 1, 4), MISCREG_DBGBVR1_EL1 },
878  { MiscRegNum64(2, 0, 0, 1, 5), MISCREG_DBGBCR1_EL1 },
879  { MiscRegNum64(2, 0, 0, 1, 6), MISCREG_DBGWVR1_EL1 },
880  { MiscRegNum64(2, 0, 0, 1, 7), MISCREG_DBGWCR1_EL1 },
881  { MiscRegNum64(2, 0, 0, 2, 0), MISCREG_MDCCINT_EL1 },
882  { MiscRegNum64(2, 0, 0, 2, 2), MISCREG_MDSCR_EL1 },
883  { MiscRegNum64(2, 0, 0, 2, 4), MISCREG_DBGBVR2_EL1 },
884  { MiscRegNum64(2, 0, 0, 2, 5), MISCREG_DBGBCR2_EL1 },
885  { MiscRegNum64(2, 0, 0, 2, 6), MISCREG_DBGWVR2_EL1 },
886  { MiscRegNum64(2, 0, 0, 2, 7), MISCREG_DBGWCR2_EL1 },
887  { MiscRegNum64(2, 0, 0, 3, 2), MISCREG_OSDTRTX_EL1 },
888  { MiscRegNum64(2, 0, 0, 3, 4), MISCREG_DBGBVR3_EL1 },
889  { MiscRegNum64(2, 0, 0, 3, 5), MISCREG_DBGBCR3_EL1 },
890  { MiscRegNum64(2, 0, 0, 3, 6), MISCREG_DBGWVR3_EL1 },
891  { MiscRegNum64(2, 0, 0, 3, 7), MISCREG_DBGWCR3_EL1 },
892  { MiscRegNum64(2, 0, 0, 4, 4), MISCREG_DBGBVR4_EL1 },
893  { MiscRegNum64(2, 0, 0, 4, 5), MISCREG_DBGBCR4_EL1 },
894  { MiscRegNum64(2, 0, 0, 4, 6), MISCREG_DBGWVR4_EL1 },
895  { MiscRegNum64(2, 0, 0, 4, 7), MISCREG_DBGWCR4_EL1 },
896  { MiscRegNum64(2, 0, 0, 5, 4), MISCREG_DBGBVR5_EL1 },
897  { MiscRegNum64(2, 0, 0, 5, 5), MISCREG_DBGBCR5_EL1 },
898  { MiscRegNum64(2, 0, 0, 5, 6), MISCREG_DBGWVR5_EL1 },
899  { MiscRegNum64(2, 0, 0, 5, 7), MISCREG_DBGWCR5_EL1 },
900  { MiscRegNum64(2, 0, 0, 6, 2), MISCREG_OSECCR_EL1 },
901  { MiscRegNum64(2, 0, 0, 6, 4), MISCREG_DBGBVR6_EL1 },
902  { MiscRegNum64(2, 0, 0, 6, 5), MISCREG_DBGBCR6_EL1 },
903  { MiscRegNum64(2, 0, 0, 6, 6), MISCREG_DBGWVR6_EL1 },
904  { MiscRegNum64(2, 0, 0, 6, 7), MISCREG_DBGWCR6_EL1 },
905  { MiscRegNum64(2, 0, 0, 7, 4), MISCREG_DBGBVR7_EL1 },
906  { MiscRegNum64(2, 0, 0, 7, 5), MISCREG_DBGBCR7_EL1 },
907  { MiscRegNum64(2, 0, 0, 7, 6), MISCREG_DBGWVR7_EL1 },
908  { MiscRegNum64(2, 0, 0, 7, 7), MISCREG_DBGWCR7_EL1 },
909  { MiscRegNum64(2, 0, 0, 8, 4), MISCREG_DBGBVR8_EL1 },
910  { MiscRegNum64(2, 0, 0, 8, 5), MISCREG_DBGBCR8_EL1 },
911  { MiscRegNum64(2, 0, 0, 8, 6), MISCREG_DBGWVR8_EL1 },
912  { MiscRegNum64(2, 0, 0, 8, 7), MISCREG_DBGWCR8_EL1 },
913  { MiscRegNum64(2, 0, 0, 9, 4), MISCREG_DBGBVR9_EL1 },
914  { MiscRegNum64(2, 0, 0, 9, 5), MISCREG_DBGBCR9_EL1 },
915  { MiscRegNum64(2, 0, 0, 9, 6), MISCREG_DBGWVR9_EL1 },
916  { MiscRegNum64(2, 0, 0, 9, 7), MISCREG_DBGWCR9_EL1 },
917  { MiscRegNum64(2, 0, 0, 10, 4), MISCREG_DBGBVR10_EL1 },
918  { MiscRegNum64(2, 0, 0, 10, 5), MISCREG_DBGBCR10_EL1 },
919  { MiscRegNum64(2, 0, 0, 10, 6), MISCREG_DBGWVR10_EL1 },
920  { MiscRegNum64(2, 0, 0, 10, 7), MISCREG_DBGWCR10_EL1 },
921  { MiscRegNum64(2, 0, 0, 11, 4), MISCREG_DBGBVR11_EL1 },
922  { MiscRegNum64(2, 0, 0, 11, 5), MISCREG_DBGBCR11_EL1 },
923  { MiscRegNum64(2, 0, 0, 11, 6), MISCREG_DBGWVR11_EL1 },
924  { MiscRegNum64(2, 0, 0, 11, 7), MISCREG_DBGWCR11_EL1 },
925  { MiscRegNum64(2, 0, 0, 12, 4), MISCREG_DBGBVR12_EL1 },
926  { MiscRegNum64(2, 0, 0, 12, 5), MISCREG_DBGBCR12_EL1 },
927  { MiscRegNum64(2, 0, 0, 12, 6), MISCREG_DBGWVR12_EL1 },
928  { MiscRegNum64(2, 0, 0, 12, 7), MISCREG_DBGWCR12_EL1 },
929  { MiscRegNum64(2, 0, 0, 13, 4), MISCREG_DBGBVR13_EL1 },
930  { MiscRegNum64(2, 0, 0, 13, 5), MISCREG_DBGBCR13_EL1 },
931  { MiscRegNum64(2, 0, 0, 13, 6), MISCREG_DBGWVR13_EL1 },
932  { MiscRegNum64(2, 0, 0, 13, 7), MISCREG_DBGWCR13_EL1 },
933  { MiscRegNum64(2, 0, 0, 14, 4), MISCREG_DBGBVR14_EL1 },
934  { MiscRegNum64(2, 0, 0, 14, 5), MISCREG_DBGBCR14_EL1 },
935  { MiscRegNum64(2, 0, 0, 14, 6), MISCREG_DBGWVR14_EL1 },
936  { MiscRegNum64(2, 0, 0, 14, 7), MISCREG_DBGWCR14_EL1 },
937  { MiscRegNum64(2, 0, 0, 15, 4), MISCREG_DBGBVR15_EL1 },
938  { MiscRegNum64(2, 0, 0, 15, 5), MISCREG_DBGBCR15_EL1 },
939  { MiscRegNum64(2, 0, 0, 15, 6), MISCREG_DBGWVR15_EL1 },
940  { MiscRegNum64(2, 0, 0, 15, 7), MISCREG_DBGWCR15_EL1 },
941  { MiscRegNum64(2, 0, 1, 0, 0), MISCREG_MDRAR_EL1 },
942  { MiscRegNum64(2, 0, 1, 0, 4), MISCREG_OSLAR_EL1 },
943  { MiscRegNum64(2, 0, 1, 1, 4), MISCREG_OSLSR_EL1 },
944  { MiscRegNum64(2, 0, 1, 3, 4), MISCREG_OSDLR_EL1 },
945  { MiscRegNum64(2, 0, 1, 4, 4), MISCREG_DBGPRCR_EL1 },
946  { MiscRegNum64(2, 0, 7, 8, 6), MISCREG_DBGCLAIMSET_EL1 },
947  { MiscRegNum64(2, 0, 7, 9, 6), MISCREG_DBGCLAIMCLR_EL1 },
948  { MiscRegNum64(2, 0, 7, 14, 6), MISCREG_DBGAUTHSTATUS_EL1 },
949  { MiscRegNum64(2, 2, 0, 0, 0), MISCREG_TEECR32_EL1 },
950  { MiscRegNum64(2, 2, 1, 0, 0), MISCREG_TEEHBR32_EL1 },
951  { MiscRegNum64(2, 3, 0, 1, 0), MISCREG_MDCCSR_EL0 },
952  { MiscRegNum64(2, 3, 0, 4, 0), MISCREG_MDDTR_EL0 },
953  { MiscRegNum64(2, 3, 0, 5, 0), MISCREG_MDDTRRX_EL0 },
954  { MiscRegNum64(2, 4, 0, 7, 0), MISCREG_DBGVCR32_EL2 },
955  { MiscRegNum64(3, 0, 0, 0, 0), MISCREG_MIDR_EL1 },
956  { MiscRegNum64(3, 0, 0, 0, 5), MISCREG_MPIDR_EL1 },
957  { MiscRegNum64(3, 0, 0, 0, 6), MISCREG_REVIDR_EL1 },
958  { MiscRegNum64(3, 0, 0, 1, 0), MISCREG_ID_PFR0_EL1 },
959  { MiscRegNum64(3, 0, 0, 1, 1), MISCREG_ID_PFR1_EL1 },
960  { MiscRegNum64(3, 0, 0, 1, 2), MISCREG_ID_DFR0_EL1 },
961  { MiscRegNum64(3, 0, 0, 1, 3), MISCREG_ID_AFR0_EL1 },
962  { MiscRegNum64(3, 0, 0, 1, 4), MISCREG_ID_MMFR0_EL1 },
963  { MiscRegNum64(3, 0, 0, 1, 5), MISCREG_ID_MMFR1_EL1 },
964  { MiscRegNum64(3, 0, 0, 1, 6), MISCREG_ID_MMFR2_EL1 },
965  { MiscRegNum64(3, 0, 0, 1, 7), MISCREG_ID_MMFR3_EL1 },
966  { MiscRegNum64(3, 0, 0, 2, 0), MISCREG_ID_ISAR0_EL1 },
967  { MiscRegNum64(3, 0, 0, 2, 1), MISCREG_ID_ISAR1_EL1 },
968  { MiscRegNum64(3, 0, 0, 2, 2), MISCREG_ID_ISAR2_EL1 },
969  { MiscRegNum64(3, 0, 0, 2, 3), MISCREG_ID_ISAR3_EL1 },
970  { MiscRegNum64(3, 0, 0, 2, 4), MISCREG_ID_ISAR4_EL1 },
971  { MiscRegNum64(3, 0, 0, 2, 5), MISCREG_ID_ISAR5_EL1 },
972  { MiscRegNum64(3, 0, 0, 2, 6), MISCREG_ID_MMFR4_EL1 },
973  { MiscRegNum64(3, 0, 0, 2, 7), MISCREG_ID_ISAR6_EL1 },
974  { MiscRegNum64(3, 0, 0, 3, 0), MISCREG_MVFR0_EL1 },
975  { MiscRegNum64(3, 0, 0, 3, 1), MISCREG_MVFR1_EL1 },
976  { MiscRegNum64(3, 0, 0, 3, 2), MISCREG_MVFR2_EL1 },
977  { MiscRegNum64(3, 0, 0, 3, 3), MISCREG_RAZ },
978  { MiscRegNum64(3, 0, 0, 3, 4), MISCREG_RAZ },
979  { MiscRegNum64(3, 0, 0, 3, 5), MISCREG_RAZ },
980  { MiscRegNum64(3, 0, 0, 3, 6), MISCREG_RAZ },
981  { MiscRegNum64(3, 0, 0, 3, 7), MISCREG_RAZ },
982  { MiscRegNum64(3, 0, 0, 4, 0), MISCREG_ID_AA64PFR0_EL1 },
983  { MiscRegNum64(3, 0, 0, 4, 1), MISCREG_ID_AA64PFR1_EL1 },
984  { MiscRegNum64(3, 0, 0, 4, 2), MISCREG_RAZ },
985  { MiscRegNum64(3, 0, 0, 4, 3), MISCREG_RAZ },
986  { MiscRegNum64(3, 0, 0, 4, 4), MISCREG_ID_AA64ZFR0_EL1 },
987  { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_RAZ },
988  { MiscRegNum64(3, 0, 0, 4, 6), MISCREG_RAZ },
989  { MiscRegNum64(3, 0, 0, 4, 7), MISCREG_RAZ },
990  { MiscRegNum64(3, 0, 0, 5, 0), MISCREG_ID_AA64DFR0_EL1 },
991  { MiscRegNum64(3, 0, 0, 5, 1), MISCREG_ID_AA64DFR1_EL1 },
992  { MiscRegNum64(3, 0, 0, 5, 2), MISCREG_RAZ },
993  { MiscRegNum64(3, 0, 0, 5, 3), MISCREG_RAZ },
994  { MiscRegNum64(3, 0, 0, 5, 4), MISCREG_ID_AA64AFR0_EL1 },
995  { MiscRegNum64(3, 0, 0, 5, 5), MISCREG_ID_AA64AFR1_EL1 },
996  { MiscRegNum64(3, 0, 0, 5, 6), MISCREG_RAZ },
997  { MiscRegNum64(3, 0, 0, 5, 7), MISCREG_RAZ },
998  { MiscRegNum64(3, 0, 0, 6, 0), MISCREG_ID_AA64ISAR0_EL1 },
999  { MiscRegNum64(3, 0, 0, 6, 1), MISCREG_ID_AA64ISAR1_EL1 },
1000  { MiscRegNum64(3, 0, 0, 6, 2), MISCREG_RAZ },
1001  { MiscRegNum64(3, 0, 0, 6, 3), MISCREG_RAZ },
1002  { MiscRegNum64(3, 0, 0, 6, 4), MISCREG_RAZ },
1003  { MiscRegNum64(3, 0, 0, 6, 5), MISCREG_RAZ },
1004  { MiscRegNum64(3, 0, 0, 6, 6), MISCREG_RAZ },
1005  { MiscRegNum64(3, 0, 0, 6, 7), MISCREG_RAZ },
1006  { MiscRegNum64(3, 0, 0, 7, 0), MISCREG_ID_AA64MMFR0_EL1 },
1007  { MiscRegNum64(3, 0, 0, 7, 1), MISCREG_ID_AA64MMFR1_EL1 },
1008  { MiscRegNum64(3, 0, 0, 7, 2), MISCREG_ID_AA64MMFR2_EL1 },
1009  { MiscRegNum64(3, 0, 0, 7, 3), MISCREG_RAZ },
1010  { MiscRegNum64(3, 0, 0, 7, 4), MISCREG_RAZ },
1011  { MiscRegNum64(3, 0, 0, 7, 5), MISCREG_RAZ },
1012  { MiscRegNum64(3, 0, 0, 7, 6), MISCREG_RAZ },
1013  { MiscRegNum64(3, 0, 0, 7, 7), MISCREG_RAZ },
1014  { MiscRegNum64(3, 0, 1, 0, 0), MISCREG_SCTLR_EL1 },
1015  { MiscRegNum64(3, 0, 1, 0, 1), MISCREG_ACTLR_EL1 },
1016  { MiscRegNum64(3, 0, 1, 0, 2), MISCREG_CPACR_EL1 },
1017  { MiscRegNum64(3, 0, 1, 2, 0), MISCREG_ZCR_EL1 },
1018  { MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
1019  { MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
1020  { MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
1021  { MiscRegNum64(3, 0, 2, 1, 0), MISCREG_APIAKeyLo_EL1 },
1022  { MiscRegNum64(3, 0, 2, 1, 1), MISCREG_APIAKeyHi_EL1 },
1023  { MiscRegNum64(3, 0, 2, 1, 2), MISCREG_APIBKeyLo_EL1 },
1024  { MiscRegNum64(3, 0, 2, 1, 3), MISCREG_APIBKeyHi_EL1 },
1025  { MiscRegNum64(3, 0, 2, 2, 0), MISCREG_APDAKeyLo_EL1 },
1026  { MiscRegNum64(3, 0, 2, 2, 1), MISCREG_APDAKeyHi_EL1 },
1027  { MiscRegNum64(3, 0, 2, 2, 2), MISCREG_APDBKeyLo_EL1 },
1028  { MiscRegNum64(3, 0, 2, 2, 3), MISCREG_APDBKeyHi_EL1 },
1029  { MiscRegNum64(3, 0, 2, 3, 0), MISCREG_APGAKeyLo_EL1 },
1030  { MiscRegNum64(3, 0, 2, 3, 1), MISCREG_APGAKeyHi_EL1 },
1031  { MiscRegNum64(3, 0, 4, 0, 0), MISCREG_SPSR_EL1 },
1032  { MiscRegNum64(3, 0, 4, 0, 1), MISCREG_ELR_EL1 },
1033  { MiscRegNum64(3, 0, 4, 1, 0), MISCREG_SP_EL0 },
1034  { MiscRegNum64(3, 0, 4, 2, 0), MISCREG_SPSEL },
1035  { MiscRegNum64(3, 0, 4, 2, 2), MISCREG_CURRENTEL },
1036  { MiscRegNum64(3, 0, 4, 2, 3), MISCREG_PAN },
1037  { MiscRegNum64(3, 0, 4, 2, 4), MISCREG_UAO },
1038  { MiscRegNum64(3, 0, 4, 6, 0), MISCREG_ICC_PMR_EL1 },
1039  { MiscRegNum64(3, 0, 5, 1, 0), MISCREG_AFSR0_EL1 },
1040  { MiscRegNum64(3, 0, 5, 1, 1), MISCREG_AFSR1_EL1 },
1041  { MiscRegNum64(3, 0, 5, 2, 0), MISCREG_ESR_EL1 },
1042  { MiscRegNum64(3, 0, 5, 3, 0), MISCREG_ERRIDR_EL1 },
1043  { MiscRegNum64(3, 0, 5, 3, 1), MISCREG_ERRSELR_EL1 },
1044  { MiscRegNum64(3, 0, 5, 4, 0), MISCREG_ERXFR_EL1 },
1045  { MiscRegNum64(3, 0, 5, 4, 1), MISCREG_ERXCTLR_EL1 },
1046  { MiscRegNum64(3, 0, 5, 4, 2), MISCREG_ERXSTATUS_EL1 },
1047  { MiscRegNum64(3, 0, 5, 4, 3), MISCREG_ERXADDR_EL1 },
1048  { MiscRegNum64(3, 0, 5, 5, 0), MISCREG_ERXMISC0_EL1 },
1049  { MiscRegNum64(3, 0, 5, 5, 1), MISCREG_ERXMISC1_EL1 },
1050  { MiscRegNum64(3, 0, 6, 0, 0), MISCREG_FAR_EL1 },
1051  { MiscRegNum64(3, 0, 7, 4, 0), MISCREG_PAR_EL1 },
1052  { MiscRegNum64(3, 0, 9, 14, 1), MISCREG_PMINTENSET_EL1 },
1053  { MiscRegNum64(3, 0, 9, 14, 2), MISCREG_PMINTENCLR_EL1 },
1054  { MiscRegNum64(3, 0, 10, 2, 0), MISCREG_MAIR_EL1 },
1055  { MiscRegNum64(3, 0, 10, 3, 0), MISCREG_AMAIR_EL1 },
1056  { MiscRegNum64(3, 0, 12, 0, 0), MISCREG_VBAR_EL1 },
1057  { MiscRegNum64(3, 0, 12, 0, 1), MISCREG_RVBAR_EL1 },
1058  { MiscRegNum64(3, 0, 12, 1, 0), MISCREG_ISR_EL1 },
1059  { MiscRegNum64(3, 0, 12, 1, 1), MISCREG_DISR_EL1 },
1060  { MiscRegNum64(3, 0, 12, 8, 0), MISCREG_ICC_IAR0_EL1 },
1061  { MiscRegNum64(3, 0, 12, 8, 1), MISCREG_ICC_EOIR0_EL1 },
1062  { MiscRegNum64(3, 0, 12, 8, 2), MISCREG_ICC_HPPIR0_EL1 },
1063  { MiscRegNum64(3, 0, 12, 8, 3), MISCREG_ICC_BPR0_EL1 },
1064  { MiscRegNum64(3, 0, 12, 8, 4), MISCREG_ICC_AP0R0_EL1 },
1065  { MiscRegNum64(3, 0, 12, 8, 5), MISCREG_ICC_AP0R1_EL1 },
1066  { MiscRegNum64(3, 0, 12, 8, 6), MISCREG_ICC_AP0R2_EL1 },
1067  { MiscRegNum64(3, 0, 12, 8, 7), MISCREG_ICC_AP0R3_EL1 },
1068  { MiscRegNum64(3, 0, 12, 9, 0), MISCREG_ICC_AP1R0_EL1 },
1069  { MiscRegNum64(3, 0, 12, 9, 1), MISCREG_ICC_AP1R1_EL1 },
1070  { MiscRegNum64(3, 0, 12, 9, 2), MISCREG_ICC_AP1R2_EL1 },
1071  { MiscRegNum64(3, 0, 12, 9, 3), MISCREG_ICC_AP1R3_EL1 },
1072  { MiscRegNum64(3, 0, 12, 11, 1), MISCREG_ICC_DIR_EL1 },
1073  { MiscRegNum64(3, 0, 12, 11, 3), MISCREG_ICC_RPR_EL1 },
1074  { MiscRegNum64(3, 0, 12, 11, 5), MISCREG_ICC_SGI1R_EL1 },
1075  { MiscRegNum64(3, 0, 12, 11, 6), MISCREG_ICC_ASGI1R_EL1 },
1076  { MiscRegNum64(3, 0, 12, 11, 7), MISCREG_ICC_SGI0R_EL1 },
1077  { MiscRegNum64(3, 0, 12, 12, 0), MISCREG_ICC_IAR1_EL1 },
1078  { MiscRegNum64(3, 0, 12, 12, 1), MISCREG_ICC_EOIR1_EL1 },
1079  { MiscRegNum64(3, 0, 12, 12, 2), MISCREG_ICC_HPPIR1_EL1 },
1080  { MiscRegNum64(3, 0, 12, 12, 3), MISCREG_ICC_BPR1_EL1 },
1081  { MiscRegNum64(3, 0, 12, 12, 4), MISCREG_ICC_CTLR_EL1 },
1082  { MiscRegNum64(3, 0, 12, 12, 5), MISCREG_ICC_SRE_EL1 },
1083  { MiscRegNum64(3, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0_EL1 },
1084  { MiscRegNum64(3, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL1 },
1085  { MiscRegNum64(3, 0, 13, 0, 1), MISCREG_CONTEXTIDR_EL1 },
1086  { MiscRegNum64(3, 0, 13, 0, 4), MISCREG_TPIDR_EL1 },
1087  { MiscRegNum64(3, 0, 14, 1, 0), MISCREG_CNTKCTL_EL1 },
1088  { MiscRegNum64(3, 0, 15, 0, 0), MISCREG_IL1DATA0_EL1 },
1089  { MiscRegNum64(3, 0, 15, 0, 1), MISCREG_IL1DATA1_EL1 },
1090  { MiscRegNum64(3, 0, 15, 0, 2), MISCREG_IL1DATA2_EL1 },
1091  { MiscRegNum64(3, 0, 15, 0, 3), MISCREG_IL1DATA3_EL1 },
1092  { MiscRegNum64(3, 0, 15, 1, 0), MISCREG_DL1DATA0_EL1 },
1093  { MiscRegNum64(3, 0, 15, 1, 1), MISCREG_DL1DATA1_EL1 },
1094  { MiscRegNum64(3, 0, 15, 1, 2), MISCREG_DL1DATA2_EL1 },
1095  { MiscRegNum64(3, 0, 15, 1, 3), MISCREG_DL1DATA3_EL1 },
1096  { MiscRegNum64(3, 0, 15, 1, 4), MISCREG_DL1DATA4_EL1 },
1097  { MiscRegNum64(3, 1, 0, 0, 0), MISCREG_CCSIDR_EL1 },
1098  { MiscRegNum64(3, 1, 0, 0, 1), MISCREG_CLIDR_EL1 },
1099  { MiscRegNum64(3, 1, 0, 0, 7), MISCREG_AIDR_EL1 },
1100  { MiscRegNum64(3, 1, 11, 0, 2), MISCREG_L2CTLR_EL1 },
1101  { MiscRegNum64(3, 1, 11, 0, 3), MISCREG_L2ECTLR_EL1 },
1102  { MiscRegNum64(3, 1, 15, 0, 0), MISCREG_L2ACTLR_EL1 },
1103  { MiscRegNum64(3, 1, 15, 2, 0), MISCREG_CPUACTLR_EL1 },
1104  { MiscRegNum64(3, 1, 15, 2, 1), MISCREG_CPUECTLR_EL1 },
1105  { MiscRegNum64(3, 1, 15, 2, 2), MISCREG_CPUMERRSR_EL1 },
1106  { MiscRegNum64(3, 1, 15, 2, 3), MISCREG_L2MERRSR_EL1 },
1107  { MiscRegNum64(3, 1, 15, 3, 0), MISCREG_CBAR_EL1 },
1108  { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
1109  { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
1110  { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
1111  { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
1112  { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
1113  { MiscRegNum64(3, 3, 4, 4, 0), MISCREG_FPCR },
1114  { MiscRegNum64(3, 3, 4, 4, 1), MISCREG_FPSR },
1115  { MiscRegNum64(3, 3, 4, 5, 0), MISCREG_DSPSR_EL0 },
1116  { MiscRegNum64(3, 3, 4, 5, 1), MISCREG_DLR_EL0 },
1117  { MiscRegNum64(3, 3, 9, 12, 0), MISCREG_PMCR_EL0 },
1118  { MiscRegNum64(3, 3, 9, 12, 1), MISCREG_PMCNTENSET_EL0 },
1119  { MiscRegNum64(3, 3, 9, 12, 2), MISCREG_PMCNTENCLR_EL0 },
1120  { MiscRegNum64(3, 3, 9, 12, 3), MISCREG_PMOVSCLR_EL0 },
1121  { MiscRegNum64(3, 3, 9, 12, 4), MISCREG_PMSWINC_EL0 },
1122  { MiscRegNum64(3, 3, 9, 12, 5), MISCREG_PMSELR_EL0 },
1123  { MiscRegNum64(3, 3, 9, 12, 6), MISCREG_PMCEID0_EL0 },
1124  { MiscRegNum64(3, 3, 9, 12, 7), MISCREG_PMCEID1_EL0 },
1125  { MiscRegNum64(3, 3, 9, 13, 0), MISCREG_PMCCNTR_EL0 },
1126  { MiscRegNum64(3, 3, 9, 13, 1), MISCREG_PMXEVTYPER_EL0 },
1127  { MiscRegNum64(3, 3, 9, 13, 2), MISCREG_PMXEVCNTR_EL0 },
1128  { MiscRegNum64(3, 3, 9, 14, 0), MISCREG_PMUSERENR_EL0 },
1129  { MiscRegNum64(3, 3, 9, 14, 3), MISCREG_PMOVSSET_EL0 },
1130  { MiscRegNum64(3, 3, 13, 0, 2), MISCREG_TPIDR_EL0 },
1131  { MiscRegNum64(3, 3, 13, 0, 3), MISCREG_TPIDRRO_EL0 },
1132  { MiscRegNum64(3, 3, 14, 0, 0), MISCREG_CNTFRQ_EL0 },
1133  { MiscRegNum64(3, 3, 14, 0, 1), MISCREG_CNTPCT_EL0 },
1134  { MiscRegNum64(3, 3, 14, 0, 2), MISCREG_CNTVCT_EL0 },
1135  { MiscRegNum64(3, 3, 14, 2, 0), MISCREG_CNTP_TVAL_EL0 },
1136  { MiscRegNum64(3, 3, 14, 2, 1), MISCREG_CNTP_CTL_EL0 },
1137  { MiscRegNum64(3, 3, 14, 2, 2), MISCREG_CNTP_CVAL_EL0 },
1138  { MiscRegNum64(3, 3, 14, 3, 0), MISCREG_CNTV_TVAL_EL0 },
1139  { MiscRegNum64(3, 3, 14, 3, 1), MISCREG_CNTV_CTL_EL0 },
1140  { MiscRegNum64(3, 3, 14, 3, 2), MISCREG_CNTV_CVAL_EL0 },
1141  { MiscRegNum64(3, 3, 14, 8, 0), MISCREG_PMEVCNTR0_EL0 },
1142  { MiscRegNum64(3, 3, 14, 8, 1), MISCREG_PMEVCNTR1_EL0 },
1143  { MiscRegNum64(3, 3, 14, 8, 2), MISCREG_PMEVCNTR2_EL0 },
1144  { MiscRegNum64(3, 3, 14, 8, 3), MISCREG_PMEVCNTR3_EL0 },
1145  { MiscRegNum64(3, 3, 14, 8, 4), MISCREG_PMEVCNTR4_EL0 },
1146  { MiscRegNum64(3, 3, 14, 8, 5), MISCREG_PMEVCNTR5_EL0 },
1147  { MiscRegNum64(3, 3, 14, 12, 0), MISCREG_PMEVTYPER0_EL0 },
1148  { MiscRegNum64(3, 3, 14, 12, 1), MISCREG_PMEVTYPER1_EL0 },
1149  { MiscRegNum64(3, 3, 14, 12, 2), MISCREG_PMEVTYPER2_EL0 },
1150  { MiscRegNum64(3, 3, 14, 12, 3), MISCREG_PMEVTYPER3_EL0 },
1151  { MiscRegNum64(3, 3, 14, 12, 4), MISCREG_PMEVTYPER4_EL0 },
1152  { MiscRegNum64(3, 3, 14, 12, 5), MISCREG_PMEVTYPER5_EL0 },
1153  { MiscRegNum64(3, 3, 14, 15, 7), MISCREG_PMCCFILTR_EL0 },
1154  { MiscRegNum64(3, 4, 0, 0, 0), MISCREG_VPIDR_EL2 },
1155  { MiscRegNum64(3, 4, 0, 0, 5), MISCREG_VMPIDR_EL2 },
1156  { MiscRegNum64(3, 4, 1, 0, 0), MISCREG_SCTLR_EL2 },
1157  { MiscRegNum64(3, 4, 1, 0, 1), MISCREG_ACTLR_EL2 },
1158  { MiscRegNum64(3, 4, 1, 1, 0), MISCREG_HCR_EL2 },
1159  { MiscRegNum64(3, 4, 1, 1, 1), MISCREG_MDCR_EL2 },
1160  { MiscRegNum64(3, 4, 1, 1, 2), MISCREG_CPTR_EL2 },
1161  { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
1162  { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
1163  { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
1164  { MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
1165  { MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
1166  { MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
1167  { MiscRegNum64(3, 4, 2, 1, 0), MISCREG_VTTBR_EL2 },
1168  { MiscRegNum64(3, 4, 2, 1, 2), MISCREG_VTCR_EL2 },
1169  { MiscRegNum64(3, 4, 2, 6, 0), MISCREG_VSTTBR_EL2 },
1170  { MiscRegNum64(3, 4, 2, 6, 2), MISCREG_VSTCR_EL2 },
1171  { MiscRegNum64(3, 4, 3, 0, 0), MISCREG_DACR32_EL2 },
1172  { MiscRegNum64(3, 4, 4, 0, 0), MISCREG_SPSR_EL2 },
1173  { MiscRegNum64(3, 4, 4, 0, 1), MISCREG_ELR_EL2 },
1174  { MiscRegNum64(3, 4, 4, 1, 0), MISCREG_SP_EL1 },
1175  { MiscRegNum64(3, 4, 4, 3, 0), MISCREG_SPSR_IRQ_AA64 },
1176  { MiscRegNum64(3, 4, 4, 3, 1), MISCREG_SPSR_ABT_AA64 },
1177  { MiscRegNum64(3, 4, 4, 3, 2), MISCREG_SPSR_UND_AA64 },
1178  { MiscRegNum64(3, 4, 4, 3, 3), MISCREG_SPSR_FIQ_AA64 },
1179  { MiscRegNum64(3, 4, 5, 0, 1), MISCREG_IFSR32_EL2 },
1180  { MiscRegNum64(3, 4, 5, 1, 0), MISCREG_AFSR0_EL2 },
1181  { MiscRegNum64(3, 4, 5, 1, 1), MISCREG_AFSR1_EL2 },
1182  { MiscRegNum64(3, 4, 5, 2, 0), MISCREG_ESR_EL2 },
1183  { MiscRegNum64(3, 4, 5, 2, 3), MISCREG_VSESR_EL2 },
1184  { MiscRegNum64(3, 4, 5, 3, 0), MISCREG_FPEXC32_EL2 },
1185  { MiscRegNum64(3, 4, 6, 0, 0), MISCREG_FAR_EL2 },
1186  { MiscRegNum64(3, 4, 6, 0, 4), MISCREG_HPFAR_EL2 },
1187  { MiscRegNum64(3, 4, 10, 2, 0), MISCREG_MAIR_EL2 },
1188  { MiscRegNum64(3, 4, 10, 3, 0), MISCREG_AMAIR_EL2 },
1189  { MiscRegNum64(3, 4, 12, 0, 0), MISCREG_VBAR_EL2 },
1190  { MiscRegNum64(3, 4, 12, 0, 1), MISCREG_RVBAR_EL2 },
1191  { MiscRegNum64(3, 4, 12, 1, 1), MISCREG_VDISR_EL2 },
1192  { MiscRegNum64(3, 4, 12, 8, 0), MISCREG_ICH_AP0R0_EL2 },
1193  { MiscRegNum64(3, 4, 12, 8, 1), MISCREG_ICH_AP0R1_EL2 },
1194  { MiscRegNum64(3, 4, 12, 8, 2), MISCREG_ICH_AP0R2_EL2 },
1195  { MiscRegNum64(3, 4, 12, 8, 3), MISCREG_ICH_AP0R3_EL2 },
1196  { MiscRegNum64(3, 4, 12, 9, 0), MISCREG_ICH_AP1R0_EL2 },
1197  { MiscRegNum64(3, 4, 12, 9, 1), MISCREG_ICH_AP1R1_EL2 },
1198  { MiscRegNum64(3, 4, 12, 9, 2), MISCREG_ICH_AP1R2_EL2 },
1199  { MiscRegNum64(3, 4, 12, 9, 3), MISCREG_ICH_AP1R3_EL2 },
1200  { MiscRegNum64(3, 4, 12, 9, 5), MISCREG_ICC_SRE_EL2 },
1201  { MiscRegNum64(3, 4, 12, 11, 0), MISCREG_ICH_HCR_EL2 },
1202  { MiscRegNum64(3, 4, 12, 11, 1), MISCREG_ICH_VTR_EL2 },
1203  { MiscRegNum64(3, 4, 12, 11, 2), MISCREG_ICH_MISR_EL2 },
1204  { MiscRegNum64(3, 4, 12, 11, 3), MISCREG_ICH_EISR_EL2 },
1205  { MiscRegNum64(3, 4, 12, 11, 5), MISCREG_ICH_ELRSR_EL2 },
1206  { MiscRegNum64(3, 4, 12, 11, 7), MISCREG_ICH_VMCR_EL2 },
1207  { MiscRegNum64(3, 4, 12, 12, 0), MISCREG_ICH_LR0_EL2 },
1208  { MiscRegNum64(3, 4, 12, 12, 1), MISCREG_ICH_LR1_EL2 },
1209  { MiscRegNum64(3, 4, 12, 12, 2), MISCREG_ICH_LR2_EL2 },
1210  { MiscRegNum64(3, 4, 12, 12, 3), MISCREG_ICH_LR3_EL2 },
1211  { MiscRegNum64(3, 4, 12, 12, 4), MISCREG_ICH_LR4_EL2 },
1212  { MiscRegNum64(3, 4, 12, 12, 5), MISCREG_ICH_LR5_EL2 },
1213  { MiscRegNum64(3, 4, 12, 12, 6), MISCREG_ICH_LR6_EL2 },
1214  { MiscRegNum64(3, 4, 12, 12, 7), MISCREG_ICH_LR7_EL2 },
1215  { MiscRegNum64(3, 4, 12, 13, 0), MISCREG_ICH_LR8_EL2 },
1216  { MiscRegNum64(3, 4, 12, 13, 1), MISCREG_ICH_LR9_EL2 },
1217  { MiscRegNum64(3, 4, 12, 13, 2), MISCREG_ICH_LR10_EL2 },
1218  { MiscRegNum64(3, 4, 12, 13, 3), MISCREG_ICH_LR11_EL2 },
1219  { MiscRegNum64(3, 4, 12, 13, 4), MISCREG_ICH_LR12_EL2 },
1220  { MiscRegNum64(3, 4, 12, 13, 5), MISCREG_ICH_LR13_EL2 },
1221  { MiscRegNum64(3, 4, 12, 13, 6), MISCREG_ICH_LR14_EL2 },
1222  { MiscRegNum64(3, 4, 12, 13, 7), MISCREG_ICH_LR15_EL2 },
1223  { MiscRegNum64(3, 4, 13, 0, 1), MISCREG_CONTEXTIDR_EL2 },
1224  { MiscRegNum64(3, 4, 13, 0, 2), MISCREG_TPIDR_EL2 },
1225  { MiscRegNum64(3, 4, 14, 0, 3), MISCREG_CNTVOFF_EL2 },
1226  { MiscRegNum64(3, 4, 14, 1, 0), MISCREG_CNTHCTL_EL2 },
1227  { MiscRegNum64(3, 4, 14, 2, 0), MISCREG_CNTHP_TVAL_EL2 },
1228  { MiscRegNum64(3, 4, 14, 2, 1), MISCREG_CNTHP_CTL_EL2 },
1229  { MiscRegNum64(3, 4, 14, 2, 2), MISCREG_CNTHP_CVAL_EL2 },
1230  { MiscRegNum64(3, 4, 14, 3, 0), MISCREG_CNTHV_TVAL_EL2 },
1231  { MiscRegNum64(3, 4, 14, 3, 1), MISCREG_CNTHV_CTL_EL2 },
1232  { MiscRegNum64(3, 4, 14, 3, 2), MISCREG_CNTHV_CVAL_EL2 },
1233  { MiscRegNum64(3, 4, 14, 4, 0), MISCREG_CNTHVS_TVAL_EL2 },
1234  { MiscRegNum64(3, 4, 14, 4, 1), MISCREG_CNTHVS_CTL_EL2 },
1235  { MiscRegNum64(3, 4, 14, 4, 2), MISCREG_CNTHVS_CVAL_EL2 },
1236  { MiscRegNum64(3, 4, 14, 5, 0), MISCREG_CNTHPS_TVAL_EL2 },
1237  { MiscRegNum64(3, 4, 14, 5, 1), MISCREG_CNTHPS_CTL_EL2 },
1238  { MiscRegNum64(3, 4, 14, 5, 2), MISCREG_CNTHPS_CVAL_EL2 },
1239  { MiscRegNum64(3, 5, 1, 0, 0), MISCREG_SCTLR_EL12 },
1240  { MiscRegNum64(3, 5, 1, 0, 2), MISCREG_CPACR_EL12 },
1241  { MiscRegNum64(3, 5, 1, 2, 0), MISCREG_ZCR_EL12 },
1242  { MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
1243  { MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
1244  { MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
1245  { MiscRegNum64(3, 5, 4, 0, 0), MISCREG_SPSR_EL12 },
1246  { MiscRegNum64(3, 5, 4, 0, 1), MISCREG_ELR_EL12 },
1247  { MiscRegNum64(3, 5, 5, 1, 0), MISCREG_AFSR0_EL12 },
1248  { MiscRegNum64(3, 5, 5, 1, 1), MISCREG_AFSR1_EL12 },
1249  { MiscRegNum64(3, 5, 5, 2, 0), MISCREG_ESR_EL12 },
1250  { MiscRegNum64(3, 5, 6, 0, 0), MISCREG_FAR_EL12 },
1251  { MiscRegNum64(3, 5, 10, 2, 0), MISCREG_MAIR_EL12 },
1252  { MiscRegNum64(3, 5, 10, 3, 0), MISCREG_AMAIR_EL12 },
1253  { MiscRegNum64(3, 5, 12, 0, 0), MISCREG_VBAR_EL12 },
1254  { MiscRegNum64(3, 5, 13, 0, 1), MISCREG_CONTEXTIDR_EL12 },
1255  { MiscRegNum64(3, 5, 14, 1, 0), MISCREG_CNTKCTL_EL12 },
1256  { MiscRegNum64(3, 5, 14, 2, 0), MISCREG_CNTP_TVAL_EL02 },
1257  { MiscRegNum64(3, 5, 14, 2, 1), MISCREG_CNTP_CTL_EL02 },
1258  { MiscRegNum64(3, 5, 14, 2, 2), MISCREG_CNTP_CVAL_EL02 },
1259  { MiscRegNum64(3, 5, 14, 3, 0), MISCREG_CNTV_TVAL_EL02 },
1260  { MiscRegNum64(3, 5, 14, 3, 1), MISCREG_CNTV_CTL_EL02 },
1261  { MiscRegNum64(3, 5, 14, 3, 2), MISCREG_CNTV_CVAL_EL02 },
1262  { MiscRegNum64(3, 6, 1, 0, 0), MISCREG_SCTLR_EL3 },
1263  { MiscRegNum64(3, 6, 1, 0, 1), MISCREG_ACTLR_EL3 },
1264  { MiscRegNum64(3, 6, 1, 1, 0), MISCREG_SCR_EL3 },
1265  { MiscRegNum64(3, 6, 1, 1, 1), MISCREG_SDER32_EL3 },
1266  { MiscRegNum64(3, 6, 1, 1, 2), MISCREG_CPTR_EL3 },
1267  { MiscRegNum64(3, 6, 1, 2, 0), MISCREG_ZCR_EL3 },
1268  { MiscRegNum64(3, 6, 1, 3, 1), MISCREG_MDCR_EL3 },
1269  { MiscRegNum64(3, 6, 2, 0, 0), MISCREG_TTBR0_EL3 },
1270  { MiscRegNum64(3, 6, 2, 0, 2), MISCREG_TCR_EL3 },
1271  { MiscRegNum64(3, 6, 4, 0, 0), MISCREG_SPSR_EL3 },
1272  { MiscRegNum64(3, 6, 4, 0, 1), MISCREG_ELR_EL3 },
1273  { MiscRegNum64(3, 6, 4, 1, 0), MISCREG_SP_EL2 },
1274  { MiscRegNum64(3, 6, 5, 1, 0), MISCREG_AFSR0_EL3 },
1275  { MiscRegNum64(3, 6, 5, 1, 1), MISCREG_AFSR1_EL3 },
1276  { MiscRegNum64(3, 6, 5, 2, 0), MISCREG_ESR_EL3 },
1277  { MiscRegNum64(3, 6, 6, 0, 0), MISCREG_FAR_EL3 },
1278  { MiscRegNum64(3, 6, 10, 2, 0), MISCREG_MAIR_EL3 },
1279  { MiscRegNum64(3, 6, 10, 3, 0), MISCREG_AMAIR_EL3 },
1280  { MiscRegNum64(3, 6, 12, 0, 0), MISCREG_VBAR_EL3 },
1281  { MiscRegNum64(3, 6, 12, 0, 1), MISCREG_RVBAR_EL3 },
1282  { MiscRegNum64(3, 6, 12, 0, 2), MISCREG_RMR_EL3 },
1283  { MiscRegNum64(3, 6, 12, 12, 4), MISCREG_ICC_CTLR_EL3 },
1284  { MiscRegNum64(3, 6, 12, 12, 5), MISCREG_ICC_SRE_EL3 },
1285  { MiscRegNum64(3, 6, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL3 },
1286  { MiscRegNum64(3, 6, 13, 0, 2), MISCREG_TPIDR_EL3 },
1287  { MiscRegNum64(3, 7, 14, 2, 0), MISCREG_CNTPS_TVAL_EL1 },
1288  { MiscRegNum64(3, 7, 14, 2, 1), MISCREG_CNTPS_CTL_EL1 },
1289  { MiscRegNum64(3, 7, 14, 2, 2), MISCREG_CNTPS_CVAL_EL1 }
1290 };
1291 
1292 }
1293 
1294 MiscRegIndex
1295 decodeAArch64SysReg(unsigned op0, unsigned op1,
1296  unsigned crn, unsigned crm,
1297  unsigned op2)
1298 {
1299  MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
1300  auto it = miscRegNumToIdx.find(sys_reg);
1301  if (it != miscRegNumToIdx.end()) {
1302  return it->second;
1303  } else {
1304  // Check for a pseudo register before returning MISCREG_UNKNOWN
1305  if ((op0 == 1 || op0 == 3) && (crn == 11 || crn == 15)) {
1306  return MISCREG_IMPDEF_UNIMPL;
1307  } else {
1308  return MISCREG_UNKNOWN;
1309  }
1310  }
1311 }
1312 
1313 MiscRegNum64
1314 encodeAArch64SysReg(MiscRegIndex misc_reg)
1315 {
1316  if (auto it = idxToMiscRegNum.find(misc_reg);
1317  it != idxToMiscRegNum.end()) {
1318  return it->second;
1319  } else {
1320  panic("Invalid MiscRegIndex: %n\n", misc_reg);
1321  }
1322 }
1323 
1324 void
1325 ISA::initializeMiscRegMetadata()
1326 {
1327  // the MiscReg metadata tables are shared across all instances of the
1328  // ISA object, so there's no need to initialize them multiple times.
1329  static bool completed = false;
1330  if (completed)
1331  return;
1332 
1333  // This boolean variable specifies if the system is running in aarch32 at
1334  // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
1335  // is running in aarch64 (aarch32EL3 = false)
1336  bool aarch32EL3 = release->has(ArmExtension::SECURITY) && !highestELIs64;
1337 
1338  // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
1339  // unsupported
1340  bool SPAN = false;
1341 
1342  // Implicit error synchronization event enable (Arm 8.2+), unsupported
1343  bool IESB = false;
1344 
1345  // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
1346  // unsupported
1347  bool LSMAOE = false;
1348 
1349  // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
1350  bool nTLSMD = false;
1351 
1352  // Pointer authentication (Arm 8.3+), unsupported
1353  bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
1354  bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
1355  bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
1356  bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
1357 
1358  const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE);
1359  const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2);
1373  InitReg(MISCREG_CPSR)
1374  .allPrivileges();
1375  InitReg(MISCREG_SPSR)
1376  .allPrivileges();
1377  InitReg(MISCREG_SPSR_FIQ)
1378  .allPrivileges();
1379  InitReg(MISCREG_SPSR_IRQ)
1380  .allPrivileges();
1381  InitReg(MISCREG_SPSR_SVC)
1382  .allPrivileges();
1383  InitReg(MISCREG_SPSR_MON)
1384  .allPrivileges();
1385  InitReg(MISCREG_SPSR_ABT)
1386  .allPrivileges();
1387  InitReg(MISCREG_SPSR_HYP)
1388  .allPrivileges();
1389  InitReg(MISCREG_SPSR_UND)
1390  .allPrivileges();
1391  InitReg(MISCREG_ELR_HYP)
1392  .allPrivileges();
1393  InitReg(MISCREG_FPSID)
1394  .allPrivileges();
1395  InitReg(MISCREG_FPSCR)
1396  .allPrivileges();
1397  InitReg(MISCREG_MVFR1)
1398  .allPrivileges();
1399  InitReg(MISCREG_MVFR0)
1400  .allPrivileges();
1401  InitReg(MISCREG_FPEXC)
1402  .allPrivileges();
1403 
1404  // Helper registers
1405  InitReg(MISCREG_CPSR_MODE)
1406  .allPrivileges();
1407  InitReg(MISCREG_CPSR_Q)
1408  .allPrivileges();
1409  InitReg(MISCREG_FPSCR_EXC)
1410  .allPrivileges();
1411  InitReg(MISCREG_FPSCR_QC)
1412  .allPrivileges();
1413  InitReg(MISCREG_LOCKADDR)
1414  .allPrivileges();
1415  InitReg(MISCREG_LOCKFLAG)
1416  .allPrivileges();
1417  InitReg(MISCREG_PRRR_MAIR0)
1418  .mutex()
1419  .banked();
1420  InitReg(MISCREG_PRRR_MAIR0_NS)
1421  .mutex()
1422  .privSecure(!aarch32EL3)
1423  .bankedChild();
1424  InitReg(MISCREG_PRRR_MAIR0_S)
1425  .mutex()
1426  .bankedChild();
1427  InitReg(MISCREG_NMRR_MAIR1)
1428  .mutex()
1429  .banked();
1430  InitReg(MISCREG_NMRR_MAIR1_NS)
1431  .mutex()
1432  .privSecure(!aarch32EL3)
1433  .bankedChild();
1434  InitReg(MISCREG_NMRR_MAIR1_S)
1435  .mutex()
1436  .bankedChild();
1437  InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
1438  .mutex();
1439  InitReg(MISCREG_SCTLR_RST)
1440  .allPrivileges();
1441  InitReg(MISCREG_SEV_MAILBOX)
1442  .allPrivileges();
1443  InitReg(MISCREG_TLBINEEDSYNC)
1444  .allPrivileges().exceptUserMode();
1445 
1446  // AArch32 CP14 registers
1447  InitReg(MISCREG_DBGDIDR)
1448  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1449  InitReg(MISCREG_DBGDSCRint)
1450  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1451  InitReg(MISCREG_DBGDCCINT)
1452  .unimplemented()
1453  .allPrivileges();
1454  InitReg(MISCREG_DBGDTRTXint)
1455  .unimplemented()
1456  .allPrivileges();
1457  InitReg(MISCREG_DBGDTRRXint)
1458  .unimplemented()
1459  .allPrivileges();
1460  InitReg(MISCREG_DBGWFAR)
1461  .unimplemented()
1462  .allPrivileges();
1463  InitReg(MISCREG_DBGVCR)
1464  .allPrivileges().exceptUserMode();
1465  InitReg(MISCREG_DBGDTRRXext)
1466  .unimplemented()
1467  .allPrivileges();
1468  InitReg(MISCREG_DBGDSCRext)
1469  .allPrivileges();
1470  InitReg(MISCREG_DBGDTRTXext)
1471  .unimplemented()
1472  .allPrivileges();
1473  InitReg(MISCREG_DBGOSECCR)
1474  .unimplemented()
1475  .allPrivileges();
1476  InitReg(MISCREG_DBGBVR0)
1477  .allPrivileges().exceptUserMode();
1478  InitReg(MISCREG_DBGBVR1)
1479  .allPrivileges().exceptUserMode();
1480  InitReg(MISCREG_DBGBVR2)
1481  .allPrivileges().exceptUserMode();
1482  InitReg(MISCREG_DBGBVR3)
1483  .allPrivileges().exceptUserMode();
1484  InitReg(MISCREG_DBGBVR4)
1485  .allPrivileges().exceptUserMode();
1486  InitReg(MISCREG_DBGBVR5)
1487  .allPrivileges().exceptUserMode();
1488  InitReg(MISCREG_DBGBVR6)
1489  .allPrivileges().exceptUserMode();
1490  InitReg(MISCREG_DBGBVR7)
1491  .allPrivileges().exceptUserMode();
1492  InitReg(MISCREG_DBGBVR8)
1493  .allPrivileges().exceptUserMode();
1494  InitReg(MISCREG_DBGBVR9)
1495  .allPrivileges().exceptUserMode();
1496  InitReg(MISCREG_DBGBVR10)
1497  .allPrivileges().exceptUserMode();
1498  InitReg(MISCREG_DBGBVR11)
1499  .allPrivileges().exceptUserMode();
1500  InitReg(MISCREG_DBGBVR12)
1501  .allPrivileges().exceptUserMode();
1502  InitReg(MISCREG_DBGBVR13)
1503  .allPrivileges().exceptUserMode();
1504  InitReg(MISCREG_DBGBVR14)
1505  .allPrivileges().exceptUserMode();
1506  InitReg(MISCREG_DBGBVR15)
1507  .allPrivileges().exceptUserMode();
1508  InitReg(MISCREG_DBGBCR0)
1509  .allPrivileges().exceptUserMode();
1510  InitReg(MISCREG_DBGBCR1)
1511  .allPrivileges().exceptUserMode();
1512  InitReg(MISCREG_DBGBCR2)
1513  .allPrivileges().exceptUserMode();
1514  InitReg(MISCREG_DBGBCR3)
1515  .allPrivileges().exceptUserMode();
1516  InitReg(MISCREG_DBGBCR4)
1517  .allPrivileges().exceptUserMode();
1518  InitReg(MISCREG_DBGBCR5)
1519  .allPrivileges().exceptUserMode();
1520  InitReg(MISCREG_DBGBCR6)
1521  .allPrivileges().exceptUserMode();
1522  InitReg(MISCREG_DBGBCR7)
1523  .allPrivileges().exceptUserMode();
1524  InitReg(MISCREG_DBGBCR8)
1525  .allPrivileges().exceptUserMode();
1526  InitReg(MISCREG_DBGBCR9)
1527  .allPrivileges().exceptUserMode();
1528  InitReg(MISCREG_DBGBCR10)
1529  .allPrivileges().exceptUserMode();
1530  InitReg(MISCREG_DBGBCR11)
1531  .allPrivileges().exceptUserMode();
1532  InitReg(MISCREG_DBGBCR12)
1533  .allPrivileges().exceptUserMode();
1534  InitReg(MISCREG_DBGBCR13)
1535  .allPrivileges().exceptUserMode();
1536  InitReg(MISCREG_DBGBCR14)
1537  .allPrivileges().exceptUserMode();
1538  InitReg(MISCREG_DBGBCR15)
1539  .allPrivileges().exceptUserMode();
1540  InitReg(MISCREG_DBGWVR0)
1541  .allPrivileges().exceptUserMode();
1542  InitReg(MISCREG_DBGWVR1)
1543  .allPrivileges().exceptUserMode();
1544  InitReg(MISCREG_DBGWVR2)
1545  .allPrivileges().exceptUserMode();
1546  InitReg(MISCREG_DBGWVR3)
1547  .allPrivileges().exceptUserMode();
1548  InitReg(MISCREG_DBGWVR4)
1549  .allPrivileges().exceptUserMode();
1550  InitReg(MISCREG_DBGWVR5)
1551  .allPrivileges().exceptUserMode();
1552  InitReg(MISCREG_DBGWVR6)
1553  .allPrivileges().exceptUserMode();
1554  InitReg(MISCREG_DBGWVR7)
1555  .allPrivileges().exceptUserMode();
1556  InitReg(MISCREG_DBGWVR8)
1557  .allPrivileges().exceptUserMode();
1558  InitReg(MISCREG_DBGWVR9)
1559  .allPrivileges().exceptUserMode();
1560  InitReg(MISCREG_DBGWVR10)
1561  .allPrivileges().exceptUserMode();
1562  InitReg(MISCREG_DBGWVR11)
1563  .allPrivileges().exceptUserMode();
1564  InitReg(MISCREG_DBGWVR12)
1565  .allPrivileges().exceptUserMode();
1566  InitReg(MISCREG_DBGWVR13)
1567  .allPrivileges().exceptUserMode();
1568  InitReg(MISCREG_DBGWVR14)
1569  .allPrivileges().exceptUserMode();
1570  InitReg(MISCREG_DBGWVR15)
1571  .allPrivileges().exceptUserMode();
1572  InitReg(MISCREG_DBGWCR0)
1573  .allPrivileges().exceptUserMode();
1574  InitReg(MISCREG_DBGWCR1)
1575  .allPrivileges().exceptUserMode();
1576  InitReg(MISCREG_DBGWCR2)
1577  .allPrivileges().exceptUserMode();
1578  InitReg(MISCREG_DBGWCR3)
1579  .allPrivileges().exceptUserMode();
1580  InitReg(MISCREG_DBGWCR4)
1581  .allPrivileges().exceptUserMode();
1582  InitReg(MISCREG_DBGWCR5)
1583  .allPrivileges().exceptUserMode();
1584  InitReg(MISCREG_DBGWCR6)
1585  .allPrivileges().exceptUserMode();
1586  InitReg(MISCREG_DBGWCR7)
1587  .allPrivileges().exceptUserMode();
1588  InitReg(MISCREG_DBGWCR8)
1589  .allPrivileges().exceptUserMode();
1590  InitReg(MISCREG_DBGWCR9)
1591  .allPrivileges().exceptUserMode();
1592  InitReg(MISCREG_DBGWCR10)
1593  .allPrivileges().exceptUserMode();
1594  InitReg(MISCREG_DBGWCR11)
1595  .allPrivileges().exceptUserMode();
1596  InitReg(MISCREG_DBGWCR12)
1597  .allPrivileges().exceptUserMode();
1598  InitReg(MISCREG_DBGWCR13)
1599  .allPrivileges().exceptUserMode();
1600  InitReg(MISCREG_DBGWCR14)
1601  .allPrivileges().exceptUserMode();
1602  InitReg(MISCREG_DBGWCR15)
1603  .allPrivileges().exceptUserMode();
1604  InitReg(MISCREG_DBGDRAR)
1605  .unimplemented()
1606  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1607  InitReg(MISCREG_DBGBXVR0)
1608  .allPrivileges().exceptUserMode();
1609  InitReg(MISCREG_DBGBXVR1)
1610  .allPrivileges().exceptUserMode();
1611  InitReg(MISCREG_DBGBXVR2)
1612  .allPrivileges().exceptUserMode();
1613  InitReg(MISCREG_DBGBXVR3)
1614  .allPrivileges().exceptUserMode();
1615  InitReg(MISCREG_DBGBXVR4)
1616  .allPrivileges().exceptUserMode();
1617  InitReg(MISCREG_DBGBXVR5)
1618  .allPrivileges().exceptUserMode();
1619  InitReg(MISCREG_DBGBXVR0)
1620  .allPrivileges().exceptUserMode();
1621  InitReg(MISCREG_DBGBXVR6)
1622  .allPrivileges().exceptUserMode();
1623  InitReg(MISCREG_DBGBXVR7)
1624  .allPrivileges().exceptUserMode();
1625  InitReg(MISCREG_DBGBXVR8)
1626  .allPrivileges().exceptUserMode();
1627  InitReg(MISCREG_DBGBXVR9)
1628  .allPrivileges().exceptUserMode();
1629  InitReg(MISCREG_DBGBXVR10)
1630  .allPrivileges().exceptUserMode();
1631  InitReg(MISCREG_DBGBXVR11)
1632  .allPrivileges().exceptUserMode();
1633  InitReg(MISCREG_DBGBXVR12)
1634  .allPrivileges().exceptUserMode();
1635  InitReg(MISCREG_DBGBXVR13)
1636  .allPrivileges().exceptUserMode();
1637  InitReg(MISCREG_DBGBXVR14)
1638  .allPrivileges().exceptUserMode();
1639  InitReg(MISCREG_DBGBXVR15)
1640  .allPrivileges().exceptUserMode();
1641  InitReg(MISCREG_DBGOSLAR)
1642  .allPrivileges().monSecureRead(0).monNonSecureRead(0);
1643  InitReg(MISCREG_DBGOSLSR)
1644  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1645  InitReg(MISCREG_DBGOSDLR)
1646  .unimplemented()
1647  .warnNotFail()
1648  .allPrivileges();
1649  InitReg(MISCREG_DBGPRCR)
1650  .unimplemented()
1651  .allPrivileges();
1652  InitReg(MISCREG_DBGDSAR)
1653  .unimplemented()
1654  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1655  InitReg(MISCREG_DBGCLAIMSET)
1656  .unimplemented()
1657  .allPrivileges();
1658  InitReg(MISCREG_DBGCLAIMCLR)
1659  .unimplemented()
1660  .allPrivileges();
1661  InitReg(MISCREG_DBGAUTHSTATUS)
1662  .unimplemented()
1663  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1664  InitReg(MISCREG_DBGDEVID2)
1665  .unimplemented()
1666  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1667  InitReg(MISCREG_DBGDEVID1)
1668  .unimplemented()
1669  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1670  InitReg(MISCREG_DBGDEVID0)
1671  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
1672  InitReg(MISCREG_TEECR)
1673  .unimplemented()
1674  .allPrivileges();
1675  InitReg(MISCREG_JIDR)
1676  .allPrivileges();
1677  InitReg(MISCREG_TEEHBR)
1678  .allPrivileges();
1679  InitReg(MISCREG_JOSCR)
1680  .allPrivileges();
1681  InitReg(MISCREG_JMCR)
1682  .allPrivileges();
1683 
1684  // AArch32 CP15 registers
1685  InitReg(MISCREG_MIDR)
1686  .allPrivileges().exceptUserMode().writes(0);
1687  InitReg(MISCREG_CTR)
1688  .allPrivileges().exceptUserMode().writes(0);
1689  InitReg(MISCREG_TCMTR)
1690  .allPrivileges().exceptUserMode().writes(0);
1691  InitReg(MISCREG_TLBTR)
1692  .allPrivileges().exceptUserMode().writes(0);
1693  InitReg(MISCREG_MPIDR)
1694  .allPrivileges().exceptUserMode().writes(0);
1695  InitReg(MISCREG_REVIDR)
1696  .unimplemented()
1697  .warnNotFail()
1698  .allPrivileges().exceptUserMode().writes(0);
1699  InitReg(MISCREG_ID_PFR0)
1700  .allPrivileges().exceptUserMode().writes(0);
1701  InitReg(MISCREG_ID_PFR1)
1702  .allPrivileges().exceptUserMode().writes(0);
1703  InitReg(MISCREG_ID_DFR0)
1704  .allPrivileges().exceptUserMode().writes(0);
1705  InitReg(MISCREG_ID_AFR0)
1706  .allPrivileges().exceptUserMode().writes(0);
1707  InitReg(MISCREG_ID_MMFR0)
1708  .allPrivileges().exceptUserMode().writes(0);
1709  InitReg(MISCREG_ID_MMFR1)
1710  .allPrivileges().exceptUserMode().writes(0);
1711  InitReg(MISCREG_ID_MMFR2)
1712  .allPrivileges().exceptUserMode().writes(0);
1713  InitReg(MISCREG_ID_MMFR3)
1714  .allPrivileges().exceptUserMode().writes(0);
1715  InitReg(MISCREG_ID_MMFR4)
1716  .allPrivileges().exceptUserMode().writes(0);
1717  InitReg(MISCREG_ID_ISAR0)
1718  .allPrivileges().exceptUserMode().writes(0);
1719  InitReg(MISCREG_ID_ISAR1)
1720  .allPrivileges().exceptUserMode().writes(0);
1721  InitReg(MISCREG_ID_ISAR2)
1722  .allPrivileges().exceptUserMode().writes(0);
1723  InitReg(MISCREG_ID_ISAR3)
1724  .allPrivileges().exceptUserMode().writes(0);
1725  InitReg(MISCREG_ID_ISAR4)
1726  .allPrivileges().exceptUserMode().writes(0);
1727  InitReg(MISCREG_ID_ISAR5)
1728  .allPrivileges().exceptUserMode().writes(0);
1729  InitReg(MISCREG_ID_ISAR6)
1730  .allPrivileges().exceptUserMode().writes(0);
1731  InitReg(MISCREG_CCSIDR)
1732  .allPrivileges().exceptUserMode().writes(0);
1733  InitReg(MISCREG_CLIDR)
1734  .allPrivileges().exceptUserMode().writes(0);
1735  InitReg(MISCREG_AIDR)
1736  .allPrivileges().exceptUserMode().writes(0);
1737  InitReg(MISCREG_CSSELR)
1738  .banked();
1739  InitReg(MISCREG_CSSELR_NS)
1740  .bankedChild()
1741  .privSecure(!aarch32EL3)
1742  .nonSecure().exceptUserMode();
1743  InitReg(MISCREG_CSSELR_S)
1744  .bankedChild()
1745  .secure().exceptUserMode();
1746  InitReg(MISCREG_VPIDR)
1747  .hyp().monNonSecure();
1748  InitReg(MISCREG_VMPIDR)
1749  .hyp().monNonSecure();
1750  InitReg(MISCREG_SCTLR)
1751  .banked()
1752  // readMiscRegNoEffect() uses this metadata
1753  // despite using children (below) as backing store
1754  .res0(0x8d22c600)
1755  .res1(0x00400800 | (SPAN ? 0 : 0x800000)
1756  | (LSMAOE ? 0 : 0x10)
1757  | (nTLSMD ? 0 : 0x8));
1758  InitReg(MISCREG_SCTLR_NS)
1759  .bankedChild()
1760  .privSecure(!aarch32EL3)
1761  .nonSecure().exceptUserMode();
1762  InitReg(MISCREG_SCTLR_S)
1763  .bankedChild()
1764  .secure().exceptUserMode();
1765  InitReg(MISCREG_ACTLR)
1766  .banked();
1767  InitReg(MISCREG_ACTLR_NS)
1768  .bankedChild()
1769  .privSecure(!aarch32EL3)
1770  .nonSecure().exceptUserMode();
1771  InitReg(MISCREG_ACTLR_S)
1772  .bankedChild()
1773  .secure().exceptUserMode();
1774  InitReg(MISCREG_CPACR)
1775  .allPrivileges().exceptUserMode();
1776  InitReg(MISCREG_SDCR)
1777  .mon();
1778  InitReg(MISCREG_SCR)
1779  .mon().secure().exceptUserMode()
1780  .res0(0xff40) // [31:16], [6]
1781  .res1(0x0030); // [5:4]
1782  InitReg(MISCREG_SDER)
1783  .mon();
1784  InitReg(MISCREG_NSACR)
1785  .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
1786  InitReg(MISCREG_HSCTLR)
1787  .hyp().monNonSecure()
1788  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
1789  | (IESB ? 0 : 0x200000)
1790  | (EnDA ? 0 : 0x8000000)
1791  | (EnIB ? 0 : 0x40000000)
1792  | (EnIA ? 0 : 0x80000000))
1793  .res1(0x30c50830);
1794  InitReg(MISCREG_HACTLR)
1795  .hyp().monNonSecure();
1796  InitReg(MISCREG_HCR)
1797  .hyp().monNonSecure()
1798  .res0(0x90000000);
1799  InitReg(MISCREG_HCR2)
1800  .hyp().monNonSecure()
1801  .res0(0xffa9ff8c);
1802  InitReg(MISCREG_HDCR)
1803  .hyp().monNonSecure();
1804  InitReg(MISCREG_HCPTR)
1805  .hyp().monNonSecure();
1806  InitReg(MISCREG_HSTR)
1807  .hyp().monNonSecure();
1808  InitReg(MISCREG_HACR)
1809  .unimplemented()
1810  .warnNotFail()
1811  .hyp().monNonSecure();
1812  InitReg(MISCREG_TTBR0)
1813  .banked();
1814  InitReg(MISCREG_TTBR0_NS)
1815  .bankedChild()
1816  .privSecure(!aarch32EL3)
1817  .nonSecure().exceptUserMode();
1818  InitReg(MISCREG_TTBR0_S)
1819  .bankedChild()
1820  .secure().exceptUserMode();
1821  InitReg(MISCREG_TTBR1)
1822  .banked();
1823  InitReg(MISCREG_TTBR1_NS)
1824  .bankedChild()
1825  .privSecure(!aarch32EL3)
1826  .nonSecure().exceptUserMode();
1827  InitReg(MISCREG_TTBR1_S)
1828  .bankedChild()
1829  .secure().exceptUserMode();
1830  InitReg(MISCREG_TTBCR)
1831  .banked();
1832  InitReg(MISCREG_TTBCR_NS)
1833  .bankedChild()
1834  .privSecure(!aarch32EL3)
1835  .nonSecure().exceptUserMode();
1836  InitReg(MISCREG_TTBCR_S)
1837  .bankedChild()
1838  .secure().exceptUserMode();
1839  InitReg(MISCREG_HTCR)
1840  .hyp().monNonSecure();
1841  InitReg(MISCREG_VTCR)
1842  .hyp().monNonSecure();
1843  InitReg(MISCREG_DACR)
1844  .banked();
1845  InitReg(MISCREG_DACR_NS)
1846  .bankedChild()
1847  .privSecure(!aarch32EL3)
1848  .nonSecure().exceptUserMode();
1849  InitReg(MISCREG_DACR_S)
1850  .bankedChild()
1851  .secure().exceptUserMode();
1852  InitReg(MISCREG_DFSR)
1853  .banked();
1854  InitReg(MISCREG_DFSR_NS)
1855  .bankedChild()
1856  .privSecure(!aarch32EL3)
1857  .nonSecure().exceptUserMode();
1858  InitReg(MISCREG_DFSR_S)
1859  .bankedChild()
1860  .secure().exceptUserMode();
1861  InitReg(MISCREG_IFSR)
1862  .banked();
1863  InitReg(MISCREG_IFSR_NS)
1864  .bankedChild()
1865  .privSecure(!aarch32EL3)
1866  .nonSecure().exceptUserMode();
1867  InitReg(MISCREG_IFSR_S)
1868  .bankedChild()
1869  .secure().exceptUserMode();
1870  InitReg(MISCREG_ADFSR)
1871  .unimplemented()
1872  .warnNotFail()
1873  .banked();
1874  InitReg(MISCREG_ADFSR_NS)
1875  .unimplemented()
1876  .warnNotFail()
1877  .bankedChild()
1878  .privSecure(!aarch32EL3)
1879  .nonSecure().exceptUserMode();
1880  InitReg(MISCREG_ADFSR_S)
1881  .unimplemented()
1882  .warnNotFail()
1883  .bankedChild()
1884  .secure().exceptUserMode();
1885  InitReg(MISCREG_AIFSR)
1886  .unimplemented()
1887  .warnNotFail()
1888  .banked();
1889  InitReg(MISCREG_AIFSR_NS)
1890  .unimplemented()
1891  .warnNotFail()
1892  .bankedChild()
1893  .privSecure(!aarch32EL3)
1894  .nonSecure().exceptUserMode();
1895  InitReg(MISCREG_AIFSR_S)
1896  .unimplemented()
1897  .warnNotFail()
1898  .bankedChild()
1899  .secure().exceptUserMode();
1900  InitReg(MISCREG_HADFSR)
1901  .hyp().monNonSecure();
1902  InitReg(MISCREG_HAIFSR)
1903  .hyp().monNonSecure();
1904  InitReg(MISCREG_HSR)
1905  .hyp().monNonSecure();
1906  InitReg(MISCREG_DFAR)
1907  .banked();
1908  InitReg(MISCREG_DFAR_NS)
1909  .bankedChild()
1910  .privSecure(!aarch32EL3)
1911  .nonSecure().exceptUserMode();
1912  InitReg(MISCREG_DFAR_S)
1913  .bankedChild()
1914  .secure().exceptUserMode();
1915  InitReg(MISCREG_IFAR)
1916  .banked();
1917  InitReg(MISCREG_IFAR_NS)
1918  .bankedChild()
1919  .privSecure(!aarch32EL3)
1920  .nonSecure().exceptUserMode();
1921  InitReg(MISCREG_IFAR_S)
1922  .bankedChild()
1923  .secure().exceptUserMode();
1924  InitReg(MISCREG_HDFAR)
1925  .hyp().monNonSecure();
1926  InitReg(MISCREG_HIFAR)
1927  .hyp().monNonSecure();
1928  InitReg(MISCREG_HPFAR)
1929  .hyp().monNonSecure();
1930  InitReg(MISCREG_ICIALLUIS)
1931  .unimplemented()
1932  .warnNotFail()
1933  .writes(1).exceptUserMode();
1934  InitReg(MISCREG_BPIALLIS)
1935  .unimplemented()
1936  .warnNotFail()
1937  .writes(1).exceptUserMode();
1938  InitReg(MISCREG_PAR)
1939  .banked();
1940  InitReg(MISCREG_PAR_NS)
1941  .bankedChild()
1942  .privSecure(!aarch32EL3)
1943  .nonSecure().exceptUserMode();
1944  InitReg(MISCREG_PAR_S)
1945  .bankedChild()
1946  .secure().exceptUserMode();
1947  InitReg(MISCREG_ICIALLU)
1948  .writes(1).exceptUserMode();
1949  InitReg(MISCREG_ICIMVAU)
1950  .unimplemented()
1951  .warnNotFail()
1952  .writes(1).exceptUserMode();
1953  InitReg(MISCREG_CP15ISB)
1954  .writes(1);
1955  InitReg(MISCREG_BPIALL)
1956  .unimplemented()
1957  .warnNotFail()
1958  .writes(1).exceptUserMode();
1959  InitReg(MISCREG_BPIMVA)
1960  .unimplemented()
1961  .warnNotFail()
1962  .writes(1).exceptUserMode();
1963  InitReg(MISCREG_DCIMVAC)
1964  .unimplemented()
1965  .warnNotFail()
1966  .writes(1).exceptUserMode();
1967  InitReg(MISCREG_DCISW)
1968  .unimplemented()
1969  .warnNotFail()
1970  .writes(1).exceptUserMode();
1971  InitReg(MISCREG_ATS1CPR)
1972  .writes(1).exceptUserMode();
1973  InitReg(MISCREG_ATS1CPW)
1974  .writes(1).exceptUserMode();
1975  InitReg(MISCREG_ATS1CUR)
1976  .writes(1).exceptUserMode();
1977  InitReg(MISCREG_ATS1CUW)
1978  .writes(1).exceptUserMode();
1979  InitReg(MISCREG_ATS12NSOPR)
1980  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
1981  InitReg(MISCREG_ATS12NSOPW)
1982  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
1983  InitReg(MISCREG_ATS12NSOUR)
1984  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
1985  InitReg(MISCREG_ATS12NSOUW)
1986  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
1987  InitReg(MISCREG_DCCMVAC)
1988  .writes(1).exceptUserMode();
1989  InitReg(MISCREG_DCCSW)
1990  .unimplemented()
1991  .warnNotFail()
1992  .writes(1).exceptUserMode();
1993  InitReg(MISCREG_CP15DSB)
1994  .writes(1);
1995  InitReg(MISCREG_CP15DMB)
1996  .writes(1);
1997  InitReg(MISCREG_DCCMVAU)
1998  .unimplemented()
1999  .warnNotFail()
2000  .writes(1).exceptUserMode();
2001  InitReg(MISCREG_DCCIMVAC)
2002  .unimplemented()
2003  .warnNotFail()
2004  .writes(1).exceptUserMode();
2005  InitReg(MISCREG_DCCISW)
2006  .unimplemented()
2007  .warnNotFail()
2008  .writes(1).exceptUserMode();
2009  InitReg(MISCREG_ATS1HR)
2010  .monNonSecureWrite().hypWrite();
2011  InitReg(MISCREG_ATS1HW)
2012  .monNonSecureWrite().hypWrite();
2013  InitReg(MISCREG_TLBIALLIS)
2014  .writes(1).exceptUserMode();
2015  InitReg(MISCREG_TLBIMVAIS)
2016  .writes(1).exceptUserMode();
2017  InitReg(MISCREG_TLBIASIDIS)
2018  .writes(1).exceptUserMode();
2019  InitReg(MISCREG_TLBIMVAAIS)
2020  .writes(1).exceptUserMode();
2021  InitReg(MISCREG_TLBIMVALIS)
2022  .writes(1).exceptUserMode();
2023  InitReg(MISCREG_TLBIMVAALIS)
2024  .writes(1).exceptUserMode();
2025  InitReg(MISCREG_ITLBIALL)
2026  .writes(1).exceptUserMode();
2027  InitReg(MISCREG_ITLBIMVA)
2028  .writes(1).exceptUserMode();
2029  InitReg(MISCREG_ITLBIASID)
2030  .writes(1).exceptUserMode();
2031  InitReg(MISCREG_DTLBIALL)
2032  .writes(1).exceptUserMode();
2033  InitReg(MISCREG_DTLBIMVA)
2034  .writes(1).exceptUserMode();
2035  InitReg(MISCREG_DTLBIASID)
2036  .writes(1).exceptUserMode();
2037  InitReg(MISCREG_TLBIALL)
2038  .writes(1).exceptUserMode();
2039  InitReg(MISCREG_TLBIMVA)
2040  .writes(1).exceptUserMode();
2041  InitReg(MISCREG_TLBIASID)
2042  .writes(1).exceptUserMode();
2043  InitReg(MISCREG_TLBIMVAA)
2044  .writes(1).exceptUserMode();
2045  InitReg(MISCREG_TLBIMVAL)
2046  .writes(1).exceptUserMode();
2047  InitReg(MISCREG_TLBIMVAAL)
2048  .writes(1).exceptUserMode();
2049  InitReg(MISCREG_TLBIIPAS2IS)
2050  .monNonSecureWrite().hypWrite();
2051  InitReg(MISCREG_TLBIIPAS2LIS)
2052  .monNonSecureWrite().hypWrite();
2053  InitReg(MISCREG_TLBIALLHIS)
2054  .monNonSecureWrite().hypWrite();
2055  InitReg(MISCREG_TLBIMVAHIS)
2056  .monNonSecureWrite().hypWrite();
2057  InitReg(MISCREG_TLBIALLNSNHIS)
2058  .monNonSecureWrite().hypWrite();
2059  InitReg(MISCREG_TLBIMVALHIS)
2060  .monNonSecureWrite().hypWrite();
2061  InitReg(MISCREG_TLBIIPAS2)
2062  .monNonSecureWrite().hypWrite();
2063  InitReg(MISCREG_TLBIIPAS2L)
2064  .monNonSecureWrite().hypWrite();
2065  InitReg(MISCREG_TLBIALLH)
2066  .monNonSecureWrite().hypWrite();
2067  InitReg(MISCREG_TLBIMVAH)
2068  .monNonSecureWrite().hypWrite();
2069  InitReg(MISCREG_TLBIALLNSNH)
2070  .monNonSecureWrite().hypWrite();
2071  InitReg(MISCREG_TLBIMVALH)
2072  .monNonSecureWrite().hypWrite();
2073  InitReg(MISCREG_PMCR)
2074  .allPrivileges();
2075  InitReg(MISCREG_PMCNTENSET)
2076  .allPrivileges();
2077  InitReg(MISCREG_PMCNTENCLR)
2078  .allPrivileges();
2079  InitReg(MISCREG_PMOVSR)
2080  .allPrivileges();
2081  InitReg(MISCREG_PMSWINC)
2082  .allPrivileges();
2083  InitReg(MISCREG_PMSELR)
2084  .allPrivileges();
2085  InitReg(MISCREG_PMCEID0)
2086  .allPrivileges();
2087  InitReg(MISCREG_PMCEID1)
2088  .allPrivileges();
2089  InitReg(MISCREG_PMCCNTR)
2090  .allPrivileges();
2091  InitReg(MISCREG_PMXEVTYPER)
2092  .allPrivileges();
2093  InitReg(MISCREG_PMCCFILTR)
2094  .allPrivileges();
2095  InitReg(MISCREG_PMXEVCNTR)
2096  .allPrivileges();
2097  InitReg(MISCREG_PMUSERENR)
2098  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
2099  InitReg(MISCREG_PMINTENSET)
2100  .allPrivileges().exceptUserMode();
2101  InitReg(MISCREG_PMINTENCLR)
2102  .allPrivileges().exceptUserMode();
2103  InitReg(MISCREG_PMOVSSET)
2104  .unimplemented()
2105  .allPrivileges();
2106  InitReg(MISCREG_L2CTLR)
2107  .allPrivileges().exceptUserMode();
2108  InitReg(MISCREG_L2ECTLR)
2109  .unimplemented()
2110  .allPrivileges().exceptUserMode();
2111  InitReg(MISCREG_PRRR)
2112  .banked();
2113  InitReg(MISCREG_PRRR_NS)
2114  .bankedChild()
2115  .privSecure(!aarch32EL3)
2116  .nonSecure().exceptUserMode();
2117  InitReg(MISCREG_PRRR_S)
2118  .bankedChild()
2119  .secure().exceptUserMode();
2120  InitReg(MISCREG_MAIR0)
2121  .banked();
2122  InitReg(MISCREG_MAIR0_NS)
2123  .bankedChild()
2124  .privSecure(!aarch32EL3)
2125  .nonSecure().exceptUserMode();
2126  InitReg(MISCREG_MAIR0_S)
2127  .bankedChild()
2128  .secure().exceptUserMode();
2129  InitReg(MISCREG_NMRR)
2130  .banked();
2131  InitReg(MISCREG_NMRR_NS)
2132  .bankedChild()
2133  .privSecure(!aarch32EL3)
2134  .nonSecure().exceptUserMode();
2135  InitReg(MISCREG_NMRR_S)
2136  .bankedChild()
2137  .secure().exceptUserMode();
2138  InitReg(MISCREG_MAIR1)
2139  .banked();
2140  InitReg(MISCREG_MAIR1_NS)
2141  .bankedChild()
2142  .privSecure(!aarch32EL3)
2143  .nonSecure().exceptUserMode();
2144  InitReg(MISCREG_MAIR1_S)
2145  .bankedChild()
2146  .secure().exceptUserMode();
2147  InitReg(MISCREG_AMAIR0)
2148  .banked();
2149  InitReg(MISCREG_AMAIR0_NS)
2150  .bankedChild()
2151  .privSecure(!aarch32EL3)
2152  .nonSecure().exceptUserMode();
2153  InitReg(MISCREG_AMAIR0_S)
2154  .bankedChild()
2155  .secure().exceptUserMode();
2156  InitReg(MISCREG_AMAIR1)
2157  .banked();
2158  InitReg(MISCREG_AMAIR1_NS)
2159  .bankedChild()
2160  .privSecure(!aarch32EL3)
2161  .nonSecure().exceptUserMode();
2162  InitReg(MISCREG_AMAIR1_S)
2163  .bankedChild()
2164  .secure().exceptUserMode();
2165  InitReg(MISCREG_HMAIR0)
2166  .hyp().monNonSecure();
2167  InitReg(MISCREG_HMAIR1)
2168  .hyp().monNonSecure();
2169  InitReg(MISCREG_HAMAIR0)
2170  .unimplemented()
2171  .warnNotFail()
2172  .hyp().monNonSecure();
2173  InitReg(MISCREG_HAMAIR1)
2174  .unimplemented()
2175  .warnNotFail()
2176  .hyp().monNonSecure();
2177  InitReg(MISCREG_VBAR)
2178  .banked();
2179  InitReg(MISCREG_VBAR_NS)
2180  .bankedChild()
2181  .privSecure(!aarch32EL3)
2182  .nonSecure().exceptUserMode();
2183  InitReg(MISCREG_VBAR_S)
2184  .bankedChild()
2185  .secure().exceptUserMode();
2186  InitReg(MISCREG_MVBAR)
2187  .mon().secure()
2188  .hypRead(FullSystem && system->highestEL() == EL2)
2189  .privRead(FullSystem && system->highestEL() == EL1)
2190  .exceptUserMode();
2191  InitReg(MISCREG_RMR)
2192  .unimplemented()
2193  .mon().secure().exceptUserMode();
2194  InitReg(MISCREG_ISR)
2195  .allPrivileges().exceptUserMode().writes(0);
2196  InitReg(MISCREG_HVBAR)
2197  .hyp().monNonSecure()
2198  .res0(0x1f);
2199  InitReg(MISCREG_FCSEIDR)
2200  .unimplemented()
2201  .warnNotFail()
2202  .allPrivileges().exceptUserMode();
2203  InitReg(MISCREG_CONTEXTIDR)
2204  .banked();
2205  InitReg(MISCREG_CONTEXTIDR_NS)
2206  .bankedChild()
2207  .privSecure(!aarch32EL3)
2208  .nonSecure().exceptUserMode();
2209  InitReg(MISCREG_CONTEXTIDR_S)
2210  .bankedChild()
2211  .secure().exceptUserMode();
2212  InitReg(MISCREG_TPIDRURW)
2213  .banked();
2214  InitReg(MISCREG_TPIDRURW_NS)
2215  .bankedChild()
2216  .allPrivileges()
2217  .privSecure(!aarch32EL3)
2218  .monSecure(0);
2219  InitReg(MISCREG_TPIDRURW_S)
2220  .bankedChild()
2221  .secure();
2222  InitReg(MISCREG_TPIDRURO)
2223  .banked();
2224  InitReg(MISCREG_TPIDRURO_NS)
2225  .bankedChild()
2226  .allPrivileges()
2227  .userNonSecureWrite(0).userSecureRead(1)
2228  .privSecure(!aarch32EL3)
2229  .monSecure(0);
2230  InitReg(MISCREG_TPIDRURO_S)
2231  .bankedChild()
2232  .secure().userSecureWrite(0);
2233  InitReg(MISCREG_TPIDRPRW)
2234  .banked();
2235  InitReg(MISCREG_TPIDRPRW_NS)
2236  .bankedChild()
2237  .nonSecure().exceptUserMode()
2238  .privSecure(!aarch32EL3);
2239  InitReg(MISCREG_TPIDRPRW_S)
2240  .bankedChild()
2241  .secure().exceptUserMode();
2242  InitReg(MISCREG_HTPIDR)
2243  .hyp().monNonSecure();
2244  // BEGIN Generic Timer (AArch32)
2245  InitReg(MISCREG_CNTFRQ)
2246  .reads(1)
2247  .highest(system)
2248  .privSecureWrite(aarch32EL3);
2249  InitReg(MISCREG_CNTPCT)
2250  .unverifiable()
2251  .reads(1);
2252  InitReg(MISCREG_CNTVCT)
2253  .unverifiable()
2254  .reads(1);
2255  InitReg(MISCREG_CNTP_CTL)
2256  .banked();
2257  InitReg(MISCREG_CNTP_CTL_NS)
2258  .bankedChild()
2259  .nonSecure()
2260  .privSecure(!aarch32EL3)
2261  .userSecureRead(!aarch32EL3)
2262  .userSecureWrite(!aarch32EL3)
2263  .res0(0xfffffff8);
2264  InitReg(MISCREG_CNTP_CTL_S)
2265  .bankedChild()
2266  .secure()
2267  .privSecure(aarch32EL3)
2268  .res0(0xfffffff8);
2269  InitReg(MISCREG_CNTP_CVAL)
2270  .banked();
2271  InitReg(MISCREG_CNTP_CVAL_NS)
2272  .bankedChild()
2273  .nonSecure()
2274  .privSecure(!aarch32EL3)
2275  .userSecureRead(!aarch32EL3)
2276  .userSecureWrite(!aarch32EL3);
2277  InitReg(MISCREG_CNTP_CVAL_S)
2278  .bankedChild()
2279  .secure()
2280  .privSecure(aarch32EL3);
2281  InitReg(MISCREG_CNTP_TVAL)
2282  .banked();
2283  InitReg(MISCREG_CNTP_TVAL_NS)
2284  .bankedChild()
2285  .nonSecure()
2286  .privSecure(!aarch32EL3)
2287  .userSecureRead(!aarch32EL3)
2288  .userSecureWrite(!aarch32EL3);
2289  InitReg(MISCREG_CNTP_TVAL_S)
2290  .bankedChild()
2291  .secure()
2292  .privSecure(aarch32EL3);
2293  InitReg(MISCREG_CNTV_CTL)
2294  .allPrivileges()
2295  .res0(0xfffffff8);
2296  InitReg(MISCREG_CNTV_CVAL)
2297  .allPrivileges();
2298  InitReg(MISCREG_CNTV_TVAL)
2299  .allPrivileges();
2300  InitReg(MISCREG_CNTKCTL)
2301  .allPrivileges()
2302  .exceptUserMode()
2303  .res0(0xfffdfc00);
2304  InitReg(MISCREG_CNTHCTL)
2305  .monNonSecure()
2306  .hyp()
2307  .res0(0xfffdff00);
2308  InitReg(MISCREG_CNTHP_CTL)
2309  .monNonSecure()
2310  .hyp()
2311  .res0(0xfffffff8);
2312  InitReg(MISCREG_CNTHP_CVAL)
2313  .monNonSecure()
2314  .hyp();
2315  InitReg(MISCREG_CNTHP_TVAL)
2316  .monNonSecure()
2317  .hyp();
2318  InitReg(MISCREG_CNTVOFF)
2319  .monNonSecure()
2320  .hyp();
2321  // END Generic Timer (AArch32)
2322  InitReg(MISCREG_IL1DATA0)
2323  .unimplemented()
2324  .allPrivileges().exceptUserMode();
2325  InitReg(MISCREG_IL1DATA1)
2326  .unimplemented()
2327  .allPrivileges().exceptUserMode();
2328  InitReg(MISCREG_IL1DATA2)
2329  .unimplemented()
2330  .allPrivileges().exceptUserMode();
2331  InitReg(MISCREG_IL1DATA3)
2332  .unimplemented()
2333  .allPrivileges().exceptUserMode();
2334  InitReg(MISCREG_DL1DATA0)
2335  .unimplemented()
2336  .allPrivileges().exceptUserMode();
2337  InitReg(MISCREG_DL1DATA1)
2338  .unimplemented()
2339  .allPrivileges().exceptUserMode();
2340  InitReg(MISCREG_DL1DATA2)
2341  .unimplemented()
2342  .allPrivileges().exceptUserMode();
2343  InitReg(MISCREG_DL1DATA3)
2344  .unimplemented()
2345  .allPrivileges().exceptUserMode();
2346  InitReg(MISCREG_DL1DATA4)
2347  .unimplemented()
2348  .allPrivileges().exceptUserMode();
2349  InitReg(MISCREG_RAMINDEX)
2350  .unimplemented()
2351  .writes(1).exceptUserMode();
2352  InitReg(MISCREG_L2ACTLR)
2353  .unimplemented()
2354  .allPrivileges().exceptUserMode();
2355  InitReg(MISCREG_CBAR)
2356  .unimplemented()
2357  .allPrivileges().exceptUserMode().writes(0);
2358  InitReg(MISCREG_HTTBR)
2359  .hyp().monNonSecure();
2360  InitReg(MISCREG_VTTBR)
2361  .hyp().monNonSecure();
2362  InitReg(MISCREG_CPUMERRSR)
2363  .unimplemented()
2364  .allPrivileges().exceptUserMode();
2365  InitReg(MISCREG_L2MERRSR)
2366  .unimplemented()
2367  .warnNotFail()
2368  .allPrivileges().exceptUserMode();
2369 
2370  // AArch64 registers (Op0=2);
2371  InitReg(MISCREG_MDCCINT_EL1)
2372  .allPrivileges();
2373  InitReg(MISCREG_OSDTRRX_EL1)
2374  .allPrivileges()
2375  .mapsTo(MISCREG_DBGDTRRXext);
2376  InitReg(MISCREG_MDSCR_EL1)
2377  .allPrivileges()
2378  .mapsTo(MISCREG_DBGDSCRext);
2379  InitReg(MISCREG_OSDTRTX_EL1)
2380  .allPrivileges()
2381  .mapsTo(MISCREG_DBGDTRTXext);
2382  InitReg(MISCREG_OSECCR_EL1)
2383  .allPrivileges()
2384  .mapsTo(MISCREG_DBGOSECCR);
2385  InitReg(MISCREG_DBGBVR0_EL1)
2386  .allPrivileges().exceptUserMode()
2387  .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
2388  InitReg(MISCREG_DBGBVR1_EL1)
2389  .allPrivileges().exceptUserMode()
2390  .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
2391  InitReg(MISCREG_DBGBVR2_EL1)
2392  .allPrivileges().exceptUserMode()
2393  .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
2394  InitReg(MISCREG_DBGBVR3_EL1)
2395  .allPrivileges().exceptUserMode()
2396  .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
2397  InitReg(MISCREG_DBGBVR4_EL1)
2398  .allPrivileges().exceptUserMode()
2399  .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
2400  InitReg(MISCREG_DBGBVR5_EL1)
2401  .allPrivileges().exceptUserMode()
2402  .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
2403  InitReg(MISCREG_DBGBVR6_EL1)
2404  .allPrivileges().exceptUserMode()
2405  .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
2406  InitReg(MISCREG_DBGBVR7_EL1)
2407  .allPrivileges().exceptUserMode()
2408  .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
2409  InitReg(MISCREG_DBGBVR8_EL1)
2410  .allPrivileges().exceptUserMode()
2411  .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
2412  InitReg(MISCREG_DBGBVR9_EL1)
2413  .allPrivileges().exceptUserMode()
2414  .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
2415  InitReg(MISCREG_DBGBVR10_EL1)
2416  .allPrivileges().exceptUserMode()
2417  .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
2418  InitReg(MISCREG_DBGBVR11_EL1)
2419  .allPrivileges().exceptUserMode()
2420  .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
2421  InitReg(MISCREG_DBGBVR12_EL1)
2422  .allPrivileges().exceptUserMode()
2423  .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
2424  InitReg(MISCREG_DBGBVR13_EL1)
2425  .allPrivileges().exceptUserMode()
2426  .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
2427  InitReg(MISCREG_DBGBVR14_EL1)
2428  .allPrivileges().exceptUserMode()
2429  .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
2430  InitReg(MISCREG_DBGBVR15_EL1)
2431  .allPrivileges().exceptUserMode()
2432  .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
2433  InitReg(MISCREG_DBGBCR0_EL1)
2434  .allPrivileges().exceptUserMode()
2435  .mapsTo(MISCREG_DBGBCR0);
2436  InitReg(MISCREG_DBGBCR1_EL1)
2437  .allPrivileges().exceptUserMode()
2438  .mapsTo(MISCREG_DBGBCR1);
2439  InitReg(MISCREG_DBGBCR2_EL1)
2440  .allPrivileges().exceptUserMode()
2441  .mapsTo(MISCREG_DBGBCR2);
2442  InitReg(MISCREG_DBGBCR3_EL1)
2443  .allPrivileges().exceptUserMode()
2444  .mapsTo(MISCREG_DBGBCR3);
2445  InitReg(MISCREG_DBGBCR4_EL1)
2446  .allPrivileges().exceptUserMode()
2447  .mapsTo(MISCREG_DBGBCR4);
2448  InitReg(MISCREG_DBGBCR5_EL1)
2449  .allPrivileges().exceptUserMode()
2450  .mapsTo(MISCREG_DBGBCR5);
2451  InitReg(MISCREG_DBGBCR6_EL1)
2452  .allPrivileges().exceptUserMode()
2453  .mapsTo(MISCREG_DBGBCR6);
2454  InitReg(MISCREG_DBGBCR7_EL1)
2455  .allPrivileges().exceptUserMode()
2456  .mapsTo(MISCREG_DBGBCR7);
2457  InitReg(MISCREG_DBGBCR8_EL1)
2458  .allPrivileges().exceptUserMode()
2459  .mapsTo(MISCREG_DBGBCR8);
2460  InitReg(MISCREG_DBGBCR9_EL1)
2461  .allPrivileges().exceptUserMode()
2462  .mapsTo(MISCREG_DBGBCR9);
2463  InitReg(MISCREG_DBGBCR10_EL1)
2464  .allPrivileges().exceptUserMode()
2465  .mapsTo(MISCREG_DBGBCR10);
2466  InitReg(MISCREG_DBGBCR11_EL1)
2467  .allPrivileges().exceptUserMode()
2468  .mapsTo(MISCREG_DBGBCR11);
2469  InitReg(MISCREG_DBGBCR12_EL1)
2470  .allPrivileges().exceptUserMode()
2471  .mapsTo(MISCREG_DBGBCR12);
2472  InitReg(MISCREG_DBGBCR13_EL1)
2473  .allPrivileges().exceptUserMode()
2474  .mapsTo(MISCREG_DBGBCR13);
2475  InitReg(MISCREG_DBGBCR14_EL1)
2476  .allPrivileges().exceptUserMode()
2477  .mapsTo(MISCREG_DBGBCR14);
2478  InitReg(MISCREG_DBGBCR15_EL1)
2479  .allPrivileges().exceptUserMode()
2480  .mapsTo(MISCREG_DBGBCR15);
2481  InitReg(MISCREG_DBGWVR0_EL1)
2482  .allPrivileges().exceptUserMode()
2483  .mapsTo(MISCREG_DBGWVR0);
2484  InitReg(MISCREG_DBGWVR1_EL1)
2485  .allPrivileges().exceptUserMode()
2486  .mapsTo(MISCREG_DBGWVR1);
2487  InitReg(MISCREG_DBGWVR2_EL1)
2488  .allPrivileges().exceptUserMode()
2489  .mapsTo(MISCREG_DBGWVR2);
2490  InitReg(MISCREG_DBGWVR3_EL1)
2491  .allPrivileges().exceptUserMode()
2492  .mapsTo(MISCREG_DBGWVR3);
2493  InitReg(MISCREG_DBGWVR4_EL1)
2494  .allPrivileges().exceptUserMode()
2495  .mapsTo(MISCREG_DBGWVR4);
2496  InitReg(MISCREG_DBGWVR5_EL1)
2497  .allPrivileges().exceptUserMode()
2498  .mapsTo(MISCREG_DBGWVR5);
2499  InitReg(MISCREG_DBGWVR6_EL1)
2500  .allPrivileges().exceptUserMode()
2501  .mapsTo(MISCREG_DBGWVR6);
2502  InitReg(MISCREG_DBGWVR7_EL1)
2503  .allPrivileges().exceptUserMode()
2504  .mapsTo(MISCREG_DBGWVR7);
2505  InitReg(MISCREG_DBGWVR8_EL1)
2506  .allPrivileges().exceptUserMode()
2507  .mapsTo(MISCREG_DBGWVR8);
2508  InitReg(MISCREG_DBGWVR9_EL1)
2509  .allPrivileges().exceptUserMode()
2510  .mapsTo(MISCREG_DBGWVR9);
2511  InitReg(MISCREG_DBGWVR10_EL1)
2512  .allPrivileges().exceptUserMode()
2513  .mapsTo(MISCREG_DBGWVR10);
2514  InitReg(MISCREG_DBGWVR11_EL1)
2515  .allPrivileges().exceptUserMode()
2516  .mapsTo(MISCREG_DBGWVR11);
2517  InitReg(MISCREG_DBGWVR12_EL1)
2518  .allPrivileges().exceptUserMode()
2519  .mapsTo(MISCREG_DBGWVR12);
2520  InitReg(MISCREG_DBGWVR13_EL1)
2521  .allPrivileges().exceptUserMode()
2522  .mapsTo(MISCREG_DBGWVR13);
2523  InitReg(MISCREG_DBGWVR14_EL1)
2524  .allPrivileges().exceptUserMode()
2525  .mapsTo(MISCREG_DBGWVR14);
2526  InitReg(MISCREG_DBGWVR15_EL1)
2527  .allPrivileges().exceptUserMode()
2528  .mapsTo(MISCREG_DBGWVR15);
2529  InitReg(MISCREG_DBGWCR0_EL1)
2530  .allPrivileges().exceptUserMode()
2531  .mapsTo(MISCREG_DBGWCR0);
2532  InitReg(MISCREG_DBGWCR1_EL1)
2533  .allPrivileges().exceptUserMode()
2534  .mapsTo(MISCREG_DBGWCR1);
2535  InitReg(MISCREG_DBGWCR2_EL1)
2536  .allPrivileges().exceptUserMode()
2537  .mapsTo(MISCREG_DBGWCR2);
2538  InitReg(MISCREG_DBGWCR3_EL1)
2539  .allPrivileges().exceptUserMode()
2540  .mapsTo(MISCREG_DBGWCR3);
2541  InitReg(MISCREG_DBGWCR4_EL1)
2542  .allPrivileges().exceptUserMode()
2543  .mapsTo(MISCREG_DBGWCR4);
2544  InitReg(MISCREG_DBGWCR5_EL1)
2545  .allPrivileges().exceptUserMode()
2546  .mapsTo(MISCREG_DBGWCR5);
2547  InitReg(MISCREG_DBGWCR6_EL1)
2548  .allPrivileges().exceptUserMode()
2549  .mapsTo(MISCREG_DBGWCR6);
2550  InitReg(MISCREG_DBGWCR7_EL1)
2551  .allPrivileges().exceptUserMode()
2552  .mapsTo(MISCREG_DBGWCR7);
2553  InitReg(MISCREG_DBGWCR8_EL1)
2554  .allPrivileges().exceptUserMode()
2555  .mapsTo(MISCREG_DBGWCR8);
2556  InitReg(MISCREG_DBGWCR9_EL1)
2557  .allPrivileges().exceptUserMode()
2558  .mapsTo(MISCREG_DBGWCR9);
2559  InitReg(MISCREG_DBGWCR10_EL1)
2560  .allPrivileges().exceptUserMode()
2561  .mapsTo(MISCREG_DBGWCR10);
2562  InitReg(MISCREG_DBGWCR11_EL1)
2563  .allPrivileges().exceptUserMode()
2564  .mapsTo(MISCREG_DBGWCR11);
2565  InitReg(MISCREG_DBGWCR12_EL1)
2566  .allPrivileges().exceptUserMode()
2567  .mapsTo(MISCREG_DBGWCR12);
2568  InitReg(MISCREG_DBGWCR13_EL1)
2569  .allPrivileges().exceptUserMode()
2570  .mapsTo(MISCREG_DBGWCR13);
2571  InitReg(MISCREG_DBGWCR14_EL1)
2572  .allPrivileges().exceptUserMode()
2573  .mapsTo(MISCREG_DBGWCR14);
2574  InitReg(MISCREG_DBGWCR15_EL1)
2575  .allPrivileges().exceptUserMode()
2576  .mapsTo(MISCREG_DBGWCR15);
2577  InitReg(MISCREG_MDCCSR_EL0)
2578  .allPrivileges().writes(0)
2579  //monSecureWrite(0).monNonSecureWrite(0)
2580  .mapsTo(MISCREG_DBGDSCRint);
2581  InitReg(MISCREG_MDDTR_EL0)
2582  .allPrivileges();
2583  InitReg(MISCREG_MDDTRTX_EL0)
2584  .allPrivileges();
2585  InitReg(MISCREG_MDDTRRX_EL0)
2586  .allPrivileges();
2587  InitReg(MISCREG_DBGVCR32_EL2)
2588  .hyp().mon()
2589  .mapsTo(MISCREG_DBGVCR);
2590  InitReg(MISCREG_MDRAR_EL1)
2591  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
2592  .mapsTo(MISCREG_DBGDRAR);
2593  InitReg(MISCREG_OSLAR_EL1)
2594  .allPrivileges().monSecureRead(0).monNonSecureRead(0)
2595  .mapsTo(MISCREG_DBGOSLAR);
2596  InitReg(MISCREG_OSLSR_EL1)
2597  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
2598  .mapsTo(MISCREG_DBGOSLSR);
2599  InitReg(MISCREG_OSDLR_EL1)
2600  .allPrivileges()
2601  .mapsTo(MISCREG_DBGOSDLR);
2602  InitReg(MISCREG_DBGPRCR_EL1)
2603  .allPrivileges()
2604  .mapsTo(MISCREG_DBGPRCR);
2605  InitReg(MISCREG_DBGCLAIMSET_EL1)
2606  .allPrivileges()
2607  .mapsTo(MISCREG_DBGCLAIMSET);
2608  InitReg(MISCREG_DBGCLAIMCLR_EL1)
2609  .allPrivileges()
2610  .mapsTo(MISCREG_DBGCLAIMCLR);
2611  InitReg(MISCREG_DBGAUTHSTATUS_EL1)
2612  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
2613  .mapsTo(MISCREG_DBGAUTHSTATUS);
2614  InitReg(MISCREG_TEECR32_EL1);
2615  InitReg(MISCREG_TEEHBR32_EL1);
2616 
2617  // AArch64 registers (Op0=1,3);
2618  InitReg(MISCREG_MIDR_EL1)
2619  .allPrivileges().exceptUserMode().writes(0);
2620  InitReg(MISCREG_MPIDR_EL1)
2621  .allPrivileges().exceptUserMode().writes(0);
2622  InitReg(MISCREG_REVIDR_EL1)
2623  .allPrivileges().exceptUserMode().writes(0);
2624  InitReg(MISCREG_ID_PFR0_EL1)
2625  .allPrivileges().exceptUserMode().writes(0)
2626  .mapsTo(MISCREG_ID_PFR0);
2627  InitReg(MISCREG_ID_PFR1_EL1)
2628  .allPrivileges().exceptUserMode().writes(0)
2629  .mapsTo(MISCREG_ID_PFR1);
2630  InitReg(MISCREG_ID_DFR0_EL1)
2631  .allPrivileges().exceptUserMode().writes(0)
2632  .mapsTo(MISCREG_ID_DFR0);
2633  InitReg(MISCREG_ID_AFR0_EL1)
2634  .allPrivileges().exceptUserMode().writes(0)
2635  .mapsTo(MISCREG_ID_AFR0);
2636  InitReg(MISCREG_ID_MMFR0_EL1)
2637  .allPrivileges().exceptUserMode().writes(0)
2638  .mapsTo(MISCREG_ID_MMFR0);
2639  InitReg(MISCREG_ID_MMFR1_EL1)
2640  .allPrivileges().exceptUserMode().writes(0)
2641  .mapsTo(MISCREG_ID_MMFR1);
2642  InitReg(MISCREG_ID_MMFR2_EL1)
2643  .allPrivileges().exceptUserMode().writes(0)
2644  .mapsTo(MISCREG_ID_MMFR2);
2645  InitReg(MISCREG_ID_MMFR3_EL1)
2646  .allPrivileges().exceptUserMode().writes(0)
2647  .mapsTo(MISCREG_ID_MMFR3);
2648  InitReg(MISCREG_ID_MMFR4_EL1)
2649  .allPrivileges().exceptUserMode().writes(0)
2650  .mapsTo(MISCREG_ID_MMFR4);
2651  InitReg(MISCREG_ID_ISAR0_EL1)
2652  .allPrivileges().exceptUserMode().writes(0)
2653  .mapsTo(MISCREG_ID_ISAR0);
2654  InitReg(MISCREG_ID_ISAR1_EL1)
2655  .allPrivileges().exceptUserMode().writes(0)
2656  .mapsTo(MISCREG_ID_ISAR1);
2657  InitReg(MISCREG_ID_ISAR2_EL1)
2658  .allPrivileges().exceptUserMode().writes(0)
2659  .mapsTo(MISCREG_ID_ISAR2);
2660  InitReg(MISCREG_ID_ISAR3_EL1)
2661  .allPrivileges().exceptUserMode().writes(0)
2662  .mapsTo(MISCREG_ID_ISAR3);
2663  InitReg(MISCREG_ID_ISAR4_EL1)
2664  .allPrivileges().exceptUserMode().writes(0)
2665  .mapsTo(MISCREG_ID_ISAR4);
2666  InitReg(MISCREG_ID_ISAR5_EL1)
2667  .allPrivileges().exceptUserMode().writes(0)
2668  .mapsTo(MISCREG_ID_ISAR5);
2669  InitReg(MISCREG_ID_ISAR6_EL1)
2670  .allPrivileges().exceptUserMode().writes(0)
2671  .mapsTo(MISCREG_ID_ISAR6);
2672  InitReg(MISCREG_MVFR0_EL1)
2673  .allPrivileges().exceptUserMode().writes(0);
2674  InitReg(MISCREG_MVFR1_EL1)
2675  .allPrivileges().exceptUserMode().writes(0);
2676  InitReg(MISCREG_MVFR2_EL1)
2677  .allPrivileges().exceptUserMode().writes(0);
2678  InitReg(MISCREG_ID_AA64PFR0_EL1)
2679  .allPrivileges().exceptUserMode().writes(0);
2680  InitReg(MISCREG_ID_AA64PFR1_EL1)
2681  .allPrivileges().exceptUserMode().writes(0);
2682  InitReg(MISCREG_ID_AA64DFR0_EL1)
2683  .allPrivileges().exceptUserMode().writes(0);
2684  InitReg(MISCREG_ID_AA64DFR1_EL1)
2685  .allPrivileges().exceptUserMode().writes(0);
2686  InitReg(MISCREG_ID_AA64AFR0_EL1)
2687  .allPrivileges().exceptUserMode().writes(0);
2688  InitReg(MISCREG_ID_AA64AFR1_EL1)
2689  .allPrivileges().exceptUserMode().writes(0);
2690  InitReg(MISCREG_ID_AA64ISAR0_EL1)
2691  .allPrivileges().exceptUserMode().writes(0);
2692  InitReg(MISCREG_ID_AA64ISAR1_EL1)
2693  .allPrivileges().exceptUserMode().writes(0);
2694  InitReg(MISCREG_ID_AA64MMFR0_EL1)
2695  .allPrivileges().exceptUserMode().writes(0);
2696  InitReg(MISCREG_ID_AA64MMFR1_EL1)
2697  .allPrivileges().exceptUserMode().writes(0);
2698  InitReg(MISCREG_ID_AA64MMFR2_EL1)
2699  .allPrivileges().exceptUserMode().writes(0);
2700 
2701  InitReg(MISCREG_APDAKeyHi_EL1)
2702  .allPrivileges().exceptUserMode();
2703  InitReg(MISCREG_APDAKeyLo_EL1)
2704  .allPrivileges().exceptUserMode();
2705  InitReg(MISCREG_APDBKeyHi_EL1)
2706  .allPrivileges().exceptUserMode();
2707  InitReg(MISCREG_APDBKeyLo_EL1)
2708  .allPrivileges().exceptUserMode();
2709  InitReg(MISCREG_APGAKeyHi_EL1)
2710  .allPrivileges().exceptUserMode();
2711  InitReg(MISCREG_APGAKeyLo_EL1)
2712  .allPrivileges().exceptUserMode();
2713  InitReg(MISCREG_APIAKeyHi_EL1)
2714  .allPrivileges().exceptUserMode();
2715  InitReg(MISCREG_APIAKeyLo_EL1)
2716  .allPrivileges().exceptUserMode();
2717  InitReg(MISCREG_APIBKeyHi_EL1)
2718  .allPrivileges().exceptUserMode();
2719  InitReg(MISCREG_APIBKeyLo_EL1)
2720  .allPrivileges().exceptUserMode();
2721 
2722  InitReg(MISCREG_CCSIDR_EL1)
2723  .allPrivileges().exceptUserMode().writes(0);
2724  InitReg(MISCREG_CLIDR_EL1)
2725  .allPrivileges().exceptUserMode().writes(0);
2726  InitReg(MISCREG_AIDR_EL1)
2727  .allPrivileges().exceptUserMode().writes(0);
2728  InitReg(MISCREG_CSSELR_EL1)
2729  .allPrivileges().exceptUserMode()
2730  .mapsTo(MISCREG_CSSELR_NS);
2731  InitReg(MISCREG_CTR_EL0)
2732  .reads(1);
2733  InitReg(MISCREG_DCZID_EL0)
2734  .reads(1);
2735  InitReg(MISCREG_VPIDR_EL2)
2736  .hyp().mon()
2737  .mapsTo(MISCREG_VPIDR);
2738  InitReg(MISCREG_VMPIDR_EL2)
2739  .hyp().mon()
2740  .mapsTo(MISCREG_VMPIDR);
2741  InitReg(MISCREG_SCTLR_EL1)
2742  .allPrivileges().exceptUserMode()
2743  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
2744  | (IESB ? 0 : 0x200000)
2745  | (EnDA ? 0 : 0x8000000)
2746  | (EnIB ? 0 : 0x40000000)
2747  | (EnIA ? 0 : 0x80000000))
2748  .res1(0x500800 | (SPAN ? 0 : 0x800000)
2749  | (nTLSMD ? 0 : 0x8000000)
2750  | (LSMAOE ? 0 : 0x10000000))
2751  .mapsTo(MISCREG_SCTLR_NS);
2752  InitReg(MISCREG_SCTLR_EL12)
2753  .monE2H()
2754  .hypE2H()
2755  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
2756  | (IESB ? 0 : 0x200000)
2757  | (EnDA ? 0 : 0x8000000)
2758  | (EnIB ? 0 : 0x40000000)
2759  | (EnIA ? 0 : 0x80000000))
2760  .res1(0x500800 | (SPAN ? 0 : 0x800000)
2761  | (nTLSMD ? 0 : 0x8000000)
2762  | (LSMAOE ? 0 : 0x10000000))
2763  .mapsTo(MISCREG_SCTLR_EL1);
2764  InitReg(MISCREG_ACTLR_EL1)
2765  .allPrivileges().exceptUserMode()
2766  .mapsTo(MISCREG_ACTLR_NS);
2767  InitReg(MISCREG_CPACR_EL1)
2768  .allPrivileges().exceptUserMode()
2769  .mapsTo(MISCREG_CPACR);
2770  InitReg(MISCREG_CPACR_EL12)
2771  .monE2H()
2772  .hypE2H()
2773  .mapsTo(MISCREG_CPACR_EL1);
2774  InitReg(MISCREG_SCTLR_EL2)
2775  .hyp().mon()
2776  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2777  | (IESB ? 0 : 0x200000)
2778  | (EnDA ? 0 : 0x8000000)
2779  | (EnIB ? 0 : 0x40000000)
2780  | (EnIA ? 0 : 0x80000000))
2781  .res1(0x30c50830)
2782  .mapsTo(MISCREG_HSCTLR);
2783  InitReg(MISCREG_ACTLR_EL2)
2784  .hyp().mon()
2785  .mapsTo(MISCREG_HACTLR);
2786  InitReg(MISCREG_HCR_EL2)
2787  .hyp().mon()
2788  .mapsTo(MISCREG_HCR, MISCREG_HCR2);
2789  InitReg(MISCREG_MDCR_EL2)
2790  .hyp().mon()
2791  .mapsTo(MISCREG_HDCR);
2792  InitReg(MISCREG_CPTR_EL2)
2793  .hyp().mon()
2794  .mapsTo(MISCREG_HCPTR);
2795  InitReg(MISCREG_HSTR_EL2)
2796  .hyp().mon()
2797  .mapsTo(MISCREG_HSTR);
2798  InitReg(MISCREG_HACR_EL2)
2799  .hyp().mon()
2800  .mapsTo(MISCREG_HACR);
2801  InitReg(MISCREG_SCTLR_EL3)
2802  .mon()
2803  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2804  | (IESB ? 0 : 0x200000)
2805  | (EnDA ? 0 : 0x8000000)
2806  | (EnIB ? 0 : 0x40000000)
2807  | (EnIA ? 0 : 0x80000000))
2808  .res1(0x30c50830);
2809  InitReg(MISCREG_ACTLR_EL3)
2810  .mon();
2811  InitReg(MISCREG_SCR_EL3)
2812  .mon()
2813  .mapsTo(MISCREG_SCR); // NAM D7-2005
2814  InitReg(MISCREG_SDER32_EL3)
2815  .mon()
2816  .mapsTo(MISCREG_SDER);
2817  InitReg(MISCREG_CPTR_EL3)
2818  .mon();
2819  InitReg(MISCREG_MDCR_EL3)
2820  .mon()
2821  .mapsTo(MISCREG_SDCR);
2822  InitReg(MISCREG_TTBR0_EL1)
2823  .allPrivileges().exceptUserMode()
2824  .mapsTo(MISCREG_TTBR0_NS);
2825  InitReg(MISCREG_TTBR0_EL12)
2826  .monE2H()
2827  .hypE2H()
2828  .mapsTo(MISCREG_TTBR0_EL1);
2829  InitReg(MISCREG_TTBR1_EL1)
2830  .allPrivileges().exceptUserMode()
2831  .mapsTo(MISCREG_TTBR1_NS);
2832  InitReg(MISCREG_TTBR1_EL12)
2833  .monE2H()
2834  .hypE2H()
2835  .mapsTo(MISCREG_TTBR1_EL1);
2836  InitReg(MISCREG_TCR_EL1)
2837  .allPrivileges().exceptUserMode()
2838  .mapsTo(MISCREG_TTBCR_NS);
2839  InitReg(MISCREG_TCR_EL12)
2840  .monE2H()
2841  .hypE2H()
2842  .mapsTo(MISCREG_TTBCR_NS);
2843  InitReg(MISCREG_TTBR0_EL2)
2844  .hyp().mon()
2845  .mapsTo(MISCREG_HTTBR);
2846  InitReg(MISCREG_TTBR1_EL2)
2847  .hyp().mon();
2848  InitReg(MISCREG_TCR_EL2)
2849  .hyp().mon()
2850  .mapsTo(MISCREG_HTCR);
2851  InitReg(MISCREG_VTTBR_EL2)
2852  .hyp().mon()
2853  .mapsTo(MISCREG_VTTBR);
2854  InitReg(MISCREG_VTCR_EL2)
2855  .hyp().mon()
2856  .mapsTo(MISCREG_VTCR);
2857  InitReg(MISCREG_VSTTBR_EL2)
2858  .hypSecure().mon();
2859  InitReg(MISCREG_VSTCR_EL2)
2860  .hypSecure().mon();
2861  InitReg(MISCREG_TTBR0_EL3)
2862  .mon();
2863  InitReg(MISCREG_TCR_EL3)
2864  .mon();
2865  InitReg(MISCREG_DACR32_EL2)
2866  .hyp().mon()
2867  .mapsTo(MISCREG_DACR_NS);
2868  InitReg(MISCREG_SPSR_EL1)
2869  .allPrivileges().exceptUserMode()
2870  .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
2871  InitReg(MISCREG_SPSR_EL12)
2872  .monE2H()
2873  .hypE2H()
2874  .mapsTo(MISCREG_SPSR_SVC);
2875  InitReg(MISCREG_ELR_EL1)
2876  .allPrivileges().exceptUserMode();
2877  InitReg(MISCREG_ELR_EL12)
2878  .monE2H()
2879  .hypE2H()
2880  .mapsTo(MISCREG_ELR_EL1);
2881  InitReg(MISCREG_SP_EL0)
2882  .allPrivileges().exceptUserMode();
2883  InitReg(MISCREG_SPSEL)
2884  .allPrivileges().exceptUserMode();
2885  InitReg(MISCREG_CURRENTEL)
2886  .allPrivileges().exceptUserMode().writes(0);
2887  InitReg(MISCREG_PAN)
2888  .allPrivileges().exceptUserMode()
2889  .implemented(release->has(ArmExtension::FEAT_PAN));
2890  InitReg(MISCREG_UAO)
2891  .allPrivileges().exceptUserMode();
2892  InitReg(MISCREG_NZCV)
2893  .allPrivileges();
2894  InitReg(MISCREG_DAIF)
2895  .allPrivileges();
2896  InitReg(MISCREG_FPCR)
2897  .allPrivileges();
2898  InitReg(MISCREG_FPSR)
2899  .allPrivileges();
2900  InitReg(MISCREG_DSPSR_EL0)
2901  .allPrivileges();
2902  InitReg(MISCREG_DLR_EL0)
2903  .allPrivileges();
2904  InitReg(MISCREG_SPSR_EL2)
2905  .hyp().mon()
2906  .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
2907  InitReg(MISCREG_ELR_EL2)
2908  .hyp().mon();
2909  InitReg(MISCREG_SP_EL1)
2910  .hyp().mon();
2911  InitReg(MISCREG_SPSR_IRQ_AA64)
2912  .hyp().mon();
2913  InitReg(MISCREG_SPSR_ABT_AA64)
2914  .hyp().mon();
2915  InitReg(MISCREG_SPSR_UND_AA64)
2916  .hyp().mon();
2917  InitReg(MISCREG_SPSR_FIQ_AA64)
2918  .hyp().mon();
2919  InitReg(MISCREG_SPSR_EL3)
2920  .mon()
2921  .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
2922  InitReg(MISCREG_ELR_EL3)
2923  .mon();
2924  InitReg(MISCREG_SP_EL2)
2925  .mon();
2926  InitReg(MISCREG_AFSR0_EL1)
2927  .allPrivileges().exceptUserMode()
2928  .mapsTo(MISCREG_ADFSR_NS);
2929  InitReg(MISCREG_AFSR0_EL12)
2930  .monE2H()
2931  .hypE2H()
2932  .mapsTo(MISCREG_ADFSR_NS);
2933  InitReg(MISCREG_AFSR1_EL1)
2934  .allPrivileges().exceptUserMode()
2935  .mapsTo(MISCREG_AIFSR_NS);
2936  InitReg(MISCREG_AFSR1_EL12)
2937  .monE2H()
2938  .hypE2H()
2939  .mapsTo(MISCREG_AIFSR_NS);
2940  InitReg(MISCREG_ESR_EL1)
2941  .allPrivileges().exceptUserMode();
2942  InitReg(MISCREG_ESR_EL12)
2943  .monE2H()
2944  .hypE2H()
2945  .mapsTo(MISCREG_ESR_EL1);
2946  InitReg(MISCREG_IFSR32_EL2)
2947  .hyp().mon()
2948  .mapsTo(MISCREG_IFSR_NS);
2949  InitReg(MISCREG_AFSR0_EL2)
2950  .hyp().mon()
2951  .mapsTo(MISCREG_HADFSR);
2952  InitReg(MISCREG_AFSR1_EL2)
2953  .hyp().mon()
2954  .mapsTo(MISCREG_HAIFSR);
2955  InitReg(MISCREG_ESR_EL2)
2956  .hyp().mon()
2957  .mapsTo(MISCREG_HSR);
2958  InitReg(MISCREG_FPEXC32_EL2)
2959  .hyp().mon().mapsTo(MISCREG_FPEXC);
2960  InitReg(MISCREG_AFSR0_EL3)
2961  .mon();
2962  InitReg(MISCREG_AFSR1_EL3)
2963  .mon();
2964  InitReg(MISCREG_ESR_EL3)
2965  .mon();
2966  InitReg(MISCREG_FAR_EL1)
2967  .allPrivileges().exceptUserMode()
2968  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
2969  InitReg(MISCREG_FAR_EL12)
2970  .monE2H()
2971  .hypE2H()
2972  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
2973  InitReg(MISCREG_FAR_EL2)
2974  .hyp().mon()
2975  .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
2976  InitReg(MISCREG_HPFAR_EL2)
2977  .hyp().mon()
2978  .mapsTo(MISCREG_HPFAR);
2979  InitReg(MISCREG_FAR_EL3)
2980  .mon();
2981  InitReg(MISCREG_IC_IALLUIS)
2982  .warnNotFail()
2983  .writes(1).exceptUserMode();
2984  InitReg(MISCREG_PAR_EL1)
2985  .allPrivileges().exceptUserMode()
2986  .mapsTo(MISCREG_PAR_NS);
2987  InitReg(MISCREG_IC_IALLU)
2988  .warnNotFail()
2989  .writes(1).exceptUserMode();
2990  InitReg(MISCREG_DC_IVAC_Xt)
2991  .warnNotFail()
2992  .writes(1).exceptUserMode();
2993  InitReg(MISCREG_DC_ISW_Xt)
2994  .warnNotFail()
2995  .writes(1).exceptUserMode();
2996  InitReg(MISCREG_AT_S1E1R_Xt)
2997  .writes(1).exceptUserMode();
2998  InitReg(MISCREG_AT_S1E1W_Xt)
2999  .writes(1).exceptUserMode();
3000  InitReg(MISCREG_AT_S1E0R_Xt)
3001  .writes(1).exceptUserMode();
3002  InitReg(MISCREG_AT_S1E0W_Xt)
3003  .writes(1).exceptUserMode();
3004  InitReg(MISCREG_DC_CSW_Xt)
3005  .warnNotFail()
3006  .writes(1).exceptUserMode();
3007  InitReg(MISCREG_DC_CISW_Xt)
3008  .warnNotFail()
3009  .writes(1).exceptUserMode();
3010  InitReg(MISCREG_DC_ZVA_Xt)
3011  .warnNotFail()
3012  .writes(1).userSecureWrite(0);
3013  InitReg(MISCREG_IC_IVAU_Xt)
3014  .writes(1);
3015  InitReg(MISCREG_DC_CVAC_Xt)
3016  .warnNotFail()
3017  .writes(1);
3018  InitReg(MISCREG_DC_CVAU_Xt)
3019  .warnNotFail()
3020  .writes(1);
3021  InitReg(MISCREG_DC_CIVAC_Xt)
3022  .warnNotFail()
3023  .writes(1);
3024  InitReg(MISCREG_AT_S1E2R_Xt)
3025  .monNonSecureWrite().hypWrite();
3026  InitReg(MISCREG_AT_S1E2W_Xt)
3027  .monNonSecureWrite().hypWrite();
3028  InitReg(MISCREG_AT_S12E1R_Xt)
3029  .hypWrite().monSecureWrite().monNonSecureWrite();
3030  InitReg(MISCREG_AT_S12E1W_Xt)
3031  .hypWrite().monSecureWrite().monNonSecureWrite();
3032  InitReg(MISCREG_AT_S12E0R_Xt)
3033  .hypWrite().monSecureWrite().monNonSecureWrite();
3034  InitReg(MISCREG_AT_S12E0W_Xt)
3035  .hypWrite().monSecureWrite().monNonSecureWrite();
3036  InitReg(MISCREG_AT_S1E3R_Xt)
3037  .monSecureWrite().monNonSecureWrite();
3038  InitReg(MISCREG_AT_S1E3W_Xt)
3039  .monSecureWrite().monNonSecureWrite();
3040  InitReg(MISCREG_TLBI_VMALLE1IS)
3041  .writes(1).exceptUserMode();
3042  InitReg(MISCREG_TLBI_VAE1IS_Xt)
3043  .writes(1).exceptUserMode();
3044  InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3045  .writes(1).exceptUserMode();
3046  InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3047  .writes(1).exceptUserMode();
3048  InitReg(MISCREG_TLBI_VALE1IS_Xt)
3049  .writes(1).exceptUserMode();
3050  InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3051  .writes(1).exceptUserMode();
3052  InitReg(MISCREG_TLBI_VMALLE1)
3053  .writes(1).exceptUserMode();
3054  InitReg(MISCREG_TLBI_VAE1_Xt)
3055  .writes(1).exceptUserMode();
3056  InitReg(MISCREG_TLBI_ASIDE1_Xt)
3057  .writes(1).exceptUserMode();
3058  InitReg(MISCREG_TLBI_VAAE1_Xt)
3059  .writes(1).exceptUserMode();
3060  InitReg(MISCREG_TLBI_VALE1_Xt)
3061  .writes(1).exceptUserMode();
3062  InitReg(MISCREG_TLBI_VAALE1_Xt)
3063  .writes(1).exceptUserMode();
3064  InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3065  .hypWrite().monSecureWrite().monNonSecureWrite();
3066  InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3067  .hypWrite().monSecureWrite().monNonSecureWrite();
3068  InitReg(MISCREG_TLBI_ALLE2IS)
3069  .monNonSecureWrite().hypWrite();
3070  InitReg(MISCREG_TLBI_VAE2IS_Xt)
3071  .monNonSecureWrite().hypWrite();
3072  InitReg(MISCREG_TLBI_ALLE1IS)
3073  .hypWrite().monSecureWrite().monNonSecureWrite();
3074  InitReg(MISCREG_TLBI_VALE2IS_Xt)
3075  .monNonSecureWrite().hypWrite();
3076  InitReg(MISCREG_TLBI_VMALLS12E1IS)
3077  .hypWrite().monSecureWrite().monNonSecureWrite();
3078  InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3079  .hypWrite().monSecureWrite().monNonSecureWrite();
3080  InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3081  .hypWrite().monSecureWrite().monNonSecureWrite();
3082  InitReg(MISCREG_TLBI_ALLE2)
3083  .monNonSecureWrite().hypWrite();
3084  InitReg(MISCREG_TLBI_VAE2_Xt)
3085  .monNonSecureWrite().hypWrite();
3086  InitReg(MISCREG_TLBI_ALLE1)
3087  .hypWrite().monSecureWrite().monNonSecureWrite();
3088  InitReg(MISCREG_TLBI_VALE2_Xt)
3089  .monNonSecureWrite().hypWrite();
3090  InitReg(MISCREG_TLBI_VMALLS12E1)
3091  .hypWrite().monSecureWrite().monNonSecureWrite();
3092  InitReg(MISCREG_TLBI_ALLE3IS)
3093  .monSecureWrite().monNonSecureWrite();
3094  InitReg(MISCREG_TLBI_VAE3IS_Xt)
3095  .monSecureWrite().monNonSecureWrite();
3096  InitReg(MISCREG_TLBI_VALE3IS_Xt)
3097  .monSecureWrite().monNonSecureWrite();
3098  InitReg(MISCREG_TLBI_ALLE3)
3099  .monSecureWrite().monNonSecureWrite();
3100  InitReg(MISCREG_TLBI_VAE3_Xt)
3101  .monSecureWrite().monNonSecureWrite();
3102  InitReg(MISCREG_TLBI_VALE3_Xt)
3103  .monSecureWrite().monNonSecureWrite();
3104  InitReg(MISCREG_PMINTENSET_EL1)
3105  .allPrivileges().exceptUserMode()
3106  .mapsTo(MISCREG_PMINTENSET);
3107  InitReg(MISCREG_PMINTENCLR_EL1)
3108  .allPrivileges().exceptUserMode()
3109  .mapsTo(MISCREG_PMINTENCLR);
3110  InitReg(MISCREG_PMCR_EL0)
3111  .allPrivileges()
3112  .mapsTo(MISCREG_PMCR);
3113  InitReg(MISCREG_PMCNTENSET_EL0)
3114  .allPrivileges()
3115  .mapsTo(MISCREG_PMCNTENSET);
3116  InitReg(MISCREG_PMCNTENCLR_EL0)
3117  .allPrivileges()
3118  .mapsTo(MISCREG_PMCNTENCLR);
3119  InitReg(MISCREG_PMOVSCLR_EL0)
3120  .allPrivileges();
3121 // .mapsTo(MISCREG_PMOVSCLR);
3122  InitReg(MISCREG_PMSWINC_EL0)
3123  .writes(1).user()
3124  .mapsTo(MISCREG_PMSWINC);
3125  InitReg(MISCREG_PMSELR_EL0)
3126  .allPrivileges()
3127  .mapsTo(MISCREG_PMSELR);
3128  InitReg(MISCREG_PMCEID0_EL0)
3129  .reads(1).user()
3130  .mapsTo(MISCREG_PMCEID0);
3131  InitReg(MISCREG_PMCEID1_EL0)
3132  .reads(1).user()
3133  .mapsTo(MISCREG_PMCEID1);
3134  InitReg(MISCREG_PMCCNTR_EL0)
3135  .allPrivileges()
3136  .mapsTo(MISCREG_PMCCNTR);
3137  InitReg(MISCREG_PMXEVTYPER_EL0)
3138  .allPrivileges()
3139  .mapsTo(MISCREG_PMXEVTYPER);
3140  InitReg(MISCREG_PMCCFILTR_EL0)
3141  .allPrivileges();
3142  InitReg(MISCREG_PMXEVCNTR_EL0)
3143  .allPrivileges()
3144  .mapsTo(MISCREG_PMXEVCNTR);
3145  InitReg(MISCREG_PMUSERENR_EL0)
3146  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3147  .mapsTo(MISCREG_PMUSERENR);
3148  InitReg(MISCREG_PMOVSSET_EL0)
3149  .allPrivileges()
3150  .mapsTo(MISCREG_PMOVSSET);
3151  InitReg(MISCREG_MAIR_EL1)
3152  .allPrivileges().exceptUserMode()
3153  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3154  InitReg(MISCREG_MAIR_EL12)
3155  .monE2H()
3156  .hypE2H()
3157  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3158  InitReg(MISCREG_AMAIR_EL1)
3159  .allPrivileges().exceptUserMode()
3160  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3161  InitReg(MISCREG_AMAIR_EL12)
3162  .monE2H()
3163  .hypE2H()
3164  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3165  InitReg(MISCREG_MAIR_EL2)
3166  .hyp().mon()
3167  .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3168  InitReg(MISCREG_AMAIR_EL2)
3169  .hyp().mon()
3170  .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3171  InitReg(MISCREG_MAIR_EL3)
3172  .mon();
3173  InitReg(MISCREG_AMAIR_EL3)
3174  .mon();
3175  InitReg(MISCREG_L2CTLR_EL1)
3176  .allPrivileges().exceptUserMode();
3177  InitReg(MISCREG_L2ECTLR_EL1)
3178  .allPrivileges().exceptUserMode();
3179  InitReg(MISCREG_VBAR_EL1)
3180  .allPrivileges().exceptUserMode()
3181  .mapsTo(MISCREG_VBAR_NS);
3182  InitReg(MISCREG_VBAR_EL12)
3183  .monE2H()
3184  .hypE2H()
3185  .mapsTo(MISCREG_VBAR_NS);
3186  InitReg(MISCREG_RVBAR_EL1)
3187  .allPrivileges().exceptUserMode().writes(0);
3188  InitReg(MISCREG_ISR_EL1)
3189  .allPrivileges().exceptUserMode().writes(0);
3190  InitReg(MISCREG_VBAR_EL2)
3191  .hyp().mon()
3192  .res0(0x7ff)
3193  .mapsTo(MISCREG_HVBAR);
3194  InitReg(MISCREG_RVBAR_EL2)
3195  .mon().hyp().writes(0);
3196  InitReg(MISCREG_VBAR_EL3)
3197  .mon();
3198  InitReg(MISCREG_RVBAR_EL3)
3199  .mon().writes(0);
3200  InitReg(MISCREG_RMR_EL3)
3201  .mon();
3202  InitReg(MISCREG_CONTEXTIDR_EL1)
3203  .allPrivileges().exceptUserMode()
3204  .mapsTo(MISCREG_CONTEXTIDR_NS);
3205  InitReg(MISCREG_CONTEXTIDR_EL12)
3206  .monE2H()
3207  .hypE2H()
3208  .mapsTo(MISCREG_CONTEXTIDR_NS);
3209  InitReg(MISCREG_TPIDR_EL1)
3210  .allPrivileges().exceptUserMode()
3211  .mapsTo(MISCREG_TPIDRPRW_NS);
3212  InitReg(MISCREG_TPIDR_EL0)
3213  .allPrivileges()
3214  .mapsTo(MISCREG_TPIDRURW_NS);
3215  InitReg(MISCREG_TPIDRRO_EL0)
3216  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3217  .mapsTo(MISCREG_TPIDRURO_NS);
3218  InitReg(MISCREG_TPIDR_EL2)
3219  .hyp().mon()
3220  .mapsTo(MISCREG_HTPIDR);
3221  InitReg(MISCREG_TPIDR_EL3)
3222  .mon();
3223  // BEGIN Generic Timer (AArch64)
3224  InitReg(MISCREG_CNTFRQ_EL0)
3225  .reads(1)
3226  .highest(system)
3227  .privSecureWrite(aarch32EL3)
3228  .mapsTo(MISCREG_CNTFRQ);
3229  InitReg(MISCREG_CNTPCT_EL0)
3230  .unverifiable()
3231  .reads(1)
3232  .mapsTo(MISCREG_CNTPCT);
3233  InitReg(MISCREG_CNTVCT_EL0)
3234  .unverifiable()
3235  .reads(1)
3236  .mapsTo(MISCREG_CNTVCT);
3237  InitReg(MISCREG_CNTP_CTL_EL0)
3238  .allPrivileges()
3239  .res0(0xfffffffffffffff8)
3240  .mapsTo(MISCREG_CNTP_CTL_NS);
3241  InitReg(MISCREG_CNTP_CVAL_EL0)
3242  .allPrivileges()
3243  .mapsTo(MISCREG_CNTP_CVAL_NS);
3244  InitReg(MISCREG_CNTP_TVAL_EL0)
3245  .allPrivileges()
3246  .res0(0xffffffff00000000)
3247  .mapsTo(MISCREG_CNTP_TVAL_NS);
3248  InitReg(MISCREG_CNTV_CTL_EL0)
3249  .allPrivileges()
3250  .res0(0xfffffffffffffff8)
3251  .mapsTo(MISCREG_CNTV_CTL);
3252  InitReg(MISCREG_CNTV_CVAL_EL0)
3253  .allPrivileges()
3254  .mapsTo(MISCREG_CNTV_CVAL);
3255  InitReg(MISCREG_CNTV_TVAL_EL0)
3256  .allPrivileges()
3257  .res0(0xffffffff00000000)
3258  .mapsTo(MISCREG_CNTV_TVAL);
3259  InitReg(MISCREG_CNTP_CTL_EL02)
3260  .monE2H()
3261  .hypE2H()
3262  .res0(0xfffffffffffffff8)
3263  .mapsTo(MISCREG_CNTP_CTL_NS);
3264  InitReg(MISCREG_CNTP_CVAL_EL02)
3265  .monE2H()
3266  .hypE2H()
3267  .mapsTo(MISCREG_CNTP_CVAL_NS);
3268  InitReg(MISCREG_CNTP_TVAL_EL02)
3269  .monE2H()
3270  .hypE2H()
3271  .res0(0xffffffff00000000)
3272  .mapsTo(MISCREG_CNTP_TVAL_NS);
3273  InitReg(MISCREG_CNTV_CTL_EL02)
3274  .monE2H()
3275  .hypE2H()
3276  .res0(0xfffffffffffffff8)
3277  .mapsTo(MISCREG_CNTV_CTL);
3278  InitReg(MISCREG_CNTV_CVAL_EL02)
3279  .monE2H()
3280  .hypE2H()
3281  .mapsTo(MISCREG_CNTV_CVAL);
3282  InitReg(MISCREG_CNTV_TVAL_EL02)
3283  .monE2H()
3284  .hypE2H()
3285  .res0(0xffffffff00000000)
3286  .mapsTo(MISCREG_CNTV_TVAL);
3287  InitReg(MISCREG_CNTKCTL_EL1)
3288  .allPrivileges()
3289  .exceptUserMode()
3290  .res0(0xfffffffffffdfc00)
3291  .mapsTo(MISCREG_CNTKCTL);
3292  InitReg(MISCREG_CNTKCTL_EL12)
3293  .monE2H()
3294  .hypE2H()
3295  .res0(0xfffffffffffdfc00)
3296  .mapsTo(MISCREG_CNTKCTL);
3297  InitReg(MISCREG_CNTPS_CTL_EL1)
3298  .mon()
3299  .privSecure()
3300  .res0(0xfffffffffffffff8);
3301  InitReg(MISCREG_CNTPS_CVAL_EL1)
3302  .mon()
3303  .privSecure();
3304  InitReg(MISCREG_CNTPS_TVAL_EL1)
3305  .mon()
3306  .privSecure()
3307  .res0(0xffffffff00000000);
3308  InitReg(MISCREG_CNTHCTL_EL2)
3309  .mon()
3310  .hyp()
3311  .res0(0xfffffffffffc0000)
3312  .mapsTo(MISCREG_CNTHCTL);
3313  InitReg(MISCREG_CNTHP_CTL_EL2)
3314  .mon()
3315  .hyp()
3316  .res0(0xfffffffffffffff8)
3317  .mapsTo(MISCREG_CNTHP_CTL);
3318  InitReg(MISCREG_CNTHP_CVAL_EL2)
3319  .mon()
3320  .hyp()
3321  .mapsTo(MISCREG_CNTHP_CVAL);
3322  InitReg(MISCREG_CNTHP_TVAL_EL2)
3323  .mon()
3324  .hyp()
3325  .res0(0xffffffff00000000)
3326  .mapsTo(MISCREG_CNTHP_TVAL);
3327  InitReg(MISCREG_CNTHPS_CTL_EL2)
3328  .mon()
3329  .hypSecure()
3330  .res0(0xfffffffffffffff8)
3331  .implemented(sel2_implemented);
3332  InitReg(MISCREG_CNTHPS_CVAL_EL2)
3333  .mon()
3334  .hypSecure()
3335  .implemented(sel2_implemented);
3336  InitReg(MISCREG_CNTHPS_TVAL_EL2)
3337  .mon()
3338  .hypSecure()
3339  .res0(0xffffffff00000000)
3340  .implemented(sel2_implemented);
3341  InitReg(MISCREG_CNTHV_CTL_EL2)
3342  .mon()
3343  .hyp()
3344  .res0(0xfffffffffffffff8)
3345  .implemented(vhe_implemented);
3346  InitReg(MISCREG_CNTHV_CVAL_EL2)
3347  .mon()
3348  .hyp()
3349  .implemented(vhe_implemented);
3350  InitReg(MISCREG_CNTHV_TVAL_EL2)
3351  .mon()
3352  .hyp()
3353  .res0(0xffffffff00000000)
3354  .implemented(vhe_implemented);
3355  InitReg(MISCREG_CNTHVS_CTL_EL2)
3356  .mon()
3357  .hypSecure()
3358  .res0(0xfffffffffffffff8)
3359  .implemented(vhe_implemented && sel2_implemented);
3360  InitReg(MISCREG_CNTHVS_CVAL_EL2)
3361  .mon()
3362  .hypSecure()
3363  .implemented(vhe_implemented && sel2_implemented);
3364  InitReg(MISCREG_CNTHVS_TVAL_EL2)
3365  .mon()
3366  .hypSecure()
3367  .res0(0xffffffff00000000)
3368  .implemented(vhe_implemented && sel2_implemented);
3369  // ENDIF Armv8.1-VHE
3370  InitReg(MISCREG_CNTVOFF_EL2)
3371  .mon()
3372  .hyp()
3373  .mapsTo(MISCREG_CNTVOFF);
3374  // END Generic Timer (AArch64)
3375  InitReg(MISCREG_PMEVCNTR0_EL0)
3376  .allPrivileges();
3377 // .mapsTo(MISCREG_PMEVCNTR0);
3378  InitReg(MISCREG_PMEVCNTR1_EL0)
3379  .allPrivileges();
3380 // .mapsTo(MISCREG_PMEVCNTR1);
3381  InitReg(MISCREG_PMEVCNTR2_EL0)
3382  .allPrivileges();
3383 // .mapsTo(MISCREG_PMEVCNTR2);
3384  InitReg(MISCREG_PMEVCNTR3_EL0)
3385  .allPrivileges();
3386 // .mapsTo(MISCREG_PMEVCNTR3);
3387  InitReg(MISCREG_PMEVCNTR4_EL0)
3388  .allPrivileges();
3389 // .mapsTo(MISCREG_PMEVCNTR4);
3390  InitReg(MISCREG_PMEVCNTR5_EL0)
3391  .allPrivileges();
3392 // .mapsTo(MISCREG_PMEVCNTR5);
3393  InitReg(MISCREG_PMEVTYPER0_EL0)
3394  .allPrivileges();
3395 // .mapsTo(MISCREG_PMEVTYPER0);
3396  InitReg(MISCREG_PMEVTYPER1_EL0)
3397  .allPrivileges();
3398 // .mapsTo(MISCREG_PMEVTYPER1);
3399  InitReg(MISCREG_PMEVTYPER2_EL0)
3400  .allPrivileges();
3401 // .mapsTo(MISCREG_PMEVTYPER2);
3402  InitReg(MISCREG_PMEVTYPER3_EL0)
3403  .allPrivileges();
3404 // .mapsTo(MISCREG_PMEVTYPER3);
3405  InitReg(MISCREG_PMEVTYPER4_EL0)
3406  .allPrivileges();
3407 // .mapsTo(MISCREG_PMEVTYPER4);
3408  InitReg(MISCREG_PMEVTYPER5_EL0)
3409  .allPrivileges();
3410 // .mapsTo(MISCREG_PMEVTYPER5);
3411  InitReg(MISCREG_IL1DATA0_EL1)
3412  .allPrivileges().exceptUserMode();
3413  InitReg(MISCREG_IL1DATA1_EL1)
3414  .allPrivileges().exceptUserMode();
3415  InitReg(MISCREG_IL1DATA2_EL1)
3416  .allPrivileges().exceptUserMode();
3417  InitReg(MISCREG_IL1DATA3_EL1)
3418  .allPrivileges().exceptUserMode();
3419  InitReg(MISCREG_DL1DATA0_EL1)
3420  .allPrivileges().exceptUserMode();
3421  InitReg(MISCREG_DL1DATA1_EL1)
3422  .allPrivileges().exceptUserMode();
3423  InitReg(MISCREG_DL1DATA2_EL1)
3424  .allPrivileges().exceptUserMode();
3425  InitReg(MISCREG_DL1DATA3_EL1)
3426  .allPrivileges().exceptUserMode();
3427  InitReg(MISCREG_DL1DATA4_EL1)
3428  .allPrivileges().exceptUserMode();
3429  InitReg(MISCREG_L2ACTLR_EL1)
3430  .allPrivileges().exceptUserMode();
3431  InitReg(MISCREG_CPUACTLR_EL1)
3432  .allPrivileges().exceptUserMode();
3433  InitReg(MISCREG_CPUECTLR_EL1)
3434  .allPrivileges().exceptUserMode();
3435  InitReg(MISCREG_CPUMERRSR_EL1)
3436  .allPrivileges().exceptUserMode();
3437  InitReg(MISCREG_L2MERRSR_EL1)
3438  .unimplemented()
3439  .warnNotFail()
3440  .allPrivileges().exceptUserMode();
3441  InitReg(MISCREG_CBAR_EL1)
3442  .allPrivileges().exceptUserMode().writes(0);
3443  InitReg(MISCREG_CONTEXTIDR_EL2)
3444  .mon().hyp();
3445 
3446  // GICv3 AArch64
3447  InitReg(MISCREG_ICC_PMR_EL1)
3448  .res0(0xffffff00) // [31:8]
3449  .allPrivileges().exceptUserMode()
3450  .mapsTo(MISCREG_ICC_PMR);
3451  InitReg(MISCREG_ICC_IAR0_EL1)
3452  .allPrivileges().exceptUserMode().writes(0)
3453  .mapsTo(MISCREG_ICC_IAR0);
3454  InitReg(MISCREG_ICC_EOIR0_EL1)
3455  .allPrivileges().exceptUserMode().reads(0)
3456  .mapsTo(MISCREG_ICC_EOIR0);
3457  InitReg(MISCREG_ICC_HPPIR0_EL1)
3458  .allPrivileges().exceptUserMode().writes(0)
3459  .mapsTo(MISCREG_ICC_HPPIR0);
3460  InitReg(MISCREG_ICC_BPR0_EL1)
3461  .res0(0xfffffff8) // [31:3]
3462  .allPrivileges().exceptUserMode()
3463  .mapsTo(MISCREG_ICC_BPR0);
3464  InitReg(MISCREG_ICC_AP0R0_EL1)
3465  .allPrivileges().exceptUserMode()
3466  .mapsTo(MISCREG_ICC_AP0R0);
3467  InitReg(MISCREG_ICC_AP0R1_EL1)
3468  .allPrivileges().exceptUserMode()
3469  .mapsTo(MISCREG_ICC_AP0R1);
3470  InitReg(MISCREG_ICC_AP0R2_EL1)
3471  .allPrivileges().exceptUserMode()
3472  .mapsTo(MISCREG_ICC_AP0R2);
3473  InitReg(MISCREG_ICC_AP0R3_EL1)
3474  .allPrivileges().exceptUserMode()
3475  .mapsTo(MISCREG_ICC_AP0R3);
3476  InitReg(MISCREG_ICC_AP1R0_EL1)
3477  .banked64()
3478  .mapsTo(MISCREG_ICC_AP1R0);
3479  InitReg(MISCREG_ICC_AP1R0_EL1_NS)
3480  .bankedChild()
3481  .allPrivileges().exceptUserMode()
3482  .mapsTo(MISCREG_ICC_AP1R0_NS);
3483  InitReg(MISCREG_ICC_AP1R0_EL1_S)
3484  .bankedChild()
3485  .allPrivileges().exceptUserMode()
3486  .mapsTo(MISCREG_ICC_AP1R0_S);
3487  InitReg(MISCREG_ICC_AP1R1_EL1)
3488  .banked64()
3489  .mapsTo(MISCREG_ICC_AP1R1);
3490  InitReg(MISCREG_ICC_AP1R1_EL1_NS)
3491  .bankedChild()
3492  .allPrivileges().exceptUserMode()
3493  .mapsTo(MISCREG_ICC_AP1R1_NS);
3494  InitReg(MISCREG_ICC_AP1R1_EL1_S)
3495  .bankedChild()
3496  .allPrivileges().exceptUserMode()
3497  .mapsTo(MISCREG_ICC_AP1R1_S);
3498  InitReg(MISCREG_ICC_AP1R2_EL1)
3499  .banked64()
3500  .mapsTo(MISCREG_ICC_AP1R2);
3501  InitReg(MISCREG_ICC_AP1R2_EL1_NS)
3502  .bankedChild()
3503  .allPrivileges().exceptUserMode()
3504  .mapsTo(MISCREG_ICC_AP1R2_NS);
3505  InitReg(MISCREG_ICC_AP1R2_EL1_S)
3506  .bankedChild()
3507  .allPrivileges().exceptUserMode()
3508  .mapsTo(MISCREG_ICC_AP1R2_S);
3509  InitReg(MISCREG_ICC_AP1R3_EL1)
3510  .banked64()
3511  .mapsTo(MISCREG_ICC_AP1R3);
3512  InitReg(MISCREG_ICC_AP1R3_EL1_NS)
3513  .bankedChild()
3514  .allPrivileges().exceptUserMode()
3515  .mapsTo(MISCREG_ICC_AP1R3_NS);
3516  InitReg(MISCREG_ICC_AP1R3_EL1_S)
3517  .bankedChild()
3518  .allPrivileges().exceptUserMode()
3519  .mapsTo(MISCREG_ICC_AP1R3_S);
3520  InitReg(MISCREG_ICC_DIR_EL1)
3521  .res0(0xFF000000) // [31:24]
3522  .allPrivileges().exceptUserMode().reads(0)
3523  .mapsTo(MISCREG_ICC_DIR);
3524  InitReg(MISCREG_ICC_RPR_EL1)
3525  .allPrivileges().exceptUserMode().writes(0)
3526  .mapsTo(MISCREG_ICC_RPR);
3527  InitReg(MISCREG_ICC_SGI1R_EL1)
3528  .allPrivileges().exceptUserMode().reads(0)
3529  .mapsTo(MISCREG_ICC_SGI1R);
3530  InitReg(MISCREG_ICC_ASGI1R_EL1)
3531  .allPrivileges().exceptUserMode().reads(0)
3532  .mapsTo(MISCREG_ICC_ASGI1R);
3533  InitReg(MISCREG_ICC_SGI0R_EL1)
3534  .allPrivileges().exceptUserMode().reads(0)
3535  .mapsTo(MISCREG_ICC_SGI0R);
3536  InitReg(MISCREG_ICC_IAR1_EL1)
3537  .allPrivileges().exceptUserMode().writes(0)
3538  .mapsTo(MISCREG_ICC_IAR1);
3539  InitReg(MISCREG_ICC_EOIR1_EL1)
3540  .res0(0xFF000000) // [31:24]
3541  .allPrivileges().exceptUserMode().reads(0)
3542  .mapsTo(MISCREG_ICC_EOIR1);
3543  InitReg(MISCREG_ICC_HPPIR1_EL1)
3544  .allPrivileges().exceptUserMode().writes(0)
3545  .mapsTo(MISCREG_ICC_HPPIR1);
3546  InitReg(MISCREG_ICC_BPR1_EL1)
3547  .banked64()
3548  .mapsTo(MISCREG_ICC_BPR1);
3549  InitReg(MISCREG_ICC_BPR1_EL1_NS)
3550  .bankedChild()
3551  .res0(0xfffffff8) // [31:3]
3552  .allPrivileges().exceptUserMode()
3553  .mapsTo(MISCREG_ICC_BPR1_NS);
3554  InitReg(MISCREG_ICC_BPR1_EL1_S)
3555  .bankedChild()
3556  .res0(0xfffffff8) // [31:3]
3557  .secure().exceptUserMode()
3558  .mapsTo(MISCREG_ICC_BPR1_S);
3559  InitReg(MISCREG_ICC_CTLR_EL1)
3560  .banked64()
3561  .mapsTo(MISCREG_ICC_CTLR);
3562  InitReg(MISCREG_ICC_CTLR_EL1_NS)
3563  .bankedChild()
3564  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
3565  .allPrivileges().exceptUserMode()
3566  .mapsTo(MISCREG_ICC_CTLR_NS);
3567  InitReg(MISCREG_ICC_CTLR_EL1_S)
3568  .bankedChild()
3569  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
3570  .secure().exceptUserMode()
3571  .mapsTo(MISCREG_ICC_CTLR_S);
3572  InitReg(MISCREG_ICC_SRE_EL1)
3573  .banked()
3574  .mapsTo(MISCREG_ICC_SRE);
3575  InitReg(MISCREG_ICC_SRE_EL1_NS)
3576  .bankedChild()
3577  .res0(0xFFFFFFF8) // [31:3]
3578  .allPrivileges().exceptUserMode()
3579  .mapsTo(MISCREG_ICC_SRE_NS);
3580  InitReg(MISCREG_ICC_SRE_EL1_S)
3581  .bankedChild()
3582  .res0(0xFFFFFFF8) // [31:3]
3583  .secure().exceptUserMode()
3584  .mapsTo(MISCREG_ICC_SRE_S);
3585  InitReg(MISCREG_ICC_IGRPEN0_EL1)
3586  .res0(0xFFFFFFFE) // [31:1]
3587  .allPrivileges().exceptUserMode()
3588  .mapsTo(MISCREG_ICC_IGRPEN0);
3589  InitReg(MISCREG_ICC_IGRPEN1_EL1)
3590  .banked64()
3591  .mapsTo(MISCREG_ICC_IGRPEN1);
3592  InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
3593  .bankedChild()
3594  .res0(0xFFFFFFFE) // [31:1]
3595  .allPrivileges().exceptUserMode()
3596  .mapsTo(MISCREG_ICC_IGRPEN1_NS);
3597  InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
3598  .bankedChild()
3599  .res0(0xFFFFFFFE) // [31:1]
3600  .secure().exceptUserMode()
3601  .mapsTo(MISCREG_ICC_IGRPEN1_S);
3602  InitReg(MISCREG_ICC_SRE_EL2)
3603  .hyp().mon()
3604  .mapsTo(MISCREG_ICC_HSRE);
3605  InitReg(MISCREG_ICC_CTLR_EL3)
3606  .allPrivileges().exceptUserMode()
3607  .mapsTo(MISCREG_ICC_MCTLR);
3608  InitReg(MISCREG_ICC_SRE_EL3)
3609  .allPrivileges().exceptUserMode()
3610  .mapsTo(MISCREG_ICC_MSRE);
3611  InitReg(MISCREG_ICC_IGRPEN1_EL3)
3612  .allPrivileges().exceptUserMode()
3613  .mapsTo(MISCREG_ICC_MGRPEN1);
3614 
3615  InitReg(MISCREG_ICH_AP0R0_EL2)
3616  .hyp().mon()
3617  .mapsTo(MISCREG_ICH_AP0R0);
3618  InitReg(MISCREG_ICH_AP0R1_EL2)
3619  .hyp().mon()
3620  .unimplemented()
3621  .mapsTo(MISCREG_ICH_AP0R1);
3622  InitReg(MISCREG_ICH_AP0R2_EL2)
3623  .hyp().mon()
3624  .unimplemented()
3625  .mapsTo(MISCREG_ICH_AP0R2);
3626  InitReg(MISCREG_ICH_AP0R3_EL2)
3627  .hyp().mon()
3628  .unimplemented()
3629  .mapsTo(MISCREG_ICH_AP0R3);
3630  InitReg(MISCREG_ICH_AP1R0_EL2)
3631  .hyp().mon()
3632  .mapsTo(MISCREG_ICH_AP1R0);
3633  InitReg(MISCREG_ICH_AP1R1_EL2)
3634  .hyp().mon()
3635  .unimplemented()
3636  .mapsTo(MISCREG_ICH_AP1R1);
3637  InitReg(MISCREG_ICH_AP1R2_EL2)
3638  .hyp().mon()
3639  .unimplemented()
3640  .mapsTo(MISCREG_ICH_AP1R2);
3641  InitReg(MISCREG_ICH_AP1R3_EL2)
3642  .hyp().mon()
3643  .unimplemented()
3644  .mapsTo(MISCREG_ICH_AP1R3);
3645  InitReg(MISCREG_ICH_HCR_EL2)
3646  .hyp().mon()
3647  .mapsTo(MISCREG_ICH_HCR);
3648  InitReg(MISCREG_ICH_VTR_EL2)
3649  .hyp().mon().writes(0)
3650  .mapsTo(MISCREG_ICH_VTR);
3651  InitReg(MISCREG_ICH_MISR_EL2)
3652  .hyp().mon().writes(0)
3653  .mapsTo(MISCREG_ICH_MISR);
3654  InitReg(MISCREG_ICH_EISR_EL2)
3655  .hyp().mon().writes(0)
3656  .mapsTo(MISCREG_ICH_EISR);
3657  InitReg(MISCREG_ICH_ELRSR_EL2)
3658  .hyp().mon().writes(0)
3659  .mapsTo(MISCREG_ICH_ELRSR);
3660  InitReg(MISCREG_ICH_VMCR_EL2)
3661  .hyp().mon()
3662  .mapsTo(MISCREG_ICH_VMCR);
3663  InitReg(MISCREG_ICH_LR0_EL2)
3664  .hyp().mon()
3665  .allPrivileges().exceptUserMode();
3666  InitReg(MISCREG_ICH_LR1_EL2)
3667  .hyp().mon()
3668  .allPrivileges().exceptUserMode();
3669  InitReg(MISCREG_ICH_LR2_EL2)
3670  .hyp().mon()
3671  .allPrivileges().exceptUserMode();
3672  InitReg(MISCREG_ICH_LR3_EL2)
3673  .hyp().mon()
3674  .allPrivileges().exceptUserMode();
3675  InitReg(MISCREG_ICH_LR4_EL2)
3676  .hyp().mon()
3677  .allPrivileges().exceptUserMode();
3678  InitReg(MISCREG_ICH_LR5_EL2)
3679  .hyp().mon()
3680  .allPrivileges().exceptUserMode();
3681  InitReg(MISCREG_ICH_LR6_EL2)
3682  .hyp().mon()
3683  .allPrivileges().exceptUserMode();
3684  InitReg(MISCREG_ICH_LR7_EL2)
3685  .hyp().mon()
3686  .allPrivileges().exceptUserMode();
3687  InitReg(MISCREG_ICH_LR8_EL2)
3688  .hyp().mon()
3689  .allPrivileges().exceptUserMode();
3690  InitReg(MISCREG_ICH_LR9_EL2)
3691  .hyp().mon()
3692  .allPrivileges().exceptUserMode();
3693  InitReg(MISCREG_ICH_LR10_EL2)
3694  .hyp().mon()
3695  .allPrivileges().exceptUserMode();
3696  InitReg(MISCREG_ICH_LR11_EL2)
3697  .hyp().mon()
3698  .allPrivileges().exceptUserMode();
3699  InitReg(MISCREG_ICH_LR12_EL2)
3700  .hyp().mon()
3701  .allPrivileges().exceptUserMode();
3702  InitReg(MISCREG_ICH_LR13_EL2)
3703  .hyp().mon()
3704  .allPrivileges().exceptUserMode();
3705  InitReg(MISCREG_ICH_LR14_EL2)
3706  .hyp().mon()
3707  .allPrivileges().exceptUserMode();
3708  InitReg(MISCREG_ICH_LR15_EL2)
3709  .hyp().mon()
3710  .allPrivileges().exceptUserMode();
3711 
3712  // GICv3 AArch32
3713  InitReg(MISCREG_ICC_AP0R0)
3714  .allPrivileges().exceptUserMode();
3715  InitReg(MISCREG_ICC_AP0R1)
3716  .allPrivileges().exceptUserMode();
3717  InitReg(MISCREG_ICC_AP0R2)
3718  .allPrivileges().exceptUserMode();
3719  InitReg(MISCREG_ICC_AP0R3)
3720  .allPrivileges().exceptUserMode();
3721  InitReg(MISCREG_ICC_AP1R0)
3722  .allPrivileges().exceptUserMode();
3723  InitReg(MISCREG_ICC_AP1R0_NS)
3724  .allPrivileges().exceptUserMode();
3725  InitReg(MISCREG_ICC_AP1R0_S)
3726  .allPrivileges().exceptUserMode();
3727  InitReg(MISCREG_ICC_AP1R1)
3728  .allPrivileges().exceptUserMode();
3729  InitReg(MISCREG_ICC_AP1R1_NS)
3730  .allPrivileges().exceptUserMode();
3731  InitReg(MISCREG_ICC_AP1R1_S)
3732  .allPrivileges().exceptUserMode();
3733  InitReg(MISCREG_ICC_AP1R2)
3734  .allPrivileges().exceptUserMode();
3735  InitReg(MISCREG_ICC_AP1R2_NS)
3736  .allPrivileges().exceptUserMode();
3737  InitReg(MISCREG_ICC_AP1R2_S)
3738  .allPrivileges().exceptUserMode();
3739  InitReg(MISCREG_ICC_AP1R3)
3740  .allPrivileges().exceptUserMode();
3741  InitReg(MISCREG_ICC_AP1R3_NS)
3742  .allPrivileges().exceptUserMode();
3743  InitReg(MISCREG_ICC_AP1R3_S)
3744  .allPrivileges().exceptUserMode();
3745  InitReg(MISCREG_ICC_ASGI1R)
3746  .allPrivileges().exceptUserMode().reads(0);
3747  InitReg(MISCREG_ICC_BPR0)
3748  .allPrivileges().exceptUserMode();
3749  InitReg(MISCREG_ICC_BPR1)
3750  .allPrivileges().exceptUserMode();
3751  InitReg(MISCREG_ICC_BPR1_NS)
3752  .allPrivileges().exceptUserMode();
3753  InitReg(MISCREG_ICC_BPR1_S)
3754  .allPrivileges().exceptUserMode();
3755  InitReg(MISCREG_ICC_CTLR)
3756  .allPrivileges().exceptUserMode();
3757  InitReg(MISCREG_ICC_CTLR_NS)
3758  .allPrivileges().exceptUserMode();
3759  InitReg(MISCREG_ICC_CTLR_S)
3760  .allPrivileges().exceptUserMode();
3761  InitReg(MISCREG_ICC_DIR)
3762  .allPrivileges().exceptUserMode().reads(0);
3763  InitReg(MISCREG_ICC_EOIR0)
3764  .allPrivileges().exceptUserMode().reads(0);
3765  InitReg(MISCREG_ICC_EOIR1)
3766  .allPrivileges().exceptUserMode().reads(0);
3767  InitReg(MISCREG_ICC_HPPIR0)
3768  .allPrivileges().exceptUserMode().writes(0);
3769  InitReg(MISCREG_ICC_HPPIR1)
3770  .allPrivileges().exceptUserMode().writes(0);
3771  InitReg(MISCREG_ICC_HSRE)
3772  .allPrivileges().exceptUserMode();
3773  InitReg(MISCREG_ICC_IAR0)
3774  .allPrivileges().exceptUserMode().writes(0);
3775  InitReg(MISCREG_ICC_IAR1)
3776  .allPrivileges().exceptUserMode().writes(0);
3777  InitReg(MISCREG_ICC_IGRPEN0)
3778  .allPrivileges().exceptUserMode();
3779  InitReg(MISCREG_ICC_IGRPEN1)
3780  .allPrivileges().exceptUserMode();
3781  InitReg(MISCREG_ICC_IGRPEN1_NS)
3782  .allPrivileges().exceptUserMode();
3783  InitReg(MISCREG_ICC_IGRPEN1_S)
3784  .allPrivileges().exceptUserMode();
3785  InitReg(MISCREG_ICC_MCTLR)
3786  .allPrivileges().exceptUserMode();
3787  InitReg(MISCREG_ICC_MGRPEN1)
3788  .allPrivileges().exceptUserMode();
3789  InitReg(MISCREG_ICC_MSRE)
3790  .allPrivileges().exceptUserMode();
3791  InitReg(MISCREG_ICC_PMR)
3792  .allPrivileges().exceptUserMode();
3793  InitReg(MISCREG_ICC_RPR)
3794  .allPrivileges().exceptUserMode().writes(0);
3795  InitReg(MISCREG_ICC_SGI0R)
3796  .allPrivileges().exceptUserMode().reads(0);
3797  InitReg(MISCREG_ICC_SGI1R)
3798  .allPrivileges().exceptUserMode().reads(0);
3799  InitReg(MISCREG_ICC_SRE)
3800  .allPrivileges().exceptUserMode();
3801  InitReg(MISCREG_ICC_SRE_NS)
3802  .allPrivileges().exceptUserMode();
3803  InitReg(MISCREG_ICC_SRE_S)
3804  .allPrivileges().exceptUserMode();
3805 
3806  InitReg(MISCREG_ICH_AP0R0)
3807  .hyp().mon();
3808  InitReg(MISCREG_ICH_AP0R1)
3809  .hyp().mon();
3810  InitReg(MISCREG_ICH_AP0R2)
3811  .hyp().mon();
3812  InitReg(MISCREG_ICH_AP0R3)
3813  .hyp().mon();
3814  InitReg(MISCREG_ICH_AP1R0)
3815  .hyp().mon();
3816  InitReg(MISCREG_ICH_AP1R1)
3817  .hyp().mon();
3818  InitReg(MISCREG_ICH_AP1R2)
3819  .hyp().mon();
3820  InitReg(MISCREG_ICH_AP1R3)
3821  .hyp().mon();
3822  InitReg(MISCREG_ICH_HCR)
3823  .hyp().mon();
3824  InitReg(MISCREG_ICH_VTR)
3825  .hyp().mon().writes(0);
3826  InitReg(MISCREG_ICH_MISR)
3827  .hyp().mon().writes(0);
3828  InitReg(MISCREG_ICH_EISR)
3829  .hyp().mon().writes(0);
3830  InitReg(MISCREG_ICH_ELRSR)
3831  .hyp().mon().writes(0);
3832  InitReg(MISCREG_ICH_VMCR)
3833  .hyp().mon();
3834  InitReg(MISCREG_ICH_LR0)
3835  .hyp().mon();
3836  InitReg(MISCREG_ICH_LR1)
3837  .hyp().mon();
3838  InitReg(MISCREG_ICH_LR2)
3839  .hyp().mon();
3840  InitReg(MISCREG_ICH_LR3)
3841  .hyp().mon();
3842  InitReg(MISCREG_ICH_LR4)
3843  .hyp().mon();
3844  InitReg(MISCREG_ICH_LR5)
3845  .hyp().mon();
3846  InitReg(MISCREG_ICH_LR6)
3847  .hyp().mon();
3848  InitReg(MISCREG_ICH_LR7)
3849  .hyp().mon();
3850  InitReg(MISCREG_ICH_LR8)
3851  .hyp().mon();
3852  InitReg(MISCREG_ICH_LR9)
3853  .hyp().mon();
3854  InitReg(MISCREG_ICH_LR10)
3855  .hyp().mon();
3856  InitReg(MISCREG_ICH_LR11)
3857  .hyp().mon();
3858  InitReg(MISCREG_ICH_LR12)
3859  .hyp().mon();
3860  InitReg(MISCREG_ICH_LR13)
3861  .hyp().mon();
3862  InitReg(MISCREG_ICH_LR14)
3863  .hyp().mon();
3864  InitReg(MISCREG_ICH_LR15)
3865  .hyp().mon();
3866  InitReg(MISCREG_ICH_LRC0)
3867  .mapsTo(MISCREG_ICH_LR0)
3868  .hyp().mon();
3869  InitReg(MISCREG_ICH_LRC1)
3870  .mapsTo(MISCREG_ICH_LR1)
3871  .hyp().mon();
3872  InitReg(MISCREG_ICH_LRC2)
3873  .mapsTo(MISCREG_ICH_LR2)
3874  .hyp().mon();
3875  InitReg(MISCREG_ICH_LRC3)
3876  .mapsTo(MISCREG_ICH_LR3)
3877  .hyp().mon();
3878  InitReg(MISCREG_ICH_LRC4)
3879  .mapsTo(MISCREG_ICH_LR4)
3880  .hyp().mon();
3881  InitReg(MISCREG_ICH_LRC5)
3882  .mapsTo(MISCREG_ICH_LR5)
3883  .hyp().mon();
3884  InitReg(MISCREG_ICH_LRC6)
3885  .mapsTo(MISCREG_ICH_LR6)
3886  .hyp().mon();
3887  InitReg(MISCREG_ICH_LRC7)
3888  .mapsTo(MISCREG_ICH_LR7)
3889  .hyp().mon();
3890  InitReg(MISCREG_ICH_LRC8)
3891  .mapsTo(MISCREG_ICH_LR8)
3892  .hyp().mon();
3893  InitReg(MISCREG_ICH_LRC9)
3894  .mapsTo(MISCREG_ICH_LR9)
3895  .hyp().mon();
3896  InitReg(MISCREG_ICH_LRC10)
3897  .mapsTo(MISCREG_ICH_LR10)
3898  .hyp().mon();
3899  InitReg(MISCREG_ICH_LRC11)
3900  .mapsTo(MISCREG_ICH_LR11)
3901  .hyp().mon();
3902  InitReg(MISCREG_ICH_LRC12)
3903  .mapsTo(MISCREG_ICH_LR12)
3904  .hyp().mon();
3905  InitReg(MISCREG_ICH_LRC13)
3906  .mapsTo(MISCREG_ICH_LR13)
3907  .hyp().mon();
3908  InitReg(MISCREG_ICH_LRC14)
3909  .mapsTo(MISCREG_ICH_LR14)
3910  .hyp().mon();
3911  InitReg(MISCREG_ICH_LRC15)
3912  .mapsTo(MISCREG_ICH_LR15)
3913  .hyp().mon();
3914 
3915  // SVE
3916  InitReg(MISCREG_ID_AA64ZFR0_EL1)
3917  .allPrivileges().exceptUserMode().writes(0);
3918  InitReg(MISCREG_ZCR_EL3)
3919  .mon();
3920  InitReg(MISCREG_ZCR_EL2)
3921  .hyp().mon();
3922  InitReg(MISCREG_ZCR_EL12)
3923  .monE2H()
3924  .hypE2H()
3925  .mapsTo(MISCREG_ZCR_EL1);
3926  InitReg(MISCREG_ZCR_EL1)
3927  .allPrivileges().exceptUserMode();
3928 
3929  // Dummy registers
3930  InitReg(MISCREG_NOP)
3931  .allPrivileges();
3932  InitReg(MISCREG_RAZ)
3933  .allPrivileges().exceptUserMode().writes(0);
3934  InitReg(MISCREG_UNKNOWN);
3935  InitReg(MISCREG_IMPDEF_UNIMPL)
3936  .unimplemented()
3937  .warnNotFail(impdefAsNop);
3938 
3939  // RAS extension (unimplemented)
3940  InitReg(MISCREG_ERRIDR_EL1)
3941  .unimplemented()
3942  .warnNotFail();
3943  InitReg(MISCREG_ERRSELR_EL1)
3944  .unimplemented()
3945  .warnNotFail();
3946  InitReg(MISCREG_ERXFR_EL1)
3947  .unimplemented()
3948  .warnNotFail();
3949  InitReg(MISCREG_ERXCTLR_EL1)
3950  .unimplemented()
3951  .warnNotFail();
3952  InitReg(MISCREG_ERXSTATUS_EL1)
3953  .unimplemented()
3954  .warnNotFail();
3955  InitReg(MISCREG_ERXADDR_EL1)
3956  .unimplemented()
3957  .warnNotFail();
3958  InitReg(MISCREG_ERXMISC0_EL1)
3959  .unimplemented()
3960  .warnNotFail();
3961  InitReg(MISCREG_ERXMISC1_EL1)
3962  .unimplemented()
3963  .warnNotFail();
3964  InitReg(MISCREG_DISR_EL1)
3965  .unimplemented()
3966  .warnNotFail();
3967  InitReg(MISCREG_VSESR_EL2)
3968  .unimplemented()
3969  .warnNotFail();
3970  InitReg(MISCREG_VDISR_EL2)
3971  .unimplemented()
3972  .warnNotFail();
3973 
3974  // Register mappings for some unimplemented registers:
3975  // ESR_EL1 -> DFSR
3976  // RMR_EL1 -> RMR
3977  // RMR_EL2 -> HRMR
3978  // DBGDTR_EL0 -> DBGDTR{R or T}Xint
3979  // DBGDTRRX_EL0 -> DBGDTRRXint
3980  // DBGDTRTX_EL0 -> DBGDTRRXint
3981  // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
3982 
3983  // Populate the idxToMiscRegNum map
3984  assert(idxToMiscRegNum.empty());
3985  for (const auto& [key, val] : miscRegNumToIdx) {
3986  idxToMiscRegNum.insert({val, key});
3987  }
3988 
3989  completed = true;
3990 }
3991 
3992 } // namespace ArmISA
3993 } // namespace gem5
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: misc.hh:1121
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: misc.hh:827
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:617
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:317
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:284
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: misc.hh:356
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition: misc.hh:232
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition: misc.hh:441
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1129
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:650
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:166
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition: misc.hh:390
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:246
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition: misc.hh:655
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition: misc.hh:806
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition: misc.hh:871
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1122
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:484
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:362
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:499
gem5::ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition: misc.hh:881
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: misc.hh:359
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition: misc.hh:888
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:449
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition: misc.hh:810
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:352
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:428
gem5::ArmISA::MISCREG_ICH_LR13
@ MISCREG_ICH_LR13
Definition: misc.hh:1034
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition: misc.hh:848
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition: misc.hh:846
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:231
gem5::ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition: misc.hh:526
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:96
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition: misc.hh:989
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:313
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:532
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition: misc.hh:181
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:729
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition: misc.hh:383
gem5::ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition: misc.hh:144
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:743
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:675
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:723
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H
chain monE2H(bool v=true) const
Definition: isa.hh:419
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:291
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:722
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:787
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:132
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition: misc.hh:842
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:263
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: misc.hh:730
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: misc.hh:1128
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:716
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:334
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:253
gem5::ArmISA::MISCREG_ICH_LR13_EL2
@ MISCREG_ICH_LR13_EL2
Definition: misc.hh:913
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: misc.hh:355
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition: misc.hh:154
gem5::ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition: misc.hh:839
gem5::ArmISA::MISCREG_ICH_LRC6
@ MISCREG_ICH_LRC6
Definition: misc.hh:1043
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:597
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:368
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:705
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:610
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:492
warn
#define warn(...)
Definition: logging.hh:246
gem5::ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition: misc.hh:986
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition: misc.hh:872
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:226
gem5::ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition: misc.hh:402
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: misc.hh:385
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition: misc.hh:763
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition: misc.hh:103
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:670
gem5::ArmISA::canWriteAArch64SysReg
bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: misc.cc:771
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition: misc.hh:140
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition: misc.hh:407
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition: misc.hh:973
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: misc.hh:354
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS
@ MISCREG_ICC_AP1R1_EL1_NS
Definition: misc.hh:851
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:592
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:347
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: misc.hh:382
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:678
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:298
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:802
gem5::ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition: misc.hh:889
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:289
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:401
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:591
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:771
gem5::ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition: misc.hh:122
gem5::ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition: misc.hh:436
gem5::ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition: misc.hh:979
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: misc.hh:642
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:510
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:619
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:550
gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition: misc.hh:994
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:255
gem5::ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition: misc.hh:182
gem5::ArmISA::canWriteCoprocReg
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to write coprocessor registers.
Definition: misc.cc:608
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: misc.hh:86
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:702
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:416
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:676
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition: misc.hh:813
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:170
gem5::ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition: misc.hh:890
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition: isa.hh:191
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:574
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition: misc.hh:316
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:165
gem5::ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition: misc.hh:183
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:210
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:414
gem5::ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition: misc.hh:1018
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:712
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:400
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition: isa.hh:197
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:780
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:786
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:553
gem5::ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition: misc.hh:148
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:308
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:668
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: misc.hh:85
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:773
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:329
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: misc.hh:71
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: misc.hh:651
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition: misc.hh:173
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:237
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:163
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition: misc.hh:796
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:128
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:476
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition: isa.hh:477
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:688
gem5::ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition: misc.hh:896
gem5::ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition: misc.hh:991
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:164
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:339
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:73
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition: misc.hh:430
gem5::ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition: misc.hh:537
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:311
gem5::ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition: misc.hh:149
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: misc.hh:826
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:314
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: misc.hh:718
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:348
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:667
gem5::ArmISA::MISCREG_ICH_LR6
@ MISCREG_ICH_LR6
Definition: misc.hh:1027
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition: misc.hh:857
gem5::ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition: misc.hh:422
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:620
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition: misc.hh:443
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition: misc.hh:429
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition: misc.hh:593
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:290
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1142
gem5::ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition: misc.hh:240
gem5::ArmISA::MISCREG_ICH_LRC2
@ MISCREG_ICH_LRC2
Definition: misc.hh:1039
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition: isa.hh:98
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition: misc.hh:386
gem5::ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition: misc.hh:840
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition: misc.hh:1087
gem5::ArmISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:684
gem5::ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition: misc.hh:887
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition: isa.hh:383
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:664
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:123
gem5::ArmISA::canReadAArch64SysReg
bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: misc.cc:724
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition: misc.hh:391
gem5::ArmISA::MISCREG_HYP_E2H_NS_RD
@ MISCREG_HYP_E2H_NS_RD
Definition: misc.hh:1136
gem5::ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition: misc.hh:302
gem5::ArmISA::unflattenResultMiscReg
int unflattenResultMiscReg[NUM_MISCREGS]
If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
Definition: misc.cc:699
gem5::ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:505
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1127
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:299
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition: misc.hh:405
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:494
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:346
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:692
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: misc.hh:102
gem5::ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition: misc.hh:1045
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:621
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition: misc.hh:423
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition: misc.hh:860
gem5::ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition: misc.hh:1021
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: misc.hh:829
gem5::ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition: misc.hh:380
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:600
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:261
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:697
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:703
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:644
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:338
gem5::ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition: misc.hh:882
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:410
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition: misc.hh:528
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:304
gem5::ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition: misc.hh:1026
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:247
gem5::ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition: misc.hh:632
gem5::ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition: misc.hh:114
gem5::ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition: misc.hh:911
gem5::ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition: misc.hh:374
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:645
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:696
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition: misc.hh:248
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:322
gem5::ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition: misc.hh:971
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:504
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:530
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition: misc.hh:451
gem5::ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition: misc.hh:100
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition: isa.hh:150
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: misc.hh:833
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:483
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:342
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:711
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: misc.cc:1295
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:209
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition: misc.hh:752
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:746
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:460
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:861
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:330
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition: misc.hh:803
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:611
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:554
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition: misc.hh:109
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition: misc.hh:271
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:332
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition: isa.hh:447
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:555
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:159
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition: misc.hh:734
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition: misc.hh:256
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:224
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:351
gem5::ArmISA::MISCREG_ICH_LRC5
@ MISCREG_ICH_LRC5
Definition: misc.hh:1042
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition: misc.hh:909
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition: misc.hh:424
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:87
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:219
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:168
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition: misc.hh:733
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:84
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:188
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition: misc.hh:993
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:502
gem5::ArmISA::MISCREG_ICH_LR2
@ MISCREG_ICH_LR2
Definition: misc.hh:1023
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition: misc.hh:997
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:367
gem5::ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition: misc.hh:1013
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:727
gem5::ArmISA::MISCREG_ICH_LR1_EL2
@ MISCREG_ICH_LR1_EL2
Definition: misc.hh:901
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: misc.hh:364
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:319
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:371
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition: misc.hh:372
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:222
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:310
gem5::ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition: misc.hh:418
gem5::ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition: misc.hh:113
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: misc.hh:616
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:717
gem5::ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition: misc.hh:999
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition: misc.hh:270
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:915
gem5::ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition: misc.hh:807
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: misc.hh:88
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:721
gem5::ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition: misc.hh:294
gem5::ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition: misc.hh:442
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition: misc.hh:276
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition: misc.hh:767
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition: misc.hh:809
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:565
gem5::ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition: misc.hh:985
gem5::ArmISA::MISCREG_ICH_LR3
@ MISCREG_ICH_LR3
Definition: misc.hh:1024
gem5::ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition: misc.hh:812
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:236
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition: misc.hh:187
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1124
gem5::ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition: misc.hh:1007
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:656
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:707
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:960
gem5::ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition: misc.hh:241
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition: misc.hh:381
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:162
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:750
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:417
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:474
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:704
gem5::ArmISA::MISCREG_ICH_LR12_EL2
@ MISCREG_ICH_LR12_EL2
Definition: misc.hh:912
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition: misc.hh:849
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition: misc.hh:110
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:200
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition: misc.hh:765
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:217
gem5::ArmISA::MISCREG_ICH_LR12
@ MISCREG_ICH_LR12
Definition: misc.hh:1033
gem5::ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition: misc.hh:768
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition: misc.hh:531
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:138
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition: misc.hh:770
gem5::ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition: misc.hh:1031
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition: misc.hh:78
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition: utility.cc:902
gem5::ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition: misc.hh:967
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:203
gem5::ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition: misc.hh:735
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:607
gem5::ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition: misc.hh:895
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:129
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition: misc.hh:176
gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition: misc.hh:841
gem5::ArmISA::MISCREG_ICH_LRC1
@ MISCREG_ICH_LRC1
Definition: misc.hh:1038
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:701
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:806
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:513
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition: misc.hh:534
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:266
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:252
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:500
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:158
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:221
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:769
gem5::ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition: misc.hh:1009
gem5::ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition: misc.hh:264
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition: misc.hh:175
gem5::ArmISA::MISCREG_ICC_SRE_NS
@ MISCREG_ICC_SRE_NS
Definition: misc.hh:1004
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition: misc.hh:992
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:104
gem5::ArmISA::MISCREG_ICC_AP1R2_S
@ MISCREG_ICC_AP1R2_S
Definition: misc.hh:972
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:815
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition: misc.hh:458
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:192
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:218
gem5::ArmISA::decodeCP14Reg
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:517
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:272
gem5::ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition: misc.hh:988
gem5::ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition: misc.hh:904
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: misc.hh:834
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:333
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: misc.hh:601
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition: misc.hh:1037
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition: misc.hh:1012
gem5::ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:238
gem5::ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition: misc.hh:151
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: misc.hh:535
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition: misc.hh:858
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:522
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:777
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:774
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition: misc.hh:894
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:543
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition: isa.hh:185
gem5::ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition: misc.hh:297
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition: misc.hh:450
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition: misc.hh:1080
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition: misc.hh:996
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:434
gem5::ArmISA::MISCREG_NOP
@ MISCREG_NOP
Definition: misc.hh:1069
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition: misc.hh:847
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:615
gem5::ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition: misc.hh:900
gem5::ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition: misc.hh:1011
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:332
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:340
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:533
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:124
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:370
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:473
gem5::ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition: misc.hh:98
gem5::ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition: misc.hh:998
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:171
gem5::ArmISA::canReadCoprocReg
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to read coprocessor registers.
Definition: misc.cc:562
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition: misc.hh:792
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition: misc.hh:736
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:155
gem5::ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition: misc.hh:844
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:739
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:131
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::writes
chain writes(bool v) const
Definition: isa.hh:532
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:133
gem5::ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition: misc.hh:859
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition: isa.hh:209
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:169
gem5::ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition: misc.hh:1016
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:464
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition: misc.hh:389
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:307
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: misc.hh:581
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition: misc.hh:1079
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:509
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition: misc.hh:404
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:126
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: misc.hh:584
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:580
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:823
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:223
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1052
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition: misc.hh:300
gem5::ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition: misc.hh:525
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:549
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition: isa.hh:203
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: misc.hh:353
gem5::ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition: misc.hh:910
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition: misc.hh:817
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:225
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: misc.hh:603
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:454
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: misc.hh:747
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition: misc.hh:195
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition: isa.hh:433
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:137
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition: misc.hh:152
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:395
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition: misc.hh:254
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition: misc.hh:808
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:726
gem5::ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition: misc.hh:1086
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:493
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition: misc.hh:301
gem5::ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition: misc.hh:811
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:814
gem5::ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition: misc.hh:145
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:160
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:357
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:379
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:542
gem5::ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition: misc.hh:629
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:415
gem5::ArmISA::MISCREG_ICC_AP1R1_NS
@ MISCREG_ICC_AP1R1_NS
Definition: misc.hh:968
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:732
gem5::ArmISA::decodeCP15Reg64
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition: misc.cc:550
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition: misc.hh:852
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:75
gem5::ArmISA::MISCREG_TPIDRURW
@ MISCREG_TPIDRURW
Definition: misc.hh:403
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition: misc.hh:179
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:661
gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition: misc.hh:874
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:776
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:566
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
isa.hh
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: misc.hh:785
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:799
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:279
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: isa.hh:143
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:469
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S
@ MISCREG_ICC_AP1R2_EL1_S
Definition: misc.hh:855
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:74
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition: misc.hh:448
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition: misc.hh:233
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:433
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:491
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1145
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:454
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:293
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:862
gem5::ArmISA::MISCREG_ICC_AP1R3_NS
@ MISCREG_ICC_AP1R3_NS
Definition: misc.hh:974
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition: misc.hh:772
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:724
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:235
gem5::ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:654
gem5::ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition: misc.hh:1088
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:344
gem5::ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition: misc.hh:1008
gem5::ArmISA::MISCREG_HYP_E2H_S_RD
@ MISCREG_HYP_E2H_S_RD
Definition: misc.hh:1138
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:193
gem5::ArmISA::MISCREG_ICH_LR4
@ MISCREG_ICH_LR4
Definition: misc.hh:1025
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition: misc.hh:388
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition: misc.hh:277
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:508
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:318
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:883
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: misc.hh:1144
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:583
gem5::ArmISA::MISCREG_HYP_S_RD
@ MISCREG_HYP_S_RD
Definition: misc.hh:1133
gem5::ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition: misc.hh:1022
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition: misc.hh:180
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:527
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:320
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_ICH_LRC10
@ MISCREG_ICH_LRC10
Definition: misc.hh:1047
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:134
gem5::ArmISA::MISCREG_ICH_LR5_EL2
@ MISCREG_ICH_LR5_EL2
Definition: misc.hh:905
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:552
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition: misc.hh:115
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:264
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: misc.hh:365
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:618
gem5::ArmISA::MISCREG_TPIDRURO
@ MISCREG_TPIDRURO
Definition: misc.hh:406
gem5::ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition: misc.hh:891
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition: misc.hh:285
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition: misc.hh:1019
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_RAZ
@ MISCREG_RAZ
Definition: misc.hh:1070
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:239
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition: misc.hh:150
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:287
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition: misc.hh:868
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition: misc.hh:1082
gem5::ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition: misc.hh:865
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:628
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_ICC_AP1R1_S
@ MISCREG_ICC_AP1R1_S
Definition: misc.hh:969
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:976
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition: misc.hh:267
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:397
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:742
gem5::ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition: misc.hh:281
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition: misc.hh:153
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:558
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:215
gem5::ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition: misc.hh:867
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: misc.hh:835
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:206
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: misc.hh:832
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition: misc.hh:197
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:479
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition: misc.hh:273
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:714
gem5::ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition: misc.hh:899
gem5::ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition: misc.hh:186
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:461
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: misc.hh:295
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition: misc.hh:420
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: misc.hh:1109
gem5::ArmISA::MISCREG_TLBINEEDSYNC
@ MISCREG_TLBINEEDSYNC
Definition: misc.hh:93
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:775
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition: misc.hh:766
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition: isa.hh:470
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition: misc.hh:440
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition: isa.hh:391
gem5::ArmISA::MISCREG_ICC_SRE_S
@ MISCREG_ICC_SRE_S
Definition: misc.hh:1005
gem5::ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition: misc.hh:892
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:191
gem5::ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition: misc.hh:995
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:213
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: misc.hh:828
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition: isa.hh:215
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_ICH_LR2_EL2
@ MISCREG_ICH_LR2_EL2
Definition: misc.hh:902
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition: misc.hh:879
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:290
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition: misc.hh:1058
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:744
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1002
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: misc.hh:1126
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition: misc.hh:869
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:394
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:575
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:208
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:135
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:335
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition: misc.hh:296
gem5::ArmISA::MISCREG_HYP_E2H_NS_WR
@ MISCREG_HYP_E2H_NS_WR
Definition: misc.hh:1137
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition: misc.hh:196
gem5::ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition: misc.hh:120
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:377
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: misc.hh:82
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:795
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition: misc.hh:432
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:190
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:269
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:376
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition: misc.hh:893
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: misc.hh:831
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition: misc.hh:177
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:475
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:720
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition: misc.hh:437
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unimplemented
chain unimplemented() const
Definition: isa.hh:180
gem5::ArmISA::encodeAArch64SysReg
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg)
Definition: misc.cc:1314
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:258
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition: misc.hh:745
gem5::ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition: misc.hh:375
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:1325
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:289
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: misc.hh:639
gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition: misc.hh:876
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition: misc.hh:412
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:635
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1055
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:156
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition: misc.hh:257
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:751
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:503
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:699
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition: misc.hh:657
gem5::ArmISA::MISCREG_ICH_LRC13
@ MISCREG_ICH_LRC13
Definition: misc.hh:1050
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:480
full_system.hh
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:373
gem5::ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition: misc.hh:1048
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::reads
chain reads(bool v) const
Definition: isa.hh:520
gem5::ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition: misc.hh:143
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:684
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition: misc.hh:856
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:245
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:129
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_HYP_S_WR
@ MISCREG_HYP_S_WR
Definition: misc.hh:1134
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition: misc.hh:647
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition: misc.hh:121
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition: misc.hh:625
gem5::ArmISA::MISCREG_ICC_SRE_EL1_S
@ MISCREG_ICC_SRE_EL1_S
Definition: misc.hh:875
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition: misc.hh:447
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:127
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition: misc.hh:142
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: misc.hh:1141
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: misc.hh:366
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition: misc.hh:631
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:324
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition: misc.hh:805
gem5::ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition: misc.hh:524
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:789
gem5::ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition: misc.hh:630
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition: misc.hh:1036
gem5::ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition: misc.hh:966
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:309
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:230
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:633
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:161
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1001
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition: misc.hh:393
gem5::ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition: misc.hh:897
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition: misc.hh:804
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: misc.hh:830
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:278
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:81
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:303
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:306
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:468
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:207
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1092
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:498
gem5::ArmISA::MiscRegNum64
Definition: misc.hh:1214
gem5::ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition: misc.hh:106
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:199
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:331
gem5::ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition: misc.hh:982
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition: misc.hh:185
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:249
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:286
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition: misc.hh:984
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: misc.hh:863
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:343
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:321
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:275
gem5::ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition: misc.hh:962
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: misc.hh:363
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition: misc.hh:963
gem5::ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition: misc.hh:274
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:262
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition: misc.hh:648
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:312
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition: misc.hh:279
gem5::ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition: misc.hh:1029
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition: misc.hh:431
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition: misc.hh:816
gem5::ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition: misc.hh:1003
gem5::ArmISA::MISCREG_ICH_LR8_EL2
@ MISCREG_ICH_LR8_EL2
Definition: misc.hh:908
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: misc.hh:80
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:677
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition: isa.hh:561
gem5::ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition: misc.hh:408
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1059
gem5::ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition: misc.hh:1089
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:886
gem5::ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition: misc.hh:446
gem5::ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition: misc.hh:119
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition: misc.hh:898
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition: misc.hh:624
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:784
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:349
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition: misc.hh:1020
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition: misc.hh:873
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition: misc.hh:1015
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:125
gem5::ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition: misc.hh:147
gem5::ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition: misc.hh:384
misc.hh
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:467
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:514
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition: misc.hh:794
gem5::ArmISA::MISCREG_ICH_LRC3
@ MISCREG_ICH_LRC3
Definition: misc.hh:1040
gem5::ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition: misc.hh:421
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS
@ MISCREG_ICC_AP1R2_EL1_NS
Definition: misc.hh:854
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:189
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition: misc.hh:141
gem5::ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition: misc.hh:411
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:838
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition: misc.hh:280
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
gem5::ArmISA::MISCREG_ICC_AP1R0_NS
@ MISCREG_ICC_AP1R0_NS
Definition: misc.hh:965
gem5::ArmISA::MISCREG_ICC_CTLR_S
@ MISCREG_ICC_CTLR_S
Definition: misc.hh:983
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:548
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:649
gem5::ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition: misc.hh:1071
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition: misc.hh:1010
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:778
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:627
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:212
gem5::ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition: misc.hh:315
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:495
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:296
gem5::ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition: misc.hh:609
gem5::ArmISA::MISCREG_ICH_LR9
@ MISCREG_ICH_LR9
Definition: misc.hh:1030
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:798
gem5::ArmISA::MISCREG_ICH_LR3_EL2
@ MISCREG_ICH_LR3_EL2
Definition: misc.hh:903
logging.hh
gem5::ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition: misc.hh:172
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition: misc.hh:105
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:579
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: misc.hh:728
gem5::ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition: misc.hh:990
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:800
gem5::ArmISA::MISCREG_ICH_LRC4
@ MISCREG_ICH_LRC4
Definition: misc.hh:1041
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition: misc.hh:101
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:791
gem5::ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition: misc.hh:981
gem5::ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition: misc.hh:977
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:708
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:211
gem5::ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition: misc.hh:378
gem5::ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition: misc.hh:870
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:779
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition: misc.hh:864
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition: misc.hh:457
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition: misc.hh:1085
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:623
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1056
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition: misc.hh:117
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:466
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:398
gem5::ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:666
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: misc.hh:1123
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:392
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:636
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:361
gem5::ArmISA::MISCREG_ICH_LR11
@ MISCREG_ICH_LR11
Definition: misc.hh:1032
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:283
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition: misc.hh:961
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: misc.hh:637
gem5::ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition: misc.hh:178
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:227
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: misc.hh:198
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:634
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:818
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition: misc.hh:268
gem5::ArmISA::MISCREG_HYP_E2H_S_WR
@ MISCREG_HYP_E2H_S_WR
Definition: misc.hh:1139
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition: misc.hh:288
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:425
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:577
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition: misc.hh:259
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition: misc.hh:1044
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:658
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition: misc.hh:107
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition: misc.hh:749
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:719
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: misc.hh:358
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:669
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:400
gem5::ArmISA::MISCREG_ICH_LRC14
@ MISCREG_ICH_LRC14
Definition: misc.hh:1051
gem5::ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition: misc.hh:260
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:157
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:465
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:323
gem5::ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition: misc.hh:880
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:131
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:293
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:674
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition: misc.hh:445
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition: misc.hh:845
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:638
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:695
gem5::ArmISA::MISCREG_VSTTBR_EL2
@ MISCREG_VSTTBR_EL2
Definition: misc.hh:608
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:336
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:305
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:598
gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition: misc.hh:866
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: misc.hh:1076
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:710
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition: isa.hh:279
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:700
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:337
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1057
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:801
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: misc.hh:91
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition: misc.hh:111
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:654
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:685
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:471
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:97
gem5::ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition: misc.hh:980
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:194
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:167
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:653
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:325
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_ICH_LR14
@ MISCREG_ICH_LR14
Definition: misc.hh:1035
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:646
gem5::ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition: misc.hh:907
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: misc.hh:599
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: misc.hh:360
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:426
gem5::ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition: misc.hh:419
gem5::ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition: misc.hh:1081
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:725
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:350
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:89
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:782
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition: misc.hh:877
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition: misc.hh:184
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:292
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition: misc.hh:1084
gem5::ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition: misc.hh:764
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:640
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition: misc.hh:1014
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition: misc.hh:748
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:216
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition: misc.hh:146
gem5::ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition: misc.hh:914
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition: misc.hh:878
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: misc.hh:612
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:679
gem5::ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition: misc.hh:987
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:737
gem5::ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition: misc.hh:970
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:706
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition: misc.hh:387
gem5::ArmISA::MISCREG_TPIDRPRW
@ MISCREG_TPIDRPRW
Definition: misc.hh:409
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:715
gem5::ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition: misc.hh:438
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:497
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: misc.hh:641
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition: misc.hh:118
gem5::ArmISA::MISCREG_MON_E2H_RD
@ MISCREG_MON_E2H_RD
Definition: misc.hh:1147
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:242
gem5::ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition: misc.hh:439
gem5::ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:531
gem5::ArmISA::MISCREG_MON_E2H_WR
@ MISCREG_MON_E2H_WR
Definition: misc.hh:1148
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:551
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:456
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:501
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:489
gem5::ArmISA::MiscRegNum32
Definition: misc.hh:1155
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: misc.hh:738
gem5::ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition: misc.hh:1028
gem5::ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition: misc.hh:978
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition: misc.hh:793
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: misc.cc:702
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition: misc.hh:536
gem5::ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition: misc.hh:1000
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:130
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: misc.hh:1115
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition: misc.hh:1131
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:740
thread_context.hh
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:659
gem5::ArmISA::MISCREG_ICC_AP1R3_S
@ MISCREG_ICC_AP1R3_S
Definition: misc.hh:975
gem5::ArmISA::MISCREG_ICH_LRC12
@ MISCREG_ICH_LRC12
Definition: misc.hh:1049
gem5::ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition: misc.hh:1017
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:573
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:472
gem5::ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition: misc.hh:99
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:821
gem5::ArmISA::MISCREG_UAO
@ MISCREG_UAO
Definition: misc.hh:1093
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:214
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:136
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: misc.hh:614
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: misc.hh:713
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_ICH_LRC9
@ MISCREG_ICH_LRC9
Definition: misc.hh:1046
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:797
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition: misc.hh:112
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition: misc.hh:108
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:341
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:328
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:694
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:718
gem5::ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition: misc.hh:843
gem5::ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition: misc.hh:174
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:139
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition: misc.hh:444
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:602
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:462
gem5::ArmISA::ISA::impdefAsNop
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
Definition: isa.hh:104
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition: misc.hh:369
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition: misc.hh:116
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:693
gem5::ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition: misc.hh:964
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:470
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:523
gem5::ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition: misc.hh:906
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:709
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition: misc.hh:850
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition: misc.hh:853
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:762
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:79
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1132
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition: misc.hh:1083
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:496
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