gem5  v22.0.0.1
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gem5::ThreadContext Class Referenceabstract

ThreadContext is the external interface to all thread state for anything outside of the CPU. More...

#include <thread_context.hh>

Inheritance diagram for gem5::ThreadContext:
gem5::PCEventScope gem5::CheckerThreadContext< TC > gem5::Iris::ThreadContext gem5::o3::ThreadContext gem5::SimpleThread gem5::fastmodel::CortexA76TC gem5::fastmodel::CortexR52TC

Public Types

enum  Status { Active, Suspended, Halting, Halted }
 

Public Member Functions

bool getUseForClone ()
 
void setUseForClone (bool new_val)
 
virtual ~ThreadContext ()
 
virtual BaseCPU * getCpuPtr ()=0
 
virtual int cpuId () const =0
 
virtual uint32_t socketId () const =0
 
virtual int threadId () const =0
 
virtual void setThreadId (int id)=0
 
virtual ContextID contextId () const =0
 
virtual void setContextId (ContextID id)=0
 
virtual BaseMMU * getMMUPtr ()=0
 
virtual CheckerCPU * getCheckerCpuPtr ()=0
 
virtual BaseISA * getIsaPtr () const =0
 
virtual InstDecoder * getDecoderPtr ()=0
 
virtual System * getSystemPtr ()=0
 
virtual void sendFunctional (PacketPtr pkt)
 
virtual Process * getProcessPtr ()=0
 
virtual void setProcessPtr (Process *p)=0
 
virtual Status status () const =0
 
virtual void setStatus (Status new_status)=0
 
virtual void activate ()=0
 Set the status to Active. More...
 
virtual void suspend ()=0
 Set the status to Suspended. More...
 
virtual void halt ()=0
 Set the status to Halted. More...
 
void quiesce ()
 Quiesce thread context. More...
 
void quiesceTick (Tick resume)
 Quiesce, suspend, and schedule activate at resume. More...
 
virtual void takeOverFrom (ThreadContext *old_context)=0
 
virtual void regStats (const std::string &name)
 
virtual void scheduleInstCountEvent (Event *event, Tick count)=0
 
virtual void descheduleInstCountEvent (Event *event)=0
 
virtual Tick getCurrentInstCount ()=0
 
virtual Tick readLastActivate ()=0
 
virtual Tick readLastSuspend ()=0
 
virtual void copyArchRegs (ThreadContext *tc)=0
 
virtual void clearArchRegs ()=0
 
virtual RegVal getReg (const RegId &reg) const
 
virtual void getReg (const RegId &reg, void *val) const
 
virtual void * getWritableReg (const RegId &reg)
 
virtual void setReg (const RegId &reg, RegVal val)
 
virtual void setReg (const RegId &reg, const void *val)
 
RegVal readIntReg (RegIndex reg_idx) const
 
RegVal readFloatReg (RegIndex reg_idx) const
 
TheISA::VecRegContainer readVecReg (const RegId &reg) const
 
TheISA::VecRegContainer & getWritableVecReg (const RegId &reg)
 
RegVal readVecElem (const RegId &reg) const
 
RegVal readCCReg (RegIndex reg_idx) const
 
void setIntReg (RegIndex reg_idx, RegVal val)
 
void setFloatReg (RegIndex reg_idx, RegVal val)
 
void setVecReg (const RegId &reg, const TheISA::VecRegContainer &val)
 
void setVecElem (const RegId &reg, RegVal val)
 
void setCCReg (RegIndex reg_idx, RegVal val)
 
virtual const PCStateBase & pcState () const =0
 
virtual void pcState (const PCStateBase &val)=0
 
void pcState (Addr addr)
 
virtual void pcStateNoRecord (const PCStateBase &val)=0
 
virtual RegVal readMiscRegNoEffect (RegIndex misc_reg) const =0
 
virtual RegVal readMiscReg (RegIndex misc_reg)=0
 
virtual void setMiscRegNoEffect (RegIndex misc_reg, RegVal val)=0
 
virtual void setMiscReg (RegIndex misc_reg, RegVal val)=0
 
virtual RegId flattenRegId (const RegId &reg_id) const =0
 
virtual unsigned readStCondFailures () const =0
 
virtual void setStCondFailures (unsigned sc_failures)=0
 
virtual int exit ()
 
virtual void htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause)=0
 
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr ()=0
 
virtual void setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt)=0
 
virtual RegVal getRegFlat (const RegId &reg) const
 Flat register interfaces. More...
 
virtual void getRegFlat (const RegId &reg, void *val) const =0
 
virtual void * getWritableRegFlat (const RegId &reg)=0
 
virtual void setRegFlat (const RegId &reg, RegVal val)
 
virtual void setRegFlat (const RegId &reg, const void *val)=0
 
RegVal readIntRegFlat (RegIndex idx) const
 
void setIntRegFlat (RegIndex idx, RegVal val)
 
RegVal readFloatRegFlat (RegIndex idx) const
 
void setFloatRegFlat (RegIndex idx, RegVal val)
 
TheISA::VecRegContainer readVecRegFlat (RegIndex idx) const
 
TheISA::VecRegContainer & getWritableVecRegFlat (RegIndex idx)
 
void setVecRegFlat (RegIndex idx, const TheISA::VecRegContainer &val)
 
RegVal readVecElemFlat (RegIndex idx) const
 
void setVecElemFlat (RegIndex idx, RegVal val)
 
RegVal readCCRegFlat (RegIndex idx) const
 
void setCCRegFlat (RegIndex idx, RegVal val)
 
- Public Member Functions inherited from gem5::PCEventScope
virtual bool remove (PCEvent *event)=0
 
virtual bool schedule (PCEvent *event)=0
 

Static Public Member Functions

static void compare (ThreadContext *one, ThreadContext *two)
 function to compare two thread contexts (for debugging) More...
 

Public Attributes

int intResult = DefaultIntResult
 
double floatResult = DefaultFloatResult
 
int intOffset = 0
 

Static Public Attributes

static const int ints []
 
static const double floats []
 
static const int DefaultIntResult = 0
 
static const double DefaultFloatResult = 0.0
 

Protected Attributes

bool useForClone = false
 

Detailed Description

ThreadContext is the external interface to all thread state for anything outside of the CPU.

It provides all accessor methods to state that might be needed by external objects, ranging from register values to things such as kernel stats. It is an abstract base class; the CPU can create its own ThreadContext by deriving from it.

The ThreadContext is slightly different than the ExecContext. The ThreadContext provides access to an individual thread's state; an ExecContext provides ISA access to the CPU (meaning it is implicitly multithreaded on SMT systems). Additionally the ThreadState is an abstract class that exactly defines the interface; the ExecContext is a more implicit interface that must be implemented so that the ISA can access whatever state it needs.

Definition at line 94 of file thread_context.hh.

Member Enumeration Documentation

◆ Status

enum gem5::ThreadContext::Status
Enumerator
Active 

Running.

Instructions should be executed only when the context is in this state.

Suspended 

Temporarily inactive.

Entered while waiting for synchronization, etc.

Halting 

Trying to exit and waiting for an event to completely exit.

Entered when target executes an exit syscall.

Halted 

Permanently shut down.

Entered when target executes m5exit pseudo-instruction. When all contexts enter this state, the simulation will terminate.

Definition at line 105 of file thread_context.hh.

Constructor & Destructor Documentation

◆ ~ThreadContext()

virtual gem5::ThreadContext::~ThreadContext ( )
inlinevirtual

Reimplemented in gem5::Iris::ThreadContext.

Definition at line 125 of file thread_context.hh.

Member Function Documentation

◆ activate()

virtual void gem5::ThreadContext::activate ( )
pure virtual

Set the status to Active.

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::cloneFunc(), gem5::execveFunc(), gem5::exitImpl(), gem5::Process::initState(), gem5::System::Threads::Thread::resume(), gem5::SyscallDesc::retrySyscall(), gem5::GPUComputeDriver::signalWakeupEvent(), gem5::FVPBasePwrCtrl::startCoreUp(), gem5::pseudo_inst::wakeCPU(), and gem5::FutexMap::wakeup_bitset().

◆ clearArchRegs()

virtual void gem5::ThreadContext::clearArchRegs ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::cloneFunc(), gem5::execveFunc(), and gem5::ArmISA::Reset::invoke().

◆ compare()

void gem5::ThreadContext::compare ( ThreadContext *  one,
ThreadContext *  two 
)
static

function to compare two thread contexts (for debugging)

Definition at line 61 of file thread_context.cc.

References gem5::CCRegClass, contextId(), cpuId(), DPRINTF, gem5::FloatRegClass, getReg(), gem5::ArmISA::i, gem5::IntRegClass, gem5::MiscRegClass, gem5::ps2::one, panic, pcState(), readCCReg(), readFloatReg(), readIntReg(), readMiscRegNoEffect(), gem5::ArmISA::t1, gem5::ArmISA::t2, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ contextId()

virtual ContextID gem5::ThreadContext::contextId ( ) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::BaseRemoteGDB::addThreadContext(), gem5::FVPBasePwrCtrl::clearStandByWfi(), gem5::FVPBasePwrCtrl::clearWakeRequest(), gem5::Process::clone(), gem5::cloneFunc(), gem5::BaseRemoteGDB::cmdSetThread(), compare(), gem5::SimpleThread::copyState(), gem5::BaseKvmCPU::doMMIOAccess(), gem5::execveFunc(), gem5::X86ISA::TLB::finalizePhysical(), gem5::CheckerCPU::genMemFragmentRequest(), gem5::ArmPPIGen::get(), gem5::FVPBasePwrCtrl::getCorePwrStatus(), gem5::getcpuFunc(), gem5::ArmISA::ISA::getGenericTimer(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::RiscvISA::ISA::handleLockedRead(), gem5::RiscvISA::ISA::handleLockedSnoop(), gem5::RiscvISA::ISA::handleLockedWrite(), gem5::BaseRemoteGDB::incomingData(), gem5::PowerISA::UnimplementedOpcodeFault::invoke(), gem5::PowerISA::AlignmentFault::invoke(), gem5::PowerISA::TrapFault::invoke(), gem5::GenericPageTableFault::invoke(), gem5::GenericAlignmentFault::invoke(), gem5::ArmISA::lockedWriteHandler(), gem5::FVPBasePwrCtrl::powerCoreOff(), gem5::FVPBasePwrCtrl::powerCoreOn(), gem5::HardBreakpoint::process(), gem5::BaseRemoteGDB::queryC(), quiesce(), quiesceTick(), gem5::SparcISA::ISA::readFSReg(), gem5::X86ISA::ISA::readMiscReg(), gem5::RiscvISA::ISA::readMiscReg(), gem5::Workload::registerThreadContext(), gem5::Workload::replaceThreadContext(), gem5::FVPBasePwrCtrl::setStandByWfi(), gem5::ArmISA::PMU::setThreadContext(), gem5::ArmISA::ISA::setupThreadContext(), gem5::FVPBasePwrCtrl::setWakeRequest(), gem5::BaseRemoteGDB::singleStep(), gem5::FVPBasePwrCtrl::startCoreUp(), gem5::takeOverFrom(), gem5::ArmInterruptPin::targetContext(), gem5::X86ISA::GpuTLB::translate(), and gem5::ArmISA::MMU::updateMiscReg().

◆ copyArchRegs()

virtual void gem5::ThreadContext::copyArchRegs ( ThreadContext *  tc)
pure virtual

Implemented in gem5::SimpleThread, gem5::CheckerThreadContext< TC >, gem5::Iris::ThreadContext, and gem5::o3::ThreadContext.

Referenced by gem5::takeOverFrom().

◆ cpuId()

virtual int gem5::ThreadContext::cpuId ( ) const
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::cloneFunc(), compare(), gem5::ArmISA::getAff0(), gem5::ArmISA::getAff1(), gem5::ArmISA::getMPIDR(), gem5::GPUComputeDriver::ioctl(), gem5::ArmISA::DumpStats::process(), gem5::X86ISA::Interrupts::setThreadContext(), gem5::GPUComputeDriver::signalWakeupEvent(), gem5::GPUComputeDriver::sleepCPU(), and gem5::Trace::InstPBTrace::traceInst().

◆ descheduleInstCountEvent()

virtual void gem5::ThreadContext::descheduleInstCountEvent ( Event *  event)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::BaseRemoteGDB::descheduleInstCommitEvent().

◆ exit()

virtual int gem5::ThreadContext::exit ( )
inlinevirtual

Definition at line 301 of file thread_context.hh.

◆ flattenRegId()

virtual RegId gem5::ThreadContext::flattenRegId ( const RegId &  reg_id) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

Referenced by gem5::minor::flattenRegIndex(), getReg(), getWritableReg(), gem5::o3::Rename::renameDestRegs(), gem5::o3::Rename::renameSrcRegs(), and setReg().

◆ getCheckerCpuPtr()

virtual CheckerCPU* gem5::ThreadContext::getCheckerCpuPtr ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::TLBIALLEL::operator()(), gem5::ArmISA::TLBIVMALL::operator()(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::TLBIALLN::operator()(), gem5::ArmISA::TLBIMVAA::operator()(), gem5::ArmISA::TLBIMVA::operator()(), gem5::ArmISA::TLBIIPA::operator()(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), and gem5::ArmISA::ISA::setMiscReg().

◆ getCpuPtr()

virtual BaseCPU* gem5::ThreadContext::getCpuPtr ( )
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::SparcISA::ISA::checkSoftInt(), gem5::Linux::devRandom(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::BaseStackTrace::dump(), gem5::pseudo_inst::dumpresetstats(), gem5::pseudo_inst::dumpstats(), gem5::ArmISA::TableWalker::fetchDescriptor(), gem5::ArmISA::TableWalker::Stage2Walk::finish(), gem5::RiscvISA::ISA::globalClearExclusive(), gem5::ArmISA::ISA::handleLockedRead(), gem5::ArmISA::ISA::handleLockedSnoopHit(), gem5::pseudo_inst::initParam(), gem5::RiscvISA::RiscvFault::invoke(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::AbortFault< DataAbort >::invoke(), gem5::ArmISA::SystemError::invoke(), gem5::ArmISA::ArmSev::invoke(), gem5::pseudo_inst::loadsymbol(), gem5::ArmISA::lockedSnoopHandler(), gem5::ArmISA::lockedWriteHandler(), gem5::pseudo_inst::m5checkpoint(), gem5::Linux::openSpecialFile(), gem5::FVPBasePwrCtrl::powerCoreOff(), gem5::FVPBasePwrCtrl::powerCoreOn(), gem5::ArmISA::DumpStats::process(), gem5::SparcISA::ISA::processHSTickCompare(), gem5::SparcISA::ISA::processSTickCompare(), gem5::pseudo_inst::quiesceCycles(), gem5::pseudo_inst::quiesceSkip(), gem5::X86ISA::ISA::readMiscReg(), gem5::RiscvISA::ISA::readMiscReg(), gem5::SparcISA::ISA::readMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::MipsISA::readRegOtherThread(), gem5::System::Threads::replace(), gem5::pseudo_inst::resetstats(), gem5::System::Threads::Thread::resume(), gem5::ArmISA::sendEvent(), sendFunctional(), gem5::SparcISA::ISA::setFSReg(), gem5::X86ISA::ISA::setMiscReg(), gem5::RiscvISA::ISA::setMiscReg(), gem5::MipsISA::ISA::setMiscReg(), gem5::SparcISA::ISA::setMiscReg(), gem5::MipsISA::setRegOtherThread(), gem5::SyscallDesc::setupRetry(), gem5::Trace::TarmacContext::tarmacCpuName(), gem5::pseudo_inst::workbegin(), and gem5::pseudo_inst::workend().

◆ getCurrentInstCount()

virtual Tick gem5::ThreadContext::getCurrentInstCount ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::BaseRemoteGDB::scheduleInstCommitEvent().

◆ getDecoderPtr()

virtual InstDecoder* gem5::ThreadContext::getDecoderPtr ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::minor::Fetch2::evaluate(), gem5::GenericHtmFailureFault::invoke(), gem5::SparcISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::X86ISA::ISA::setThreadContext(), gem5::SimpleThread::takeOverFrom(), gem5::o3::ThreadContext::takeOverFrom(), and gem5::X86ISA::ISA::updateHandyM5Reg().

◆ getHtmCheckpointPtr()

virtual BaseHTMCheckpointPtr& gem5::ThreadContext::getHtmCheckpointPtr ( )
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::SimpleExecContext::getHtmTransactionUid(), gem5::o3::LSQUnit::getLatestHtmUid(), gem5::o3::LSQUnit::insertLoad(), gem5::GenericHtmFailureFault::invoke(), gem5::SimpleExecContext::newHtmTransactionUid(), and gem5::o3::LSQUnit::squash().

◆ getIsaPtr()

virtual BaseISA* gem5::ThreadContext::getIsaPtr ( ) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::ArmLinux::archClone(), gem5::X86Linux::archClone(), gem5::RiscvLinux64::archClone(), gem5::SparcLinux::archClone(), gem5::PowerLinux::archClone(), gem5::RiscvLinux32::archClone(), gem5::MiscRegOp64::checkEL2Trap(), gem5::memory::AbstractMemory::checkLockedAddrList(), gem5::o3::LSQUnit::checkSnoop(), gem5::o3::Commit::clearStates(), gem5::X86ISA::doCpuid(), gem5::ArmISA::ArmStaticInst::getCurSveVecLenInBits(), gem5::ArmISA::ISA::getSelfDebug(), gem5::ArmISA::HaveExt(), gem5::CheckerCPU::init(), gem5::GenericHtmFailureFault::invoke(), gem5::ArmISA::mcrMrc15TrapToHyp(), pcState(), gem5::TlbiOp64::performTlbi(), gem5::TlbiOp::performTlbi(), gem5::serialize(), gem5::ArmISA::snsBankedIndex64(), and gem5::unserialize().

◆ getMMUPtr()

virtual BaseMMU* gem5::ThreadContext::getMMUPtr ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::X86ISA::copyMiscRegs(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::BaseKvmCPU::doMMIOAccess(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::SparcISA::TLB::GetTsbPtr(), gem5::SparcISA::FastInstructionAccessMMUMiss::invoke(), gem5::SparcISA::FastDataAccessMMUMiss::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::GPUComputeDriver::ioctl(), gem5::Trace::TarmacParserRecord::readMemNoEffect(), gem5::minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation(), gem5::X86ISA::ISA::setMiscReg(), gem5::RiscvISA::ISA::setMiscReg(), gem5::minor::LSQ::SingleDataRequest::startAddrTranslation(), gem5::Trace::TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(), gem5::Trace::TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(), gem5::TranslatingPortProxy::tryMemsetBlob(), gem5::TranslatingPortProxy::tryReadBlob(), gem5::tryTranslate(), and gem5::TranslatingPortProxy::tryWriteBlob().

◆ getProcessPtr()

virtual Process* gem5::ThreadContext::getProcessPtr ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::_llseekFunc(), gem5::ArmISA::RemoteGDB::acc(), gem5::acceptFunc(), gem5::accessImpl(), gem5::atSyscallPath(), gem5::bindFunc(), gem5::brkFunc(), gem5::chdirFunc(), gem5::chownImpl(), gem5::cloneFunc(), gem5::closeFunc(), gem5::BaseRemoteGDB::cmdDumpPageTable(), gem5::connectFunc(), gem5::dup2Func(), gem5::dupFunc(), gem5::X86ISA::EmuLinux::event(), gem5::eventfdFunc(), gem5::execveFunc(), gem5::exitImpl(), gem5::fallocateFunc(), gem5::fchmodatFunc(), gem5::fchmodFunc(), gem5::fchownFunc(), gem5::fcntl64Func(), gem5::fcntlFunc(), gem5::SETranslatingPortProxy::fixupRange(), gem5::fstat64Func(), gem5::fstatat64Func(), gem5::fstatfsFunc(), gem5::fstatFunc(), gem5::ftruncate64Func(), gem5::ftruncateFunc(), gem5::futexFunc(), gem5::futimesatFunc(), gem5::getcwdFunc(), gem5::getegidFunc(), gem5::geteuidFunc(), gem5::getgidFunc(), gem5::getpagesizeFunc(), gem5::getpeernameFunc(), gem5::getpgrpFunc(), gem5::getpidFunc(), gem5::getppidFunc(), gem5::getsocknameFunc(), gem5::getsockoptFunc(), gem5::gettidFunc(), gem5::getuidFunc(), gem5::GenericPageTableFault::invoke(), gem5::SparcISA::FastInstructionAccessMMUMiss::invoke(), gem5::SparcISA::FastDataAccessMMUMiss::invoke(), gem5::SparcISA::SpillNNormal::invoke(), gem5::SparcISA::FillNNormal::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::GPUComputeDriver::ioctl(), gem5::ioctlFunc(), gem5::SparcISA::SEWorkload::is64(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::linkFunc(), gem5::listenFunc(), gem5::lseekFunc(), gem5::lstat64Func(), gem5::lstatFunc(), gem5::mkdirImpl(), gem5::mknodImpl(), gem5::GPUComputeDriver::mmap(), gem5::Shader::mmap(), gem5::mmap2Func(), gem5::mmapFunc(), gem5::mremapFunc(), gem5::munmapFunc(), gem5::newfstatatFunc(), gem5::GPURenderDriver::open(), gem5::GPUComputeDriver::open(), gem5::openatFunc(), gem5::X86ISA::EmuLinux::pageFault(), gem5::pipe2Func(), gem5::pollFunc(), gem5::pread64Func(), gem5::pwrite64Func(), gem5::readFunc(), gem5::readlinkatFunc(), gem5::readvFunc(), gem5::recvfromFunc(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::recvmsgFunc(), gem5::renameImpl(), gem5::rmdirImpl(), gem5::selectFunc(), gem5::sendmsgFunc(), gem5::ComputeUnit::sendRequest(), gem5::sendtoFunc(), gem5::setpgidFunc(), gem5::setsockoptFunc(), gem5::X86ISA::setThreadArea32Func(), gem5::setTidAddressFunc(), gem5::shutdownFunc(), gem5::socketFunc(), gem5::socketpairFunc(), gem5::statfsFunc(), gem5::statFunc(), gem5::symlinkFunc(), gem5::MipsISA::EmuLinux::syscall(), gem5::PowerISA::EmuLinux::syscall(), gem5::ArmISA::EmuLinux::syscall(), gem5::RiscvISA::EmuLinux::syscall(), gem5::ArmISA::EmuFreebsd::syscall(), gem5::X86ISA::EmuLinux::syscall(), gem5::SEWorkload::syscall(), gem5::SparcISA::EmuLinux::syscall32(), gem5::SparcISA::EmuLinux::syscall64(), gem5::sysinfoFunc(), gem5::takeOverFrom(), gem5::tgkillFunc(), gem5::X86ISA::TLB::translate(), gem5::RiscvISA::TLB::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::SparcISA::TLB::translateData(), gem5::X86ISA::TLB::translateFunctional(), gem5::SparcISA::TLB::translateFunctional(), gem5::SparcISA::TLB::translateInst(), gem5::ArmISA::MMU::translateSe(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::truncate64Func(), gem5::truncateFunc(), gem5::SparcISA::unameFunc(), gem5::X86ISA::unameFunc(), gem5::MipsISA::unameFunc(), gem5::PowerISA::unameFunc(), gem5::ArmISA::unameFunc32(), gem5::RiscvISA::unameFunc32(), gem5::RiscvISA::unameFunc64(), gem5::ArmISA::unameFunc64(), gem5::unlinkImpl(), gem5::TLBCoalescer::updatePhysAddresses(), gem5::wait4Func(), gem5::writeFunc(), and gem5::writevFunc().

◆ getReg() [1/2]

RegVal gem5::ThreadContext::getReg ( const RegId &  reg) const
virtual

Reimplemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::SimpleThread.

Definition at line 171 of file thread_context.cc.

References flattenRegId(), getRegFlat(), and gem5::X86ISA::reg.

Referenced by gem5::PowerISA::BranchOp::branchTarget(), gem5::PowerISA::BranchDispCondOp::branchTarget(), gem5::PowerISA::BranchRegCondOp::branchTarget(), gem5::ArmSemihosting::call32(), gem5::ArmSemihosting::call64(), compare(), gem5::PowerISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=sizeof(uint32_t)) > >::get(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::get(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::getRegs(), gem5::X86ISA::getRFlags(), gem5::ArmISA::DumpStats::getTaskDetails(), gem5::ArmISA::DumpStats64::getTaskDetails(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::prepare(), readCCReg(), readFloatReg(), readIntReg(), gem5::ArmISA::ISA::readMiscReg(), readVecElem(), readVecReg(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), gem5::ArmISA::HTMCheckpoint::save(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::guest_abi::Result< PowerISA::SEWorkload::SyscallABI, SyscallReturn >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::ArmISA::syncVecElemsToRegs(), gem5::ArmISA::syncVecRegsToElems(), gem5::PowerISA::EmuLinux::syscall(), gem5::ArmISA::EmuLinux::syscall(), gem5::ArmISA::EmuFreebsd::syscall(), gem5::X86ISA::EmuLinux::syscall(), gem5::Trace::X86NativeTrace::ThreadState::update(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateCC(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateFloat(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateInt(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::updateKvmStateFPUCommon(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updatePred(), and gem5::Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateVec().

◆ getReg() [2/2]

void gem5::ThreadContext::getReg ( const RegId &  reg,
void *  val 
) const
virtual

Reimplemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::SimpleThread.

Definition at line 189 of file thread_context.cc.

References flattenRegId(), getRegFlat(), gem5::X86ISA::reg, and gem5::X86ISA::val.

◆ getRegFlat() [1/2]

RegVal gem5::ThreadContext::getRegFlat ( const RegId &  reg) const
virtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Reimplemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Definition at line 201 of file thread_context.cc.

References gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by gem5::X86ISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), getReg(), readCCRegFlat(), readFloatRegFlat(), readIntRegFlat(), readVecElemFlat(), readVecRegFlat(), gem5::serialize(), gem5::ArmKvmCPU::updateKvmStateCore(), and gem5::ArmKvmCPU::updateKvmStateVFP().

◆ getRegFlat() [2/2]

virtual void gem5::ThreadContext::getRegFlat ( const RegId &  reg,
void *  val 
) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

◆ getSystemPtr()

virtual System* gem5::ThreadContext::getSystemPtr ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::_llseekFunc(), gem5::pseudo_inst::addsymbol(), gem5::pseudo_inst::arm(), gem5::ArmISA::TLBIOp::broadcast(), gem5::cloneFunc(), gem5::Linux::cpuOnline(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::BaseStackTrace::dump(), gem5::linux::dumpDmesg(), gem5::exitFutexWake(), gem5::exitImpl(), gem5::futexFunc(), gem5::ArmSemihosting::gatherHeapInfo(), gem5::ArmSystem::getArmSystem(), gem5::getcpuFunc(), gem5::getrlimitFunc(), gem5::System::Threads::insert(), gem5::PowerISA::UnimplementedOpcodeFault::invoke(), gem5::SESyscallFault::invoke(), gem5::PowerISA::AlignmentFault::invoke(), gem5::PowerISA::TrapFault::invoke(), gem5::GenericPageTableFault::invoke(), gem5::GenericAlignmentFault::invoke(), gem5::RiscvISA::Reset::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::SupervisorCall::invoke(), gem5::RiscvISA::SyscallFault::invokeSE(), gem5::pseudo_inst::loadsymbol(), gem5::pollFunc(), gem5::ArmSemihosting::portProxy(), gem5::ArmISA::DumpStats::process(), quiesce(), quiesceTick(), gem5::pseudo_inst::readfile(), gem5::SparcISA::ISA::readFSReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::schedGetaffinityFunc(), gem5::selectFunc(), gem5::SparcISA::ISA::setFSReg(), gem5::setpgidFunc(), gem5::takeOverFrom(), gem5::tgkillFunc(), gem5::DistIface::toggleSync(), gem5::SparcISA::TLB::translateFunctional(), gem5::pseudo_inst::triggerWorkloadEvent(), gem5::wait4Func(), gem5::pseudo_inst::wakeCPU(), gem5::pseudo_inst::workbegin(), and gem5::pseudo_inst::workend().

◆ getUseForClone()

bool gem5::ThreadContext::getUseForClone ( )
inline

Definition at line 101 of file thread_context.hh.

References useForClone.

◆ getWritableReg()

void * gem5::ThreadContext::getWritableReg ( const RegId &  reg)
virtual

Reimplemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::SimpleThread.

Definition at line 177 of file thread_context.cc.

References flattenRegId(), getWritableRegFlat(), and gem5::X86ISA::reg.

Referenced by getWritableVecReg(), and gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs().

◆ getWritableRegFlat()

virtual void* gem5::ThreadContext::getWritableRegFlat ( const RegId &  reg)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by getWritableReg(), and getWritableVecRegFlat().

◆ getWritableVecReg()

TheISA::VecRegContainer& gem5::ThreadContext::getWritableVecReg ( const RegId &  reg)
inline

Definition at line 223 of file thread_context.hh.

References getWritableReg(), and gem5::X86ISA::reg.

Referenced by gem5::ArmV8KvmCPU::updateThreadContext().

◆ getWritableVecRegFlat()

TheISA::VecRegContainer& gem5::ThreadContext::getWritableVecRegFlat ( RegIndex  idx)
inline

Definition at line 355 of file thread_context.hh.

References getWritableRegFlat(), and gem5::VecRegClass.

◆ halt()

virtual void gem5::ThreadContext::halt ( )
pure virtual

Set the status to Halted.

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::exitImpl().

◆ htmAbortTransaction()

virtual void gem5::ThreadContext::htmAbortTransaction ( uint64_t  htm_uid,
HtmFailureFaultCause  cause 
)
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::GenericHtmFailureFault::invoke().

◆ pcState() [1/3]

virtual const PCStateBase& gem5::ThreadContext::pcState ( ) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

Referenced by gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::GenericISA::M5DebugFault::advancePC(), gem5::RiscvISA::RiscvStaticInst::advancePC(), gem5::ArmISA::MightBeMicro::advancePC(), gem5::PowerISA::PowerStaticInst::advancePC(), gem5::ArmISA::MicroOp::advancePC(), gem5::ArmISA::MightBeMicro64::advancePC(), gem5::SparcISA::SparcMicroInst::advancePC(), gem5::SparcISA::SparcStaticInst::advancePC(), gem5::ArmISA::MicroOpX::advancePC(), gem5::X86ISA::X86MicroopBase::advancePC(), gem5::RiscvISA::RiscvMicroInst::advancePC(), gem5::ArmISA::ArmStaticInst::advancePC(), gem5::X86ISA::X86StaticInst::advancePC(), gem5::StaticInst::advancePC(), gem5::ArmISA::PredMicroop::advancePC(), gem5::ArmISA::FpOp::advancePC(), gem5::ArmISA::SoftwareStep::advanceSS(), gem5::MipsProcess::argsInit(), gem5::PowerProcess::argsInit(), gem5::RiscvProcess::argsInit(), gem5::ArmProcess::argsInit(), gem5::X86ISA::X86Process::argsInit(), gem5::PowerISA::BranchOp::branchTarget(), gem5::PowerISA::BranchDispCondOp::branchTarget(), gem5::Trace::SparcNativeTrace::check(), gem5::Trace::ArmNativeTrace::check(), gem5::BaseRemoteGDB::cmdAsyncCont(), gem5::BaseRemoteGDB::cmdAsyncStep(), gem5::BaseRemoteGDB::cmdCont(), gem5::BaseRemoteGDB::cmdStep(), gem5::minor::Execute::commit(), compare(), gem5::RiscvISA::ISA::copyRegsFrom(), gem5::X86ISA::ISA::copyRegsFrom(), gem5::PowerISA::ISA::copyRegsFrom(), gem5::MipsISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::BaseKvmCPU::doMMIOAccess(), gem5::SparcISA::doNormalFault(), gem5::SparcISA::doREDFault(), gem5::X86ISA::EmuLinux::event(), gem5::minor::Execute::executeMemRefInst(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::getRegs(), gem5::SparcISA::SEWorkload::handleTrap(), gem5::PowerProcess::initState(), gem5::X86ISA::FsWorkload::initState(), gem5::o3::CPU::insertThread(), gem5::FaultBase::invoke(), gem5::PowerISA::UnimplementedOpcodeFault::invoke(), gem5::SparcISA::SparcFaultBase::invoke(), gem5::X86ISA::X86FaultBase::invoke(), gem5::SESyscallFault::invoke(), gem5::ReExec::invoke(), gem5::SparcISA::PowerOnReset::invoke(), gem5::MipsISA::MipsFaultBase::invoke(), gem5::PowerISA::TrapFault::invoke(), gem5::SyscallRetryFault::invoke(), gem5::RiscvISA::RiscvFault::invoke(), gem5::MipsISA::ResetFault::invoke(), gem5::RiscvISA::Reset::invoke(), gem5::SparcISA::SpillNNormal::invoke(), gem5::MipsISA::TlbFault< TlbInvalidFault >::invoke(), gem5::SparcISA::FillNNormal::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::ArmISA::Reset::invoke(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::StartupInterrupt::invoke(), gem5::ArmISA::SupervisorCall::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::RiscvISA::RiscvFault::invokeSE(), gem5::RiscvISA::UnknownInstFault::invokeSE(), gem5::RiscvISA::IllegalInstFault::invokeSE(), gem5::RiscvISA::UnimplementedFault::invokeSE(), gem5::RiscvISA::IllegalFrmFault::invokeSE(), gem5::ioctlFunc(), gem5::mmapFunc(), pcState(), gem5::SkipFuncBase::process(), gem5::pseudo_inst::pseudoInstWork(), gem5::Trace::TarmacParserRecord::readMemNoEffect(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), gem5::ArmISA::HTMCheckpoint::save(), gem5::serialize(), gem5::MipsISA::MipsFaultBase::setExceptionState(), gem5::RiscvISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs(), gem5::X86ISA::EmuLinux::syscall(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::minor::Execute::tryPCEvents(), gem5::minor::Execute::tryToBranch(), gem5::unserialize(), gem5::Trace::X86NativeTrace::ThreadState::update(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateKvmStateCore(), gem5::X86KvmCPU::updateKvmStateRegs(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::X86KvmCPU::updateThreadContextRegs(), and gem5::minor::Fetch1::wakeupFetch().

◆ pcState() [2/3]

void gem5::ThreadContext::pcState ( Addr  addr)
inline

Definition at line 274 of file thread_context.hh.

References gem5::X86ISA::addr, getIsaPtr(), and pcState().

◆ pcState() [3/3]

virtual void gem5::ThreadContext::pcState ( const PCStateBase &  val)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

◆ pcStateNoRecord()

virtual void gem5::ThreadContext::pcStateNoRecord ( const PCStateBase &  val)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

Referenced by gem5::ArmISA::SkipFunc::returnFromFuncIn(), and gem5::ArmISA::ISA::setMiscReg().

◆ quiesce()

void gem5::ThreadContext::quiesce ( )

Quiesce thread context.

Definition at line 158 of file thread_context.cc.

References contextId(), getSystemPtr(), gem5::System::Threads::quiesce(), and gem5::System::threads.

Referenced by gem5::pseudo_inst::quiesce(), and gem5::DistIface::toggleSync().

◆ quiesceTick()

void gem5::ThreadContext::quiesceTick ( Tick  resume)

Quiesce, suspend, and schedule activate at resume.

Definition at line 165 of file thread_context.cc.

References contextId(), getSystemPtr(), gem5::System::Threads::quiesceTick(), and gem5::System::threads.

Referenced by gem5::free_bsd::onUDelay(), gem5::linux::onUDelay(), gem5::pseudo_inst::quiesceCycles(), gem5::pseudo_inst::quiesceNs(), gem5::pseudo_inst::quiesceSkip(), and gem5::DistIface::toggleSync().

◆ readCCReg()

RegVal gem5::ThreadContext::readCCReg ( RegIndex  reg_idx) const
inline

Definition at line 235 of file thread_context.hh.

References gem5::CCRegClass, and getReg().

Referenced by compare().

◆ readCCRegFlat()

RegVal gem5::ThreadContext::readCCRegFlat ( RegIndex  idx) const
inline

Definition at line 378 of file thread_context.hh.

References gem5::CCRegClass, and getRegFlat().

Referenced by gem5::serialize().

◆ readFloatReg()

RegVal gem5::ThreadContext::readFloatReg ( RegIndex  reg_idx) const
inline

Definition at line 210 of file thread_context.hh.

References gem5::FloatRegClass, and getReg().

Referenced by compare(), gem5::RiscvISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::Iris::ThreadContext::getReg(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), and gem5::MipsISA::readRegOtherThread().

◆ readFloatRegFlat()

RegVal gem5::ThreadContext::readFloatRegFlat ( RegIndex  idx) const
inline

Definition at line 337 of file thread_context.hh.

References gem5::FloatRegClass, and getRegFlat().

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), and gem5::serialize().

◆ readIntReg()

RegVal gem5::ThreadContext::readIntReg ( RegIndex  reg_idx) const
inline

Definition at line 204 of file thread_context.hh.

References getReg(), and gem5::IntRegClass.

Referenced by gem5::Trace::SparcNativeTrace::check(), compare(), gem5::RiscvISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::SparcISA::doNormalFault(), gem5::SparcISA::doREDFault(), gem5::TimingExprReadIntReg::eval(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::guest_abi::Argument< SparcPseudoInstABI, uint64_t >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< GenericSyscallABI64, ABI > &&std::is_integral_v< Arg > > >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&!ABI::template IsWideV< Arg > > >::get(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), gem5::GenericSyscallABI32::mergeRegs(), gem5::MipsISA::readRegOtherThread(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > >::store(), gem5::MipsISA::EmuLinux::syscall(), gem5::RiscvISA::EmuLinux::syscall(), gem5::SparcISA::EmuLinux::syscall32(), and gem5::SparcISA::EmuLinux::syscall64().

◆ readIntRegFlat()

RegVal gem5::ThreadContext::readIntRegFlat ( RegIndex  idx) const
inline

Definition at line 326 of file thread_context.hh.

References getRegFlat(), and gem5::IntRegClass.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), and gem5::serialize().

◆ readLastActivate()

virtual Tick gem5::ThreadContext::readLastActivate ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::pseudo_inst::quiesceTime().

◆ readLastSuspend()

virtual Tick gem5::ThreadContext::readLastSuspend ( )
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::pseudo_inst::quiesceTime().

◆ readMiscReg()

virtual RegVal gem5::ThreadContext::readMiscReg ( RegIndex  misc_reg)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

Referenced by gem5::ArmISA::AArch32isUndefinedGenericTimer(), gem5::ArmISA::addPAC(), gem5::ArmISA::addPACDA(), gem5::ArmISA::addPACDB(), gem5::ArmISA::addPACGA(), gem5::ArmISA::addPACIA(), gem5::ArmISA::addPACIB(), gem5::ArmISA::VectorCatch::addressMatching(), gem5::ArmProcess64::armHwcapImpl(), gem5::ArmISA::authDA(), gem5::ArmISA::authDB(), gem5::ArmISA::authIA(), gem5::ArmISA::authIB(), gem5::MipsISA::MipsFaultBase::base(), gem5::ArmISA::calculateBottomPACBit(), gem5::ArmISA::calculateTBI(), gem5::ArmISA::canReadAArch64SysReg(), gem5::ArmISA::canWriteAArch64SysReg(), gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::MiscRegOp64::checkEL1Trap(), gem5::MiscRegOp64::checkEL2Trap(), gem5::MiscRegOp64::checkEL3Trap(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::Interrupts::checkInterrupts(), gem5::RiscvISA::Interrupts::checkNonMaskableInterrupt(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::ArmISA::computeAddrTop(), gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2(), gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2(), gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2(), gem5::ArmISA::condGenericTimerPhysHypTrap(), gem5::ArmISA::condGenericTimerSystemAccessTrapEL1(), gem5::X86ISA::copyMiscRegs(), gem5::ArmISA::debugTargetFrom(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::RiscvISA::TLB::doTranslate(), gem5::ArmKvmCPU::dumpKvmStateCoProc(), gem5::ArmISA::PrefetchAbort::ec(), gem5::ArmISA::DataAbort::ec(), gem5::ArmISA::ELIsInHost(), gem5::ArmISA::ELStateUsingAArch32K(), gem5::ArmISA::VectorCatch::exceptionTrapping(), gem5::MiscRegImplDefined64::execute(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), gem5::ArmISA::BrkPoint::getAddrfromReg(), gem5::ArmISA::WatchPoint::getAddrfromReg(), gem5::ArmISA::BrkPoint::getContextfromReg(), gem5::ArmISA::BrkPoint::getControlReg(), gem5::ArmISA::Interrupts::getInterrupt(), gem5::RiscvISA::TLB::getMemPriv(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), gem5::ArmISA::getRestoredITBits(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::ArmISA::ArmFault::getVector64(), gem5::ArmISA::VectorCatch::getVectorBase(), gem5::ArmISA::MMU::CachedState::getVMID(), gem5::ArmISA::BrkPoint::getVMIDfromReg(), gem5::RiscvISA::Interrupts::globalMask(), gem5::ArmISA::ISA::handleLockedSnoopHit(), gem5::ArmISA::illegalExceptionReturn(), gem5::ArmISA::inAArch64(), gem5::ArmISA::SelfDebug::init(), gem5::ArmProcess32::initState(), gem5::ArmProcess64::initState(), gem5::RiscvISA::RiscvFault::invoke(), gem5::RiscvISA::Reset::invoke(), gem5::MipsISA::CoprocessorUnusableFault::invoke(), gem5::ArmISA::Reset::invoke(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::StartupInterrupt::invoke(), gem5::ArmISA::AbortFault< DataAbort >::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::X86KvmCPU::ioctlRun(), gem5::ArmISA::SelfDebug::isDebugEnabled(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::isGenericTimerCommonEL0HypTrap(), gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2(), gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2(), gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2(), gem5::ArmISA::isGenericTimerSystemAccessTrapEL1(), gem5::ArmISA::isGenericTimerSystemAccessTrapEL3(), gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2(), gem5::ArmISA::isSecure(), gem5::ArmISA::isUnpriviledgeAccess(), gem5::ArmISA::ArmStaticInst::isWFxTrapping(), gem5::ArmISA::longDescFormatInUse(), gem5::ArmISA::mcrMrc14TrapToHyp(), gem5::ArmISA::mcrMrc15TrapToHyp(), gem5::ArmISA::mcrrMrrc15TrapToHyp(), gem5::ArmISA::TableWalker::memAttrs(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::ArmISA::ArmFaultVals< FastInterrupt >::offset(), gem5::MipsISA::TlbRefillFault::offset(), gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::TLBIALLEL::operator()(), gem5::ArmISA::TLBIVMALL::operator()(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::TLBIMVAA::operator()(), gem5::ArmISA::TLBIMVA::operator()(), gem5::X86ISA::EmuLinux::pageFault(), gem5::TlbiOp64::performTlbi(), gem5::TlbiOp::performTlbi(), gem5::ArmISA::TableWalker::processWalk(), gem5::ArmISA::TableWalker::processWalkAArch64(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::ArmISA::purifyTaggedAddr(), gem5::ArmISA::readMPIDR(), gem5::MipsISA::readRegOtherThread(), gem5::ArmISA::HTMCheckpoint::save(), gem5::ArmISA::sendEvent(), gem5::Iris::Interrupts::serialize(), gem5::MipsISA::MipsFaultBase::setExceptionState(), gem5::ArmISA::ISA::setMiscReg(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::MipsISA::TlbFault< TlbInvalidFault >::setTlbExceptionState(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::snsBankedIndex64(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), gem5::ArmISA::SPAlignmentCheckEnabled(), gem5::ArmV8KvmCPU::startup(), gem5::ArmISA::stripPAC(), gem5::ArmISA::Interrupts::takeInt(), gem5::ArmISA::WatchPoint::test(), gem5::ArmISA::BrkPoint::testAddrMatch(), gem5::ArmISA::BrkPoint::testAddrMissMatch(), gem5::ArmISA::BrkPoint::testContextMatch(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::RiscvISA::TLB::translate(), gem5::ArmISA::MMU::translateMmuOff(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmISA::ArmFault::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateKvmStateCore(), gem5::updateKvmStateFPUCommon(), gem5::X86KvmCPU::updateKvmStateMSRs(), gem5::X86KvmCPU::updateKvmStateRegs(), gem5::X86KvmCPU::updateKvmStateSRegs(), gem5::ArmKvmCPU::updateKvmStateVFP(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), gem5::ArmISA::upperAndLowerRange(), and gem5::ArmISA::TableWalker::walk().

◆ readMiscRegNoEffect()

virtual RegVal gem5::ThreadContext::readMiscRegNoEffect ( RegIndex  misc_reg) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, gem5::o3::ThreadContext, and gem5::fastmodel::CortexR52TC.

Referenced by gem5::ArmISA::AbortFault< DataAbort >::abortDisable(), gem5::ArmISA::Interrupt::abortDisable(), gem5::ArmISA::FastInterrupt::abortDisable(), gem5::X86ISA::archPrctlFunc(), gem5::MipsISA::Interrupts::checkInterrupts(), gem5::SparcISA::Interrupts::checkInterrupts(), gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), compare(), gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2(), gem5::SparcISA::copyMiscRegs(), gem5::X86ISA::copyMiscRegs(), gem5::MipsISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::ArmISA::debugTargetFrom(), gem5::SparcISA::doNormalFault(), gem5::SparcISA::doREDFault(), gem5::ArmKvmCPU::dumpKvmStateCoProc(), gem5::ArmISA::EL2Enabled(), gem5::SparcISA::enterREDState(), gem5::X86ISA::TLB::finalizePhysical(), gem5::ArmISA::FastInterrupt::fiqDisable(), gem5::MipsISA::getCauseIP(), gem5::SparcISA::getHyperVector(), gem5::MipsISA::Interrupts::getInterrupt(), gem5::SparcISA::Interrupts::getInterrupt(), gem5::SparcISA::getPrivVector(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::getRegs(), gem5::X86ISA::getRFlags(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::X86KvmCPU::handleIOMiscReg32(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::ArmISA::SelfDebug::init(), gem5::X86ISA::FsWorkload::initState(), gem5::Trace::TarmacBaseRecord::InstEntry::InstEntry(), gem5::MipsISA::Interrupts::interruptsPending(), gem5::Iris::ISA::inUserMode(), gem5::SparcISA::SparcFaultBase::invoke(), gem5::X86ISA::X86FaultBase::invoke(), gem5::SparcISA::PowerOnReset::invoke(), gem5::MipsISA::ResetFault::invoke(), gem5::SparcISA::FastInstructionAccessMMUMiss::invoke(), gem5::SparcISA::FastDataAccessMMUMiss::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::ArmISA::VirtualDataAbort::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::isBigEndian64(), gem5::ArmISA::isSecureBelowEL3(), gem5::ArmISA::IsSecureEL2Enabled(), gem5::MipsISA::InterruptFault::offset(), gem5::MipsISA::Interrupts::onCpuTimerInterrupt(), gem5::X86ISA::GpuTLB::pagingProtectionChecks(), gem5::SparcISA::ISA::processHSTickCompare(), gem5::SparcISA::ISA::processSTickCompare(), gem5::ArmISA::UndefinedInstruction::routeToHyp(), gem5::ArmISA::SupervisorCall::routeToHyp(), gem5::ArmISA::SupervisorTrap::routeToHyp(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::DataAbort::routeToHyp(), gem5::ArmISA::Interrupt::routeToHyp(), gem5::ArmISA::FastInterrupt::routeToHyp(), gem5::ArmISA::PCAlignmentFault::routeToHyp(), gem5::ArmISA::SPAlignmentFault::routeToHyp(), gem5::ArmISA::SystemError::routeToHyp(), gem5::ArmISA::SoftwareBreakpoint::routeToHyp(), gem5::ArmISA::HardwareBreakpoint::routeToHyp(), gem5::ArmISA::Watchpoint::routeToHyp(), gem5::ArmISA::SoftwareStepFault::routeToHyp(), gem5::ArmISA::IllegalInstSetStateFault::routeToHyp(), gem5::ArmISA::PrefetchAbort::routeToMonitor(), gem5::ArmISA::DataAbort::routeToMonitor(), gem5::ArmISA::Interrupt::routeToMonitor(), gem5::ArmISA::FastInterrupt::routeToMonitor(), gem5::ArmISA::SystemError::routeToMonitor(), gem5::ArmISA::s1TranslationRegime(), gem5::Iris::ISA::serialize(), gem5::Iris::Interrupts::serialize(), gem5::MipsISA::setCauseIP(), gem5::setKvmDTableReg(), gem5::setKvmSegmentReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs(), gem5::PMP::shouldCheckPMP(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > >::store(), gem5::X86ISA::GpuTLB::tlbLookup(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::SparcISA::TLB::translateFunctional(), gem5::X86ISA::TLB::translateInt(), gem5::X86ISA::GpuTLB::translateInt(), gem5::Trace::ArmNativeTrace::ThreadState::update(), gem5::ArmISA::ArmFault::update(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateInt(), gem5::ArmKvmCPU::updateKvmStateCoProc(), gem5::updateKvmStateFPUCommon(), gem5::X86KvmCPU::updateKvmStateFPULegacy(), gem5::X86KvmCPU::updateKvmStateFPUXSave(), gem5::Trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmKvmCPU::updateTCStateCore().

◆ readStCondFailures()

virtual unsigned gem5::ThreadContext::readStCondFailures ( ) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

Referenced by gem5::RiscvISA::ISA::handleLockedWrite().

◆ readVecElem()

RegVal gem5::ThreadContext::readVecElem ( const RegId &  reg) const
inline

Definition at line 229 of file thread_context.hh.

References getReg(), and gem5::X86ISA::reg.

◆ readVecElemFlat()

RegVal gem5::ThreadContext::readVecElemFlat ( RegIndex  idx) const
inline

Definition at line 367 of file thread_context.hh.

References getRegFlat(), and gem5::VecElemClass.

◆ readVecReg()

TheISA::VecRegContainer gem5::ThreadContext::readVecReg ( const RegId &  reg) const
inline

Definition at line 216 of file thread_context.hh.

References getReg(), gem5::X86ISA::reg, and gem5::X86ISA::val.

◆ readVecRegFlat()

TheISA::VecRegContainer gem5::ThreadContext::readVecRegFlat ( RegIndex  idx) const
inline

Definition at line 348 of file thread_context.hh.

References getRegFlat(), gem5::X86ISA::val, and gem5::VecRegClass.

Referenced by gem5::serialize().

◆ regStats()

virtual void gem5::ThreadContext::regStats ( const std::string &  name)
inlinevirtual

Reimplemented in gem5::Iris::ThreadContext, and gem5::CheckerThreadContext< TC >.

Definition at line 178 of file thread_context.hh.

Referenced by gem5::CheckerThreadContext< TC >::regStats().

◆ scheduleInstCountEvent()

virtual void gem5::ThreadContext::scheduleInstCountEvent ( Event *  event,
Tick  count 
)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::BaseRemoteGDB::scheduleInstCommitEvent().

◆ sendFunctional()

void gem5::ThreadContext::sendFunctional ( PacketPtr  pkt)
virtual

Reimplemented in gem5::Iris::ThreadContext, and gem5::fastmodel::CortexR52TC.

Definition at line 149 of file thread_context.cc.

References getCpuPtr().

Referenced by gem5::PortProxy::PortProxy().

◆ setCCReg()

void gem5::ThreadContext::setCCReg ( RegIndex  reg_idx,
RegVal  val 
)
inline

Definition at line 265 of file thread_context.hh.

References gem5::CCRegClass, setReg(), and gem5::X86ISA::val.

◆ setCCRegFlat()

void gem5::ThreadContext::setCCRegFlat ( RegIndex  idx,
RegVal  val 
)
inline

Definition at line 383 of file thread_context.hh.

References gem5::CCRegClass, setRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::unserialize().

◆ setContextId()

virtual void gem5::ThreadContext::setContextId ( ContextID  id)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::System::Threads::insert(), and gem5::takeOverFrom().

◆ setFloatReg()

void gem5::ThreadContext::setFloatReg ( RegIndex  reg_idx,
RegVal  val 
)
inline

Definition at line 247 of file thread_context.hh.

References gem5::FloatRegClass, setReg(), and gem5::X86ISA::val.

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::Iris::ThreadContext::setReg(), gem5::MipsISA::setRegOtherThread(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), and gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs().

◆ setFloatRegFlat()

void gem5::ThreadContext::setFloatRegFlat ( RegIndex  idx,
RegVal  val 
)
inline

Definition at line 342 of file thread_context.hh.

References gem5::FloatRegClass, setRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), and gem5::unserialize().

◆ setHtmCheckpointPtr()

virtual void gem5::ThreadContext::setHtmCheckpointPtr ( BaseHTMCheckpointPtr  cpt)
pure virtual

Implemented in gem5::SimpleThread, gem5::CheckerThreadContext< TC >, gem5::o3::ThreadContext, and gem5::Iris::ThreadContext.

Referenced by gem5::ArmISA::ISA::startup().

◆ setIntReg()

void gem5::ThreadContext::setIntReg ( RegIndex  reg_idx,
RegVal  val 
)
inline

Definition at line 241 of file thread_context.hh.

References gem5::IntRegClass, setReg(), and gem5::X86ISA::val.

Referenced by gem5::RiscvLinux64::archClone(), gem5::SparcLinux::archClone(), gem5::RiscvLinux32::archClone(), gem5::MipsProcess::argsInit(), gem5::RiscvProcess::argsInit(), gem5::RiscvISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::SparcProcess::initState(), gem5::MipsISA::setRegOtherThread(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::guest_abi::Result< SparcPseudoInstABI, T >::store(), gem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI, SyscallReturn >::store(), gem5::guest_abi::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store(), and gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > >::store().

◆ setIntRegFlat()

void gem5::ThreadContext::setIntRegFlat ( RegIndex  idx,
RegVal  val 
)
inline

Definition at line 331 of file thread_context.hh.

References gem5::IntRegClass, setRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), gem5::fastmodel::CortexA76TC::setIntRegFlat(), and gem5::unserialize().

◆ setMiscReg()

virtual void gem5::ThreadContext::setMiscReg ( RegIndex  misc_reg,
RegVal  val 
)
pure virtual

Implemented in gem5::CheckerThreadContext< TC >, gem5::SimpleThread, gem5::o3::ThreadContext, and gem5::Iris::ThreadContext.

Referenced by gem5::ArmLinux::archClone(), gem5::SparcLinux::archClone(), gem5::RiscvISA::Interrupts::clearNMI(), gem5::SparcISA::copyMiscRegs(), gem5::X86ISA::copyMiscRegs(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::SparcISA::doNormalFault(), gem5::SparcISA::doREDFault(), gem5::SparcISA::enterREDState(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::ArmISA::ISA::globalClearExclusive(), gem5::X86KvmCPU::handleIOMiscReg32(), gem5::ArmISA::ISA::handleLockedRead(), gem5::ArmISA::ISA::handleLockedSnoopHit(), gem5::SparcProcess::initState(), gem5::Sparc32Process::initState(), gem5::X86ISA::FsWorkload::initState(), gem5::ArmProcess32::initState(), gem5::ArmProcess64::initState(), gem5::Sparc64Process::initState(), gem5::X86ISA::X86_64Process::initState(), gem5::X86ISA::I386Process::initState(), gem5::X86ISA::installSegDesc(), gem5::SparcISA::PowerOnReset::invoke(), gem5::RiscvISA::RiscvFault::invoke(), gem5::MipsISA::ResetFault::invoke(), gem5::RiscvISA::Reset::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::ArmISA::Reset::invoke(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::StartupInterrupt::invoke(), gem5::ArmISA::AbortFault< DataAbort >::invoke(), gem5::ArmISA::PCAlignmentFault::invoke(), gem5::ArmISA::HardwareBreakpoint::invoke(), gem5::ArmISA::Watchpoint::invoke(), gem5::ArmISA::ArmSev::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::ArmFault::invoke64(), gem5::X86KvmCPU::ioctlRun(), gem5::RiscvISA::Interrupts::postNMI(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::Iris::Interrupts::serialize(), gem5::setContextSegment(), gem5::ArmISA::ISA::setMiscReg(), gem5::MipsISA::setRegOtherThread(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs(), gem5::X86ISA::setRFlags(), gem5::ArmISA::ArmFault::setSyndrome(), gem5::ArmISA::setTLSFunc32(), gem5::ArmISA::setTLSFunc64(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmKvmCPU::updateTCStateVFP(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::X86KvmCPU::updateThreadContext(), and gem5::X86KvmCPU::updateThreadContextMSRs().

◆ setMiscRegNoEffect()

virtual void gem5::ThreadContext::setMiscRegNoEffect ( RegIndex  misc_reg,
RegVal  val 
)
pure virtual

Implemented in gem5::CheckerThreadContext< TC >, gem5::SimpleThread, gem5::o3::ThreadContext, gem5::Iris::ThreadContext, and gem5::fastmodel::CortexR52TC.

Referenced by gem5::X86Linux::archClone(), gem5::SparcLinux::archClone(), gem5::X86ISA::archPrctlFunc(), gem5::SparcISA::copyMiscRegs(), gem5::X86ISA::copyMiscRegs(), gem5::MipsISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::SparcISA::doNormalFault(), gem5::SparcISA::doREDFault(), gem5::SparcProcess::initState(), gem5::X86ISA::X86_64Process::initState(), gem5::X86ISA::I386Process::initState(), gem5::SparcISA::PowerOnReset::invoke(), gem5::MipsISA::CoprocessorUnusableFault::invoke(), gem5::MipsISA::AddressFault< TlbInvalidFault >::invoke(), gem5::ArmISA::VirtualDataAbort::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::MipsISA::setCauseIP(), gem5::MipsISA::MipsFaultBase::setExceptionState(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), gem5::MipsISA::setThreadAreaFunc(), gem5::MipsISA::TlbFault< TlbInvalidFault >::setTlbExceptionState(), gem5::ArmKvmCPU::updateTCStateCoProc(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::X86KvmCPU::updateThreadContextFPU(), gem5::updateThreadContextFPUCommon(), and gem5::X86KvmCPU::updateThreadContextXSave().

◆ setProcessPtr()

virtual void gem5::ThreadContext::setProcessPtr ( Process *  p)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::cloneFunc(), and gem5::execveFunc().

◆ setReg() [1/2]

void gem5::ThreadContext::setReg ( const RegId &  reg,
const void *  val 
)
virtual

Reimplemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::SimpleThread.

Definition at line 195 of file thread_context.cc.

References flattenRegId(), gem5::X86ISA::reg, setRegFlat(), and gem5::X86ISA::val.

◆ setReg() [2/2]

void gem5::ThreadContext::setReg ( const RegId &  reg,
RegVal  val 
)
virtual

Reimplemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::SimpleThread.

Definition at line 183 of file thread_context.cc.

References flattenRegId(), gem5::X86ISA::reg, setRegFlat(), and gem5::X86ISA::val.

Referenced by gem5::X86Linux::archClone(), gem5::PowerLinux::archClone(), gem5::ArmLinux32::archClone(), gem5::ArmLinux64::archClone(), gem5::PowerProcess::argsInit(), gem5::ArmProcess::argsInit(), gem5::X86ISA::X86Process::argsInit(), gem5::PowerISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::PowerProcess::initState(), gem5::X86ISA::X86FaultBase::invoke(), gem5::X86ISA::InitInterrupt::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::ArmISA::HTMCheckpoint::restore(), setCCReg(), setFloatReg(), setIntReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs(), gem5::X86ISA::setRFlags(), setVecElem(), setVecReg(), gem5::guest_abi::Result< X86PseudoInstABI, T >::store(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > >::store(), gem5::guest_abi::Result< PowerISA::SEWorkload::SyscallABI, SyscallReturn >::store(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< X86Linux::SyscallABI, ABI > > >::store(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::guest_abi::Result< ArmSemihosting::Abi32, ArmSemihosting::RetErrno >::store(), gem5::guest_abi::Result< ArmSemihosting::Abi64, ArmSemihosting::RetErrno >::store(), gem5::ArmISA::syncVecElemsToRegs(), gem5::ArmISA::syncVecRegsToElems(), gem5::ArmV8KvmCPU::updateThreadContext(), and gem5::updateThreadContextFPUCommon().

◆ setRegFlat() [1/2]

virtual void gem5::ThreadContext::setRegFlat ( const RegId &  reg,
const void *  val 
)
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

◆ setRegFlat() [2/2]

void gem5::ThreadContext::setRegFlat ( const RegId &  reg,
RegVal  val 
)
virtual

Reimplemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Definition at line 209 of file thread_context.cc.

References gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by gem5::X86ISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::copyRegsFrom(), setCCRegFlat(), setFloatRegFlat(), setIntRegFlat(), setReg(), setVecElemFlat(), setVecRegFlat(), gem5::unserialize(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmKvmCPU::updateTCStateVFP(), and gem5::ArmV8KvmCPU::updateThreadContext().

◆ setStatus()

virtual void gem5::ThreadContext::setStatus ( Status  new_status)
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::o3::CPU::exitThreads(), gem5::o3::CPU::insertThread(), and gem5::takeOverFrom().

◆ setStCondFailures()

virtual void gem5::ThreadContext::setStCondFailures ( unsigned  sc_failures)
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, gem5::SimpleThread, and gem5::o3::ThreadContext.

Referenced by gem5::RiscvISA::ISA::handleLockedWrite().

◆ setThreadId()

virtual void gem5::ThreadContext::setThreadId ( int  id)
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::takeOverFrom().

◆ setUseForClone()

void gem5::ThreadContext::setUseForClone ( bool  new_val)
inline

Definition at line 103 of file thread_context.hh.

References useForClone.

Referenced by gem5::cloneFunc().

◆ setVecElem()

void gem5::ThreadContext::setVecElem ( const RegId &  reg,
RegVal  val 
)
inline

Definition at line 259 of file thread_context.hh.

References gem5::X86ISA::reg, setReg(), and gem5::X86ISA::val.

◆ setVecElemFlat()

void gem5::ThreadContext::setVecElemFlat ( RegIndex  idx,
RegVal  val 
)
inline

Definition at line 372 of file thread_context.hh.

References setRegFlat(), gem5::X86ISA::val, and gem5::VecElemClass.

◆ setVecReg()

void gem5::ThreadContext::setVecReg ( const RegId &  reg,
const TheISA::VecRegContainer &  val 
)
inline

Definition at line 253 of file thread_context.hh.

References gem5::X86ISA::reg, setReg(), and gem5::X86ISA::val.

◆ setVecRegFlat()

void gem5::ThreadContext::setVecRegFlat ( RegIndex  idx,
const TheISA::VecRegContainer &  val 
)
inline

Definition at line 361 of file thread_context.hh.

References setRegFlat(), gem5::X86ISA::val, and gem5::VecRegClass.

Referenced by gem5::unserialize().

◆ socketId()

virtual uint32_t gem5::ThreadContext::socketId ( ) const
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::o3::ThreadContext, and gem5::CheckerThreadContext< TC >.

Referenced by gem5::ArmISA::getAff1(), gem5::ArmISA::getAff2(), gem5::FVPBasePwrCtrl::getCorePwrStatus(), gem5::ArmISA::getMPIDR(), gem5::FVPBasePwrCtrl::powerCoreOff(), gem5::FVPBasePwrCtrl::powerCoreOn(), and gem5::FVPBasePwrCtrl::write().

◆ status()

virtual Status gem5::ThreadContext::status ( ) const
pure virtual

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::minor::Execute::commitInst(), gem5::SimpleThread::copyState(), gem5::BaseKvmCPU::drainResume(), gem5::execveFunc(), gem5::exitImpl(), gem5::System::Threads::findFree(), gem5::System::Threads::numRunning(), gem5::SparcISA::ISA::processHSTickCompare(), gem5::SparcISA::ISA::processSTickCompare(), gem5::BaseRemoteGDB::scheduleInstCommitEvent(), gem5::setpgidFunc(), gem5::takeOverFrom(), gem5::DistIface::toggleSync(), gem5::minor::Execute::tryToBranch(), and gem5::pseudo_inst::wakeCPU().

◆ suspend()

virtual void gem5::ThreadContext::suspend ( )
pure virtual

Set the status to Suspended.

Implemented in gem5::Iris::ThreadContext, gem5::SimpleThread, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::cloneFunc(), gem5::SyscallDesc::doSyscall(), gem5::X86ISA::MicroHalt::execute(), gem5::SparcISA::ISA::setFSReg(), gem5::GPUComputeDriver::sleepCPU(), and gem5::FutexMap::suspend_bitset().

◆ takeOverFrom()

virtual void gem5::ThreadContext::takeOverFrom ( ThreadContext *  old_context)
pure virtual

Implemented in gem5::CheckerThreadContext< TC >, gem5::SimpleThread, gem5::Iris::ThreadContext, and gem5::o3::ThreadContext.

◆ threadId()

virtual int gem5::ThreadContext::threadId ( ) const
pure virtual

Implemented in gem5::SimpleThread, gem5::Iris::ThreadContext, gem5::CheckerThreadContext< TC >, and gem5::o3::ThreadContext.

Referenced by gem5::cloneFunc(), gem5::SimpleThread::copyState(), gem5::ArmISA::getAff0(), gem5::RiscvISA::ISA::globalClearExclusive(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::AbortFault< DataAbort >::invoke(), gem5::ArmISA::SystemError::invoke(), gem5::ArmISA::ArmSev::invoke(), gem5::RiscvISA::ISA::readMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::sendEvent(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::takeOverFrom().

Member Data Documentation

◆ DefaultFloatResult

const double gem5::ThreadContext::DefaultFloatResult = 0.0
static

Definition at line 47 of file guest_abi.test.cc.

Referenced by TEST().

◆ DefaultIntResult

const int gem5::ThreadContext::DefaultIntResult = 0
static

Definition at line 46 of file guest_abi.test.cc.

Referenced by TEST().

◆ floatResult

double gem5::ThreadContext::floatResult = DefaultFloatResult

Definition at line 50 of file guest_abi.test.cc.

Referenced by gem5::guest_abi::Result< TestABI_1D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > >::store(), gem5::guest_abi::Result< TestABI_2D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > >::store(), and TEST().

◆ floats

const double gem5::ThreadContext::floats
static
Initial value:
= {
10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0, 17.0
}

Definition at line 44 of file guest_abi.test.cc.

Referenced by gem5::guest_abi::Argument< TestABI_1D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > >::get(), gem5::guest_abi::Argument< TestABI_2D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > >::get(), test2DVoid(), and testIntVoid().

◆ intOffset

int gem5::ThreadContext::intOffset = 0

Definition at line 52 of file guest_abi.test.cc.

Referenced by TEST(), and testTcInit().

◆ intResult

int gem5::ThreadContext::intResult = DefaultIntResult

Definition at line 49 of file guest_abi.test.cc.

Referenced by gem5::guest_abi::Result< TestABI_1D, int >::store(), gem5::guest_abi::Result< TestABI_2D, int >::store(), and TEST().

◆ ints

const int gem5::ThreadContext::ints
static
Initial value:
= {
0, 1, 2, 3, 4, 5, 6, 7
}

Definition at line 43 of file guest_abi.test.cc.

Referenced by gem5::guest_abi::Argument< TestABI_1D, int >::get(), gem5::guest_abi::Argument< TestABI_Prepare, int >::get(), gem5::guest_abi::Argument< TestABI_2D, int >::get(), gem5::guest_abi::Argument< TestABI_TcInit, int >::get(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), and testTcInit().

◆ useForClone

bool gem5::ThreadContext::useForClone = false
protected

Definition at line 97 of file thread_context.hh.

Referenced by getUseForClone(), and setUseForClone().

The documentation for this class was generated from the following files:
Generated on Wed Jul 13 2022 10:40:15 for gem5 by doxygen 1.8.17