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isa.cc
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28 
29 #include "arch/sparc/isa.hh"
30 
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/decoder.hh"
33 #include "arch/sparc/interrupts.hh"
34 #include "arch/sparc/regs/float.hh"
35 #include "arch/sparc/regs/int.hh"
36 #include "arch/sparc/regs/misc.hh"
37 #include "arch/sparc/sparc_traits.hh"
38 #include "base/bitfield.hh"
39 #include "base/trace.hh"
40 #include "cpu/base.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/FloatRegs.hh"
43 #include "debug/IntRegs.hh"
44 #include "debug/MiscRegs.hh"
45 #include "debug/Timer.hh"
46 #include "params/SparcISA.hh"
47 
48 namespace gem5
49 {
50 
51 namespace SparcISA
52 {
53 
54 static PSTATE
55 buildPstateMask()
56 {
57  PSTATE mask = 0;
58  mask.ie = 1;
59  mask.priv = 1;
60  mask.am = 1;
61  mask.pef = 1;
62  mask.mm = 3;
63  mask.tle = 1;
64  mask.cle = 1;
65  mask.pid1 = 1;
66  return mask;
67 }
68 
69 static const PSTATE PstateMask = buildPstateMask();
70 
71 ISA::ISA(const Params &p) : BaseISA(p)
72 {
73  _regClasses.emplace_back(NumIntRegs, debug::IntRegs);
74  _regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
75  _regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
76  _regClasses.emplace_back(2, debug::IntRegs); // Not applicable for SPARC
77  _regClasses.emplace_back(1, debug::IntRegs); // Not applicable for SPARC
78  _regClasses.emplace_back(0, debug::IntRegs); // Not applicable for SPARC
79  _regClasses.emplace_back(NumMiscRegs, debug::MiscRegs);
80  clear();
81 }
82 
83 static void
84 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
85 {
86  uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
87 
88  // Read all the trap level dependent registers and save them off
89  for (int i = 1; i <= MaxTL; i++) {
90  src->setMiscRegNoEffect(MISCREG_TL, i);
91  dest->setMiscRegNoEffect(MISCREG_TL, i);
92 
93  dest->setMiscRegNoEffect(MISCREG_TT,
94  src->readMiscRegNoEffect(MISCREG_TT));
95  dest->setMiscRegNoEffect(MISCREG_TPC,
96  src->readMiscRegNoEffect(MISCREG_TPC));
97  dest->setMiscRegNoEffect(MISCREG_TNPC,
98  src->readMiscRegNoEffect(MISCREG_TNPC));
99  dest->setMiscRegNoEffect(MISCREG_TSTATE,
100  src->readMiscRegNoEffect(MISCREG_TSTATE));
101  }
102 
103  // Save off the traplevel
104  dest->setMiscRegNoEffect(MISCREG_TL, tl);
105  src->setMiscRegNoEffect(MISCREG_TL, tl);
106 
107 
108  // ASRs
109 // dest->setMiscRegNoEffect(MISCREG_Y,
110 // src->readMiscRegNoEffect(MISCREG_Y));
111 // dest->setMiscRegNoEffect(MISCREG_CCR,
112 // src->readMiscRegNoEffect(MISCREG_CCR));
113  dest->setMiscReg(MISCREG_ASI,
114  src->readMiscRegNoEffect(MISCREG_ASI));
115  dest->setMiscRegNoEffect(MISCREG_TICK,
116  src->readMiscRegNoEffect(MISCREG_TICK));
117  dest->setMiscRegNoEffect(MISCREG_FPRS,
118  src->readMiscRegNoEffect(MISCREG_FPRS));
119  dest->setMiscRegNoEffect(MISCREG_SOFTINT,
120  src->readMiscRegNoEffect(MISCREG_SOFTINT));
121  dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
122  src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
123  dest->setMiscRegNoEffect(MISCREG_STICK,
124  src->readMiscRegNoEffect(MISCREG_STICK));
125  dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
126  src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
127 
128  // Priv Registers
129  dest->setMiscRegNoEffect(MISCREG_TICK,
130  src->readMiscRegNoEffect(MISCREG_TICK));
131  dest->setMiscRegNoEffect(MISCREG_TBA,
132  src->readMiscRegNoEffect(MISCREG_TBA));
133  dest->setMiscRegNoEffect(MISCREG_PSTATE,
134  src->readMiscRegNoEffect(MISCREG_PSTATE));
135  dest->setMiscRegNoEffect(MISCREG_PIL,
136  src->readMiscRegNoEffect(MISCREG_PIL));
137  dest->setMiscReg(MISCREG_CWP,
138  src->readMiscRegNoEffect(MISCREG_CWP));
139 // dest->setMiscRegNoEffect(MISCREG_CANSAVE,
140 // src->readMiscRegNoEffect(MISCREG_CANSAVE));
141 // dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
142 // src->readMiscRegNoEffect(MISCREG_CANRESTORE));
143 // dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
144 // src->readMiscRegNoEffect(MISCREG_OTHERWIN));
145 // dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
146 // src->readMiscRegNoEffect(MISCREG_CLEANWIN));
147 // dest->setMiscRegNoEffect(MISCREG_WSTATE,
148 // src->readMiscRegNoEffect(MISCREG_WSTATE));
149  dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
150 
151  // Hyperprivilged registers
152  dest->setMiscRegNoEffect(MISCREG_HPSTATE,
153  src->readMiscRegNoEffect(MISCREG_HPSTATE));
154  dest->setMiscRegNoEffect(MISCREG_HINTP,
155  src->readMiscRegNoEffect(MISCREG_HINTP));
156  dest->setMiscRegNoEffect(MISCREG_HTBA,
157  src->readMiscRegNoEffect(MISCREG_HTBA));
158  dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
159  src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
160  dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
161  src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
162 
163  // FSR
164  dest->setMiscRegNoEffect(MISCREG_FSR,
165  src->readMiscRegNoEffect(MISCREG_FSR));
166 
167  // Strand Status Register
168  dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
169  src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
170 
171  // MMU Registers
172  dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
173  src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
174  dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
175  src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
176  dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
177  src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
178  dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
179  src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
180 
181  // Scratchpad Registers
182  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
183  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
184  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
185  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
186  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
187  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
188  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
189  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
190  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
191  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
192  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
193  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
194  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
195  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
196  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
197  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
198 
199  // Queue Registers
200  dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
201  src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
202  dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
203  src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
204  dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
205  src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
206  dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
207  src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
208  dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
209  src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
210  dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
211  src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
212  dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
213  src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
214  dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
215  src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
216 }
217 
218 void
219 ISA::copyRegsFrom(ThreadContext *src)
220 {
221  // First loop through the integer registers.
222  int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
223  int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
224  // Globals
225  for (int x = 0; x < MaxGL; ++x) {
226  src->setMiscReg(MISCREG_GL, x);
227  tc->setMiscReg(MISCREG_GL, x);
228  // Skip %g0 which is always zero.
229  for (int y = 1; y < 8; y++)
230  tc->setIntReg(y, src->readIntReg(y));
231  }
232  // Locals and ins. Outs are all also ins.
233  for (int x = 0; x < NWindows; ++x) {
234  src->setMiscReg(MISCREG_CWP, x);
235  tc->setMiscReg(MISCREG_CWP, x);
236  for (int y = 16; y < 32; y++)
237  tc->setIntReg(y, src->readIntReg(y));
238  }
239  // Microcode reg and pseudo int regs (misc regs in the integer regfile).
240  for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
241  tc->setIntReg(y, src->readIntReg(y));
242 
243  // Restore src's GL, CWP
244  src->setMiscReg(MISCREG_GL, old_gl);
245  src->setMiscReg(MISCREG_CWP, old_cwp);
246 
247 
248  // Then loop through the floating point registers.
249  for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
250  tc->setFloatReg(i, src->readFloatReg(i));
251  }
252 
253  // Copy misc. registers
254  copyMiscRegs(src, tc);
255 
256  // Lastly copy PC/NPC
257  tc->pcState(src->pcState());
258 }
259 
260 void
261 ISA::reloadRegMap()
262 {
263  installGlobals(gl, CurrentGlobalsOffset);
264  installWindow(cwp, CurrentWindowOffset);
265  // Microcode registers.
266  for (int i = 0; i < NumMicroIntRegs; i++)
267  intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16;
268  installGlobals(gl, NextGlobalsOffset);
269  installWindow(cwp - 1, NextWindowOffset);
270  installGlobals(gl, PreviousGlobalsOffset);
271  installWindow(cwp + 1, PreviousWindowOffset);
272 }
273 
274 void
275 ISA::installWindow(int cwp, int offset)
276 {
277  assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs);
278  RegIndex *mapChunk = intRegMap + offset;
279  for (int i = 0; i < NumWindowedRegs; i++)
280  mapChunk[i] = TotalGlobals +
281  ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed));
282 }
283 
284 void
285 ISA::installGlobals(int gl, int offset)
286 {
287  assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs);
288  RegIndex *mapChunk = intRegMap + offset;
289  mapChunk[0] = 0;
290  for (int i = 1; i < NumGlobalRegs; i++)
291  mapChunk[i] = i + gl * NumGlobalRegs;
292 }
293 
294 void
295 ISA::clear()
296 {
297  cwp = 0;
298  gl = 0;
299  reloadRegMap();
300 
301  // y = 0;
302  // ccr = 0;
303  asi = 0;
304  tick = 1ULL << 63;
305  fprs = 0;
306  gsr = 0;
307  softint = 0;
308  tick_cmpr = 0;
309  stick = 0;
310  stick_cmpr = 0;
311  memset(tpc, 0, sizeof(tpc));
312  memset(tnpc, 0, sizeof(tnpc));
313  memset(tstate, 0, sizeof(tstate));
314  memset(tt, 0, sizeof(tt));
315  tba = 0;
316  pstate = 0;
317  tl = 0;
318  pil = 0;
319  // cansave = 0;
320  // canrestore = 0;
321  // cleanwin = 0;
322  // otherwin = 0;
323  // wstate = 0;
324  // In a T1, bit 11 is apparently always 1
325  hpstate = 0;
326  hpstate.id = 1;
327  memset(htstate, 0, sizeof(htstate));
328  hintp = 0;
329  htba = 0;
330  hstick_cmpr = 0;
331  // This is set this way in Legion for some reason
332  strandStatusReg = 0x50000;
333  fsr = 0;
334 
335  priContext = 0;
336  secContext = 0;
337  partId = 0;
338  lsuCtrlReg = 0;
339 
340  memset(scratchPad, 0, sizeof(scratchPad));
341 
342  cpu_mondo_head = 0;
343  cpu_mondo_tail = 0;
344  dev_mondo_head = 0;
345  dev_mondo_tail = 0;
346  res_error_head = 0;
347  res_error_tail = 0;
348  nres_error_head = 0;
349  nres_error_tail = 0;
350 
351  // If one of these events is active, it's not obvious to me how to get
352  // rid of it cleanly. For now we'll just assert that they're not.
353  if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
354  panic("Tick comparison event active when clearing the ISA object.\n");
355 }
356 
357 RegVal
358 ISA::readMiscRegNoEffect(int miscReg) const
359 {
360 
361  // The three miscRegs are moved up from the switch statement
362  // due to more frequent calls.
363 
364  if (miscReg == MISCREG_GL)
365  return gl;
366  if (miscReg == MISCREG_CWP)
367  return cwp;
368  if (miscReg == MISCREG_TLB_DATA) {
369  /* Package up all the data for the tlb:
370  * 6666555555555544444444443333333333222222222211111111110000000000
371  * 3210987654321098765432109876543210987654321098765432109876543210
372  * secContext | priContext | |tl|partid| |||||^hpriv
373  * ||||^red
374  * |||^priv
375  * ||^am
376  * |^lsuim
377  * ^lsudm
378  */
379  return (uint64_t)hpstate.hpriv |
380  (uint64_t)hpstate.red << 1 |
381  (uint64_t)pstate.priv << 2 |
382  (uint64_t)pstate.am << 3 |
383  bits((uint64_t)lsuCtrlReg,3,2) << 4 |
384  bits((uint64_t)partId,7,0) << 8 |
385  bits((uint64_t)tl,2,0) << 16 |
386  (uint64_t)priContext << 32 |
387  (uint64_t)secContext << 48;
388  }
389 
390  switch (miscReg) {
391  // case MISCREG_TLB_DATA:
392  // [original contents see above]
393  // case MISCREG_Y:
394  // return y;
395  // case MISCREG_CCR:
396  // return ccr;
397  case MISCREG_ASI:
398  return asi;
399  case MISCREG_FPRS:
400  return fprs;
401  case MISCREG_TICK:
402  return tick;
403  case MISCREG_PCR:
404  panic("PCR not implemented\n");
405  case MISCREG_PIC:
406  panic("PIC not implemented\n");
407  case MISCREG_GSR:
408  return gsr;
409  case MISCREG_SOFTINT:
410  return softint;
411  case MISCREG_TICK_CMPR:
412  return tick_cmpr;
413  case MISCREG_STICK:
414  return stick;
415  case MISCREG_STICK_CMPR:
416  return stick_cmpr;
417 
419  case MISCREG_TPC:
420  return tpc[tl-1];
421  case MISCREG_TNPC:
422  return tnpc[tl-1];
423  case MISCREG_TSTATE:
424  return tstate[tl-1];
425  case MISCREG_TT:
426  return tt[tl-1];
427  case MISCREG_PRIVTICK:
428  panic("Priviliged access to tick registers not implemented\n");
429  case MISCREG_TBA:
430  return tba;
431  case MISCREG_PSTATE:
432  return (RegVal)pstate;
433  case MISCREG_TL:
434  return tl;
435  case MISCREG_PIL:
436  return pil;
437  // CWP, GL moved
438  // case MISCREG_CWP:
439  // return cwp;
440  // case MISCREG_CANSAVE:
441  // return cansave;
442  // case MISCREG_CANRESTORE:
443  // return canrestore;
444  // case MISCREG_CLEANWIN:
445  // return cleanwin;
446  // case MISCREG_OTHERWIN:
447  // return otherwin;
448  // case MISCREG_WSTATE:
449  // return wstate;
450  // case MISCREG_GL:
451  // return gl;
452 
454  case MISCREG_HPSTATE:
455  return (RegVal)hpstate;
456  case MISCREG_HTSTATE:
457  return htstate[tl-1];
458  case MISCREG_HINTP:
459  return hintp;
460  case MISCREG_HTBA:
461  return htba;
462  case MISCREG_STRAND_STS_REG:
463  return strandStatusReg;
464  case MISCREG_HSTICK_CMPR:
465  return hstick_cmpr;
466 
468  case MISCREG_FSR:
469  DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
470  return fsr;
471 
472  case MISCREG_MMU_P_CONTEXT:
473  return priContext;
474  case MISCREG_MMU_S_CONTEXT:
475  return secContext;
476  case MISCREG_MMU_PART_ID:
477  return partId;
478  case MISCREG_MMU_LSU_CTRL:
479  return lsuCtrlReg;
480 
481  case MISCREG_SCRATCHPAD_R0:
482  return scratchPad[0];
483  case MISCREG_SCRATCHPAD_R1:
484  return scratchPad[1];
485  case MISCREG_SCRATCHPAD_R2:
486  return scratchPad[2];
487  case MISCREG_SCRATCHPAD_R3:
488  return scratchPad[3];
489  case MISCREG_SCRATCHPAD_R4:
490  return scratchPad[4];
491  case MISCREG_SCRATCHPAD_R5:
492  return scratchPad[5];
493  case MISCREG_SCRATCHPAD_R6:
494  return scratchPad[6];
495  case MISCREG_SCRATCHPAD_R7:
496  return scratchPad[7];
497  case MISCREG_QUEUE_CPU_MONDO_HEAD:
498  return cpu_mondo_head;
499  case MISCREG_QUEUE_CPU_MONDO_TAIL:
500  return cpu_mondo_tail;
501  case MISCREG_QUEUE_DEV_MONDO_HEAD:
502  return dev_mondo_head;
503  case MISCREG_QUEUE_DEV_MONDO_TAIL:
504  return dev_mondo_tail;
505  case MISCREG_QUEUE_RES_ERROR_HEAD:
506  return res_error_head;
507  case MISCREG_QUEUE_RES_ERROR_TAIL:
508  return res_error_tail;
509  case MISCREG_QUEUE_NRES_ERROR_HEAD:
510  return nres_error_head;
511  case MISCREG_QUEUE_NRES_ERROR_TAIL:
512  return nres_error_tail;
513  default:
514  panic("Miscellaneous register %d not implemented\n", miscReg);
515  }
516 }
517 
518 RegVal
519 ISA::readMiscReg(int miscReg)
520 {
521  switch (miscReg) {
522  // tick and stick are aliased to each other in niagra
523  // well store the tick data in stick and the interrupt bit in tick
524  case MISCREG_STICK:
525  case MISCREG_TICK:
526  case MISCREG_PRIVTICK:
527  // I'm not sure why legion ignores the lowest two bits, but we'll go
528  // with it
529  // change from curCycle() to instCount() until we're done with legion
530  DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
531  tc->getCpuPtr()->instCount(), stick);
532  return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
533  mbits(tick,63,63);
534  case MISCREG_FPRS:
535  // in legion if fp is enabled du and dl are set
536  return fprs | 0x3;
537  case MISCREG_PCR:
538  case MISCREG_PIC:
539  panic("Performance Instrumentation not impl\n");
540  case MISCREG_SOFTINT_CLR:
541  case MISCREG_SOFTINT_SET:
542  panic("Can read from softint clr/set\n");
543  case MISCREG_SOFTINT:
544  case MISCREG_TICK_CMPR:
545  case MISCREG_STICK_CMPR:
546  case MISCREG_HINTP:
547  case MISCREG_HTSTATE:
548  case MISCREG_HTBA:
549  case MISCREG_HVER:
550  case MISCREG_STRAND_STS_REG:
551  case MISCREG_HSTICK_CMPR:
552  case MISCREG_QUEUE_CPU_MONDO_HEAD:
553  case MISCREG_QUEUE_CPU_MONDO_TAIL:
554  case MISCREG_QUEUE_DEV_MONDO_HEAD:
555  case MISCREG_QUEUE_DEV_MONDO_TAIL:
556  case MISCREG_QUEUE_RES_ERROR_HEAD:
557  case MISCREG_QUEUE_RES_ERROR_TAIL:
558  case MISCREG_QUEUE_NRES_ERROR_HEAD:
559  case MISCREG_QUEUE_NRES_ERROR_TAIL:
560  case MISCREG_HPSTATE:
561  return readFSReg(miscReg);
562  }
563  return readMiscRegNoEffect(miscReg);
564 }
565 
566 void
567 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
568 {
569  switch (miscReg) {
570 // case MISCREG_Y:
571 // y = val;
572 // break;
573 // case MISCREG_CCR:
574 // ccr = val;
575 // break;
576  case MISCREG_ASI:
577  asi = val;
578  break;
579  case MISCREG_FPRS:
580  fprs = val;
581  break;
582  case MISCREG_TICK:
583  tick = val;
584  break;
585  case MISCREG_PCR:
586  panic("PCR not implemented\n");
587  case MISCREG_PIC:
588  panic("PIC not implemented\n");
589  case MISCREG_GSR:
590  gsr = val;
591  break;
592  case MISCREG_SOFTINT:
593  softint = val;
594  break;
595  case MISCREG_TICK_CMPR:
596  tick_cmpr = val;
597  break;
598  case MISCREG_STICK:
599  stick = val;
600  break;
601  case MISCREG_STICK_CMPR:
602  stick_cmpr = val;
603  break;
604 
606  case MISCREG_TPC:
607  tpc[tl-1] = val;
608  break;
609  case MISCREG_TNPC:
610  tnpc[tl-1] = val;
611  break;
612  case MISCREG_TSTATE:
613  tstate[tl-1] = val;
614  break;
615  case MISCREG_TT:
616  tt[tl-1] = val;
617  break;
618  case MISCREG_PRIVTICK:
619  panic("Priviliged access to tick regesiters not implemented\n");
620  case MISCREG_TBA:
621  // clear lower 7 bits on writes.
622  tba = val & ~0x7FFFULL;
623  break;
624  case MISCREG_PSTATE:
625  pstate = (val & PstateMask);
626  break;
627  case MISCREG_TL:
628  tl = val;
629  break;
630  case MISCREG_PIL:
631  pil = val;
632  break;
633  case MISCREG_CWP:
634  cwp = val;
635  break;
636 // case MISCREG_CANSAVE:
637 // cansave = val;
638 // break;
639 // case MISCREG_CANRESTORE:
640 // canrestore = val;
641 // break;
642 // case MISCREG_CLEANWIN:
643 // cleanwin = val;
644 // break;
645 // case MISCREG_OTHERWIN:
646 // otherwin = val;
647 // break;
648 // case MISCREG_WSTATE:
649 // wstate = val;
650 // break;
651  case MISCREG_GL:
652  gl = val;
653  break;
654 
656  case MISCREG_HPSTATE:
657  hpstate = val;
658  break;
659  case MISCREG_HTSTATE:
660  htstate[tl-1] = val;
661  break;
662  case MISCREG_HINTP:
663  hintp = val;
664  break;
665  case MISCREG_HTBA:
666  htba = val;
667  break;
668  case MISCREG_STRAND_STS_REG:
669  strandStatusReg = val;
670  break;
671  case MISCREG_HSTICK_CMPR:
672  hstick_cmpr = val;
673  break;
674 
676  case MISCREG_FSR:
677  fsr = val;
678  DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
679  break;
680 
681  case MISCREG_MMU_P_CONTEXT:
682  priContext = val;
683  break;
684  case MISCREG_MMU_S_CONTEXT:
685  secContext = val;
686  break;
687  case MISCREG_MMU_PART_ID:
688  partId = val;
689  break;
690  case MISCREG_MMU_LSU_CTRL:
691  lsuCtrlReg = val;
692  break;
693 
694  case MISCREG_SCRATCHPAD_R0:
695  scratchPad[0] = val;
696  break;
697  case MISCREG_SCRATCHPAD_R1:
698  scratchPad[1] = val;
699  break;
700  case MISCREG_SCRATCHPAD_R2:
701  scratchPad[2] = val;
702  break;
703  case MISCREG_SCRATCHPAD_R3:
704  scratchPad[3] = val;
705  break;
706  case MISCREG_SCRATCHPAD_R4:
707  scratchPad[4] = val;
708  break;
709  case MISCREG_SCRATCHPAD_R5:
710  scratchPad[5] = val;
711  break;
712  case MISCREG_SCRATCHPAD_R6:
713  scratchPad[6] = val;
714  break;
715  case MISCREG_SCRATCHPAD_R7:
716  scratchPad[7] = val;
717  break;
718  case MISCREG_QUEUE_CPU_MONDO_HEAD:
719  cpu_mondo_head = val;
720  break;
721  case MISCREG_QUEUE_CPU_MONDO_TAIL:
722  cpu_mondo_tail = val;
723  break;
724  case MISCREG_QUEUE_DEV_MONDO_HEAD:
725  dev_mondo_head = val;
726  break;
727  case MISCREG_QUEUE_DEV_MONDO_TAIL:
728  dev_mondo_tail = val;
729  break;
730  case MISCREG_QUEUE_RES_ERROR_HEAD:
731  res_error_head = val;
732  break;
733  case MISCREG_QUEUE_RES_ERROR_TAIL:
734  res_error_tail = val;
735  break;
736  case MISCREG_QUEUE_NRES_ERROR_HEAD:
737  nres_error_head = val;
738  break;
739  case MISCREG_QUEUE_NRES_ERROR_TAIL:
740  nres_error_tail = val;
741  break;
742  default:
743  panic("Miscellaneous register %d not implemented\n", miscReg);
744  }
745 }
746 
747 void
748 ISA::setMiscReg(int miscReg, RegVal val)
749 {
750  RegVal new_val = val;
751 
752  switch (miscReg) {
753  case MISCREG_ASI:
754  tc->getDecoderPtr()->as<Decoder>().setContext(val);
755  break;
756  case MISCREG_STICK:
757  case MISCREG_TICK:
758  // stick and tick are same thing on niagra
759  // use stick for offset and tick for holding intrrupt bit
760  stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
761  tick = mbits(val,63,63);
762  DPRINTF(Timer, "Writing TICK=%#X\n", val);
763  break;
764  case MISCREG_FPRS:
765  // Configure the fpu based on the fprs
766  break;
767  case MISCREG_PCR:
768  // Set up performance counting based on pcr value
769  break;
770  case MISCREG_PSTATE:
771  pstate = val & PstateMask;
772  return;
773  case MISCREG_TL:
774  {
775  tl = val;
776  if (hpstate.tlz && tl == 0 && !hpstate.hpriv)
777  tc->getCpuPtr()->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
778  else
779  tc->getCpuPtr()->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
780  return;
781  }
782  case MISCREG_CWP:
783  new_val = val >= NWindows ? NWindows - 1 : val;
784  if (val >= NWindows)
785  new_val = NWindows - 1;
786 
787  installWindow(new_val, CurrentWindowOffset);
788  installWindow(new_val - 1, NextWindowOffset);
789  installWindow(new_val + 1, PreviousWindowOffset);
790  break;
791  case MISCREG_GL:
792  installGlobals(val, CurrentGlobalsOffset);
793  installGlobals(val, NextGlobalsOffset);
794  installGlobals(val, PreviousGlobalsOffset);
795  break;
796  case MISCREG_PIL:
797  case MISCREG_SOFTINT:
798  case MISCREG_SOFTINT_SET:
799  case MISCREG_SOFTINT_CLR:
800  case MISCREG_TICK_CMPR:
801  case MISCREG_STICK_CMPR:
802  case MISCREG_HINTP:
803  case MISCREG_HTSTATE:
804  case MISCREG_HTBA:
805  case MISCREG_HVER:
806  case MISCREG_STRAND_STS_REG:
807  case MISCREG_HSTICK_CMPR:
808  case MISCREG_QUEUE_CPU_MONDO_HEAD:
809  case MISCREG_QUEUE_CPU_MONDO_TAIL:
810  case MISCREG_QUEUE_DEV_MONDO_HEAD:
811  case MISCREG_QUEUE_DEV_MONDO_TAIL:
812  case MISCREG_QUEUE_RES_ERROR_HEAD:
813  case MISCREG_QUEUE_RES_ERROR_TAIL:
814  case MISCREG_QUEUE_NRES_ERROR_HEAD:
815  case MISCREG_QUEUE_NRES_ERROR_TAIL:
816  case MISCREG_HPSTATE:
817  setFSReg(miscReg, val);
818  return;
819  }
820  setMiscRegNoEffect(miscReg, new_val);
821 }
822 
823 void
824 ISA::serialize(CheckpointOut &cp) const
825 {
826  SERIALIZE_SCALAR(asi);
827  SERIALIZE_SCALAR(tick);
828  SERIALIZE_SCALAR(fprs);
829  SERIALIZE_SCALAR(gsr);
830  SERIALIZE_SCALAR(softint);
831  SERIALIZE_SCALAR(tick_cmpr);
832  SERIALIZE_SCALAR(stick);
833  SERIALIZE_SCALAR(stick_cmpr);
834  SERIALIZE_ARRAY(tpc,MaxTL);
835  SERIALIZE_ARRAY(tnpc,MaxTL);
836  SERIALIZE_ARRAY(tstate,MaxTL);
837  SERIALIZE_ARRAY(tt,MaxTL);
838  SERIALIZE_SCALAR(tba);
839  SERIALIZE_SCALAR(pstate);
840  SERIALIZE_SCALAR(tl);
841  SERIALIZE_SCALAR(pil);
842  SERIALIZE_SCALAR(cwp);
843  SERIALIZE_SCALAR(gl);
844  SERIALIZE_SCALAR(hpstate);
845  SERIALIZE_ARRAY(htstate,MaxTL);
846  SERIALIZE_SCALAR(hintp);
847  SERIALIZE_SCALAR(htba);
848  SERIALIZE_SCALAR(hstick_cmpr);
849  SERIALIZE_SCALAR(strandStatusReg);
850  SERIALIZE_SCALAR(fsr);
851  SERIALIZE_SCALAR(priContext);
852  SERIALIZE_SCALAR(secContext);
853  SERIALIZE_SCALAR(partId);
854  SERIALIZE_SCALAR(lsuCtrlReg);
855  SERIALIZE_ARRAY(scratchPad,8);
856  SERIALIZE_SCALAR(cpu_mondo_head);
857  SERIALIZE_SCALAR(cpu_mondo_tail);
858  SERIALIZE_SCALAR(dev_mondo_head);
859  SERIALIZE_SCALAR(dev_mondo_tail);
860  SERIALIZE_SCALAR(res_error_head);
861  SERIALIZE_SCALAR(res_error_tail);
862  SERIALIZE_SCALAR(nres_error_head);
863  SERIALIZE_SCALAR(nres_error_tail);
864 
865  Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
866  if (tickCompare && tickCompare->scheduled())
867  tick_cmp = tickCompare->when();
868  if (sTickCompare && sTickCompare->scheduled())
869  stick_cmp = sTickCompare->when();
870  if (hSTickCompare && hSTickCompare->scheduled())
871  hstick_cmp = hSTickCompare->when();
872 
873  SERIALIZE_SCALAR(tick_cmp);
874  SERIALIZE_SCALAR(stick_cmp);
875  SERIALIZE_SCALAR(hstick_cmp);
876 }
877 
878 void
879 ISA::unserialize(CheckpointIn &cp)
880 {
881  UNSERIALIZE_SCALAR(asi);
882  UNSERIALIZE_SCALAR(tick);
883  UNSERIALIZE_SCALAR(fprs);
884  UNSERIALIZE_SCALAR(gsr);
885  UNSERIALIZE_SCALAR(softint);
886  UNSERIALIZE_SCALAR(tick_cmpr);
887  UNSERIALIZE_SCALAR(stick);
888  UNSERIALIZE_SCALAR(stick_cmpr);
889  UNSERIALIZE_ARRAY(tpc,MaxTL);
890  UNSERIALIZE_ARRAY(tnpc,MaxTL);
891  UNSERIALIZE_ARRAY(tstate,MaxTL);
892  UNSERIALIZE_ARRAY(tt,MaxTL);
893  UNSERIALIZE_SCALAR(tba);
894  {
895  uint16_t pstate;
896  UNSERIALIZE_SCALAR(pstate);
897  this->pstate = pstate;
898  }
899  UNSERIALIZE_SCALAR(tl);
900  UNSERIALIZE_SCALAR(pil);
901  UNSERIALIZE_SCALAR(cwp);
902  UNSERIALIZE_SCALAR(gl);
903  reloadRegMap();
904  {
905  uint64_t hpstate;
906  UNSERIALIZE_SCALAR(hpstate);
907  this->hpstate = hpstate;
908  }
909  UNSERIALIZE_ARRAY(htstate,MaxTL);
910  UNSERIALIZE_SCALAR(hintp);
911  UNSERIALIZE_SCALAR(htba);
912  UNSERIALIZE_SCALAR(hstick_cmpr);
913  UNSERIALIZE_SCALAR(strandStatusReg);
914  UNSERIALIZE_SCALAR(fsr);
915  UNSERIALIZE_SCALAR(priContext);
916  UNSERIALIZE_SCALAR(secContext);
917  UNSERIALIZE_SCALAR(partId);
918  UNSERIALIZE_SCALAR(lsuCtrlReg);
919  UNSERIALIZE_ARRAY(scratchPad,8);
920  UNSERIALIZE_SCALAR(cpu_mondo_head);
921  UNSERIALIZE_SCALAR(cpu_mondo_tail);
922  UNSERIALIZE_SCALAR(dev_mondo_head);
923  UNSERIALIZE_SCALAR(dev_mondo_tail);
924  UNSERIALIZE_SCALAR(res_error_head);
925  UNSERIALIZE_SCALAR(res_error_tail);
926  UNSERIALIZE_SCALAR(nres_error_head);
927  UNSERIALIZE_SCALAR(nres_error_tail);
928 
929  Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
930  UNSERIALIZE_SCALAR(tick_cmp);
931  UNSERIALIZE_SCALAR(stick_cmp);
932  UNSERIALIZE_SCALAR(hstick_cmp);
933 
934  if (tick_cmp) {
935  tickCompare = new TickCompareEvent(this);
936  schedule(tickCompare, tick_cmp);
937  }
938  if (stick_cmp) {
939  sTickCompare = new STickCompareEvent(this);
940  schedule(sTickCompare, stick_cmp);
941  }
942  if (hstick_cmp) {
943  hSTickCompare = new HSTickCompareEvent(this);
944  schedule(hSTickCompare, hstick_cmp);
945  }
946 }
947 
948 } // namespace SparcISA
949 } // namespace gem5
gem5::SparcISA::Decoder
Definition: decoder.hh:46
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::SparcISA::MISCREG_TICK_CMPR
@ MISCREG_TICK_CMPR
Definition: misc.hh:54
gem5::SparcISA::ISA::TotalWindowed
static const int TotalWindowed
Definition: isa.hh:150
gem5::SparcISA::ISA::fsr
uint64_t fsr
Floating point misc registers.
Definition: isa.hh:102
gem5::SparcISA::ISA::CurrentWindowOffset
@ CurrentWindowOffset
Definition: isa.hh:155
gem5::Event::when
Tick when() const
Get the time that the event is scheduled.
Definition: eventq.hh:508
misc.hh
gem5::SparcISA::ISA::HSTickCompareEvent
EventWrapper< ISA, &ISA::processHSTickCompare > HSTickCompareEvent
Definition: isa.hh:141
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const
Definition: thread_context.hh:210
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SparcISA::ISA::nres_error_head
uint64_t nres_error_head
Definition: isa.hh:118
gem5::SparcISA::ISA::installWindow
void installWindow(int cwp, int offset)
Definition: isa.cc:275
gem5::SparcISA::ISA::strandStatusReg
uint64_t strandStatusReg
Definition: isa.hh:99
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::SparcISA::ISA::asi
uint8_t asi
Definition: isa.hh:61
gem5::SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: misc.hh:62
gem5::SparcISA::IT_TRAP_LEVEL_ZERO
@ IT_TRAP_LEVEL_ZERO
Definition: interrupts.hh:48
gem5::SparcISA::ISA::setFSReg
void setFSReg(int miscReg, RegVal val)
Definition: ua2005.cc:92
gem5::SparcISA::ISA::tnpc
uint64_t tnpc[MaxTL]
Definition: isa.hh:74
gem5::SparcISA::NumFloatArchRegs
const int NumFloatArchRegs
Definition: float.hh:39
gem5::InstDecoder::as
Type & as()
Definition: decoder.hh:71
gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD
@ MISCREG_QUEUE_DEV_MONDO_HEAD
Definition: misc.hh:107
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::SparcISA::ISA::stick
uint64_t stick
Definition: isa.hh:67
gem5::SparcISA::ISA::hSTickCompare
HSTickCompareEvent * hSTickCompare
Definition: isa.hh:142
gem5::SparcISA::MISCREG_STICK
@ MISCREG_STICK
Definition: misc.hh:55
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD
@ MISCREG_QUEUE_NRES_ERROR_HEAD
Definition: misc.hh:111
gem5::SparcISA::ISA::NextGlobalsOffset
@ NextGlobalsOffset
Definition: isa.hh:157
gem5::SparcISA::ISA::readFSReg
RegVal readFSReg(int miscReg)
Definition: ua2005.cc:248
gem5::SparcISA::MISCREG_SOFTINT_SET
@ MISCREG_SOFTINT_SET
Definition: misc.hh:51
gem5::SparcISA::ISA::tl
uint8_t tl
Definition: isa.hh:82
gem5::SparcISA::ISA::PreviousGlobalsOffset
@ PreviousGlobalsOffset
Definition: isa.hh:159
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::SparcISA::ISA::cwp
uint8_t cwp
Definition: isa.hh:84
gem5::SparcISA::ISA::tt
uint16_t tt[MaxTL]
Definition: isa.hh:77
gem5::SparcISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:824
gem5::SparcISA::ISA::CurrentGlobalsOffset
@ CurrentGlobalsOffset
Definition: isa.hh:154
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::SparcISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:219
gem5::SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:39
gem5::SparcISA::ISA::tpc
uint64_t tpc[MaxTL]
Definition: isa.hh:72
gem5::SparcISA::ISA::hstick_cmpr
uint64_t hstick_cmpr
Definition: isa.hh:97
gem5::SparcISA::MISCREG_HVER
@ MISCREG_HVER
Definition: misc.hh:81
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::ISA::res_error_head
uint64_t res_error_head
Definition: isa.hh:116
gem5::SparcISA::ISA::installGlobals
void installGlobals(int gl, int offset)
Definition: isa.cc:285
gem5::SparcISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:79
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::SparcISA::ISA::clear
void clear()
Definition: isa.cc:295
gem5::SparcISA::MISCREG_FPRS
@ MISCREG_FPRS
Definition: misc.hh:47
gem5::SparcISA::MISCREG_HINTP
@ MISCREG_HINTP
Definition: misc.hh:79
gem5::SparcISA::ISA::lsuCtrlReg
uint64_t lsuCtrlReg
Definition: isa.hh:108
gem5::SparcISA::ISA::scratchPad
uint64_t scratchPad[8]
Definition: isa.hh:110
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::SparcISA::ISA::NumGlobalRegs
static const int NumGlobalRegs
Definition: isa.hh:144
gem5::SparcISA::MISCREG_SCRATCHPAD_R4
@ MISCREG_SCRATCHPAD_R4
Definition: misc.hh:99
gem5::SparcISA::ISA::res_error_tail
uint64_t res_error_tail
Definition: isa.hh:117
gem5::SparcISA::ISA::tstate
uint64_t tstate[MaxTL]
Definition: isa.hh:76
gem5::SparcISA::ISA::htba
uint64_t htba
Definition: isa.hh:96
gem5::SparcISA::ISA::nres_error_tail
uint64_t nres_error_tail
Definition: isa.hh:119
gem5::SparcISA::MISCREG_HSTICK_CMPR
@ MISCREG_HSTICK_CMPR
Definition: misc.hh:83
gem5::SparcISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:879
gem5::SparcISA::ISA::fprs
uint8_t fprs
Definition: isa.hh:63
gem5::SparcISA::ISA::STickCompareEvent
EventWrapper< ISA, &ISA::processSTickCompare > STickCompareEvent
Definition: isa.hh:138
gem5::SparcISA::ISA::TickCompareEvent
EventWrapper< ISA, &ISA::processTickCompare > TickCompareEvent
Definition: isa.hh:135
gem5::SparcISA::ISA::PreviousWindowOffset
@ PreviousWindowOffset
Definition: isa.hh:160
gem5::SparcISA::MISCREG_SCRATCHPAD_R1
@ MISCREG_SCRATCHPAD_R1
Definition: misc.hh:96
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::SparcISA::ISA::gsr
uint64_t gsr
Definition: isa.hh:64
gem5::SparcISA::MISCREG_MMU_PART_ID
@ MISCREG_MMU_PART_ID
Definition: misc.hh:91
gem5::SparcISA::MISCREG_PRIVTICK
@ MISCREG_PRIVTICK
Definition: misc.hh:63
gem5::SparcISA::ISA::gl
uint8_t gl
Definition: isa.hh:90
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SparcISA::NumMiscRegs
const int NumMiscRegs
Definition: misc.hh:173
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::SparcISA::NumIntArchRegs
@ NumIntArchRegs
Definition: int.hh:55
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::SparcISA::ISA::RegsPerWindow
static const int RegsPerWindow
Definition: isa.hh:149
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
asi.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::VegaISA::x
Bitfield< 4 > x
Definition: pagetable.hh:61
gem5::SparcISA::MISCREG_MMU_S_CONTEXT
@ MISCREG_MMU_S_CONTEXT
Definition: misc.hh:90
gem5::SparcISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int miscReg, RegVal val)
Definition: isa.cc:567
gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL
@ MISCREG_QUEUE_DEV_MONDO_TAIL
Definition: misc.hh:108
gem5::SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: misc.hh:61
gem5::SparcISA::MISCREG_SCRATCHPAD_R7
@ MISCREG_SCRATCHPAD_R7
Definition: misc.hh:102
gem5::SparcISA::copyMiscRegs
static void copyMiscRegs(ThreadContext *src, ThreadContext *dest)
Definition: isa.cc:84
float.hh
gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL
@ MISCREG_QUEUE_CPU_MONDO_TAIL
Definition: misc.hh:106
gem5::SparcISA::ISA::tickCompare
TickCompareEvent * tickCompare
Definition: isa.hh:136
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
int.hh
gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD
@ MISCREG_QUEUE_RES_ERROR_HEAD
Definition: misc.hh:109
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::SparcISA::ISA::hpstate
HPSTATE hpstate
Hyperprivileged Registers.
Definition: isa.hh:93
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::SparcISA::ISA::dev_mondo_head
uint64_t dev_mondo_head
Definition: isa.hh:114
gem5::SparcISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:71
gem5::SparcISA::ISA::tba
uint64_t tba
Definition: isa.hh:79
gem5::SparcISA::MISCREG_PCR
@ MISCREG_PCR
Definition: misc.hh:48
gem5::SparcISA::ISA::secContext
uint16_t secContext
Definition: isa.hh:106
gem5::SparcISA::ISA::softint
uint64_t softint
Definition: isa.hh:65
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::SparcISA::ISA::priContext
uint16_t priContext
MMU Internal Registers.
Definition: isa.hh:105
gem5::SparcISA::MISCREG_SCRATCHPAD_R5
@ MISCREG_SCRATCHPAD_R5
Definition: misc.hh:100
gem5::SparcISA::ISA::TotalGlobals
static const int TotalGlobals
Definition: isa.hh:148
gem5::SparcISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int miscReg) const
Definition: isa.cc:358
gem5::SparcISA::ISA::hintp
uint64_t hintp
Definition: isa.hh:95
gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD
@ MISCREG_QUEUE_CPU_MONDO_HEAD
Definition: misc.hh:105
gem5::SparcISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:38
gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL
@ MISCREG_QUEUE_NRES_ERROR_TAIL
Definition: misc.hh:112
gem5::SparcISA::ISA::NextWindowOffset
@ NextWindowOffset
Definition: isa.hh:158
gem5::SparcISA::MISCREG_GSR
@ MISCREG_GSR
Definition: misc.hh:50
gem5::SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:44
gem5::SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: misc.hh:80
gem5::SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: misc.hh:60
gem5::SparcISA::ISA::reloadRegMap
void reloadRegMap()
Definition: isa.cc:261
gem5::SparcISA::ISA::pil
uint8_t pil
Definition: isa.hh:83
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: misc.hh:64
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: misc.hh:86
gem5::SparcISA::ISA::setMiscReg
void setMiscReg(int miscReg, RegVal val)
Definition: isa.cc:748
decoder.hh
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:40
gem5::MipsISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:254
interrupts.hh
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::ISA::tick_cmpr
uint64_t tick_cmpr
Definition: isa.hh:66
gem5::SparcISA::MISCREG_SCRATCHPAD_R3
@ MISCREG_SCRATCHPAD_R3
Definition: misc.hh:98
gem5::SparcISA::ISA::dev_mondo_tail
uint64_t dev_mondo_tail
Definition: isa.hh:115
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::ISA::partId
uint16_t partId
Definition: isa.hh:107
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::SparcISA::ISA::NumWindowedRegs
static const int NumWindowedRegs
Definition: isa.hh:145
gem5::SparcISA::MISCREG_TLB_DATA
@ MISCREG_TLB_DATA
Definition: misc.hh:115
gem5::SparcISA::MISCREG_SOFTINT_CLR
@ MISCREG_SOFTINT_CLR
Definition: misc.hh:52
trace.hh
gem5::SparcISA::ISA::readMiscReg
RegVal readMiscReg(int miscReg)
Definition: isa.cc:519
gem5::SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: misc.hh:78
gem5::SparcISA::ISA::stick_cmpr
uint64_t stick_cmpr
Definition: isa.hh:68
gem5::SparcISA::MISCREG_PIL
@ MISCREG_PIL
Definition: misc.hh:67
gem5::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:247
gem5::SparcISA::MISCREG_STRAND_STS_REG
@ MISCREG_STRAND_STS_REG
Definition: misc.hh:82
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::SparcISA::ISA::intRegMap
RegIndex intRegMap[TotalInstIntRegs]
Definition: isa.hh:164
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::SparcISA::ISA::tick
uint64_t tick
Definition: isa.hh:62
gem5::SparcISA::MISCREG_SCRATCHPAD_R6
@ MISCREG_SCRATCHPAD_R6
Definition: misc.hh:101
gem5::SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: misc.hh:74
gem5::SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: misc.hh:59
gem5::SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: misc.hh:92
gem5::SparcISA::MISCREG_PIC
@ MISCREG_PIC
Definition: misc.hh:49
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::SparcISA::ISA::MicroIntOffset
@ MicroIntOffset
Definition: isa.hh:156
gem5::SparcISA::ISA::sTickCompare
STickCompareEvent * sTickCompare
Definition: isa.hh:139
gem5::SparcISA::ISA::cpu_mondo_head
uint64_t cpu_mondo_head
Definition: isa.hh:112
gem5::SparcISA::PstateMask
static const PSTATE PstateMask
Definition: isa.cc:69
gem5::SparcISA::buildPstateMask
static PSTATE buildPstateMask()
Definition: isa.cc:55
sparc_traits.hh
gem5::SparcISA::MISCREG_STICK_CMPR
@ MISCREG_STICK_CMPR
Definition: misc.hh:56
gem5::SparcISA::ISA::pstate
PSTATE pstate
Definition: isa.hh:81
gem5::SparcISA::NumMicroIntRegs
@ NumMicroIntRegs
Definition: int.hh:67
gem5::SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: misc.hh:89
gem5::SparcISA::ISA::cpu_mondo_tail
uint64_t cpu_mondo_tail
Definition: isa.hh:113
isa.hh
thread_context.hh
gem5::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:241
gem5::SparcISA::MISCREG_SOFTINT
@ MISCREG_SOFTINT
Definition: misc.hh:53
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::SparcISA::MISCREG_SCRATCHPAD_R0
@ MISCREG_SCRATCHPAD_R0
Scratchpad regiscers.
Definition: misc.hh:95
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::SparcISA::MISCREG_SCRATCHPAD_R2
@ MISCREG_SCRATCHPAD_R2
Definition: misc.hh:97
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::SparcISA::ISA::htstate
uint64_t htstate[MaxTL]
Definition: isa.hh:94
gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL
@ MISCREG_QUEUE_RES_ERROR_TAIL
Definition: misc.hh:110
gem5::SparcISA::ISA::Params
SparcISAParams Params
Definition: isa.hh:236
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