tlb.hh

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/*
 * Copyright (c) 2007 The Hewlett-Packard Development Company
 * All rights reserved.
 *
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 * property including but not limited to intellectual property relating
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 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * met: redistributions of source code must retain the above copyright
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#ifndef __ARCH_X86_TLB_HH__
#define __ARCH_X86_TLB_HH__
 
#include <list>
#include <vector>
 
#include "arch/generic/tlb.hh"
#include "arch/x86/pagetable.hh"
#include "base/trie.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
#include "sim/stats.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace X86ISA
{
    class Walker;
 
    class TLB : public BaseTLB
    {
      protected:
        friend class Walker;
 
        typedef std::list<TlbEntry *> EntryList;
 
        uint32_t configAddress;
 
      public:
 
        typedef X86TLBParams Params;
        TLB(const Params &p);
 
        void takeOverFrom(BaseTLB *otlb) override {}
 
        TlbEntry *lookup(Addr va, bool update_lru = true);
 
        void setConfigAddress(uint32_t addr);
 
      protected:
 
        EntryList::iterator lookupIt(Addr va, bool update_lru = true);
 
        Walker * walker;
 
      public:
        Walker *getWalker();
 
        void flushAll() override;
 
        void flushNonGlobal();
 
        void demapPage(Addr va, uint64_t asn) override;
 
      protected:
        uint32_t size;
 
        std::vector<TlbEntry> tlb;
 
        EntryList freeList;
 
        TlbEntryTrie trie;
        uint64_t lruSeq;
 
        AddrRange m5opRange;
 
        struct TlbStats : public statistics::Group
        {
            TlbStats(statistics::Group *parent);
 
            statistics::Scalar rdAccesses;
            statistics::Scalar wrAccesses;
            statistics::Scalar rdMisses;
            statistics::Scalar wrMisses;
        } stats;
 
        Fault translateInt(bool read, RequestPtr req, ThreadContext *tc);
 
        Fault translate(const RequestPtr &req, ThreadContext *tc,
                BaseMMU::Translation *translation, BaseMMU::Mode mode,
                bool &delayedResponse, bool timing);
 
      public:
 
        void evictLRU();
 
        uint64_t
        nextSeq()
        {
            return ++lruSeq;
        }
 
        Fault translateAtomic(
            const RequestPtr &req, ThreadContext *tc,
            BaseMMU::Mode mode) override;
        Fault translateFunctional(
            const RequestPtr &req, ThreadContext *tc,
            BaseMMU::Mode mode) override;
        void translateTiming(
            const RequestPtr &req, ThreadContext *tc,
            BaseMMU::Translation *translation, BaseMMU::Mode mode) override;
 
        Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
                               BaseMMU::Mode mode) const override;
 
        TlbEntry *insert(Addr vpn, const TlbEntry &entry);
 
        // Checkpointing
        void serialize(CheckpointOut &cp) const override;
        void unserialize(CheckpointIn &cp) override;
 
        Port *getTableWalkerPort() override;
    };
 
} // namespace X86ISA
} // namespace gem5
 
#endif // __ARCH_X86_TLB_HH__