gem5 v23.0.0.0
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misc.cc
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1/*
2 * Copyright (c) 2010-2013, 2015-2023 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "arch/arm/regs/misc.hh"
39
40#include <tuple>
41
42#include "arch/arm/insts/misc64.hh"
43#include "arch/arm/isa.hh"
44#include "base/logging.hh"
45#include "cpu/thread_context.hh"
46#include "dev/arm/gic_v3_cpu_interface.hh"
47#include "sim/full_system.hh"
48#include "params/ArmISA.hh"
49
50namespace gem5
51{
52
53namespace ArmISA
54{
55
56namespace
57{
58
59std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
60 // MCR/MRC regs
61 { MiscRegNum32(14, 0, 0, 0, 0), MISCREG_DBGDIDR },
62 { MiscRegNum32(14, 0, 0, 0, 2), MISCREG_DBGDTRRXext },
63 { MiscRegNum32(14, 0, 0, 0, 4), MISCREG_DBGBVR0 },
64 { MiscRegNum32(14, 0, 0, 0, 5), MISCREG_DBGBCR0 },
65 { MiscRegNum32(14, 0, 0, 0, 6), MISCREG_DBGWVR0 },
66 { MiscRegNum32(14, 0, 0, 0, 7), MISCREG_DBGWCR0 },
67 { MiscRegNum32(14, 0, 0, 1, 0), MISCREG_DBGDSCRint },
68 { MiscRegNum32(14, 0, 0, 1, 4), MISCREG_DBGBVR1 },
69 { MiscRegNum32(14, 0, 0, 1, 5), MISCREG_DBGBCR1 },
70 { MiscRegNum32(14, 0, 0, 1, 6), MISCREG_DBGWVR1 },
71 { MiscRegNum32(14, 0, 0, 1, 7), MISCREG_DBGWCR1 },
72 { MiscRegNum32(14, 0, 0, 2, 2), MISCREG_DBGDSCRext },
73 { MiscRegNum32(14, 0, 0, 2, 4), MISCREG_DBGBVR2 },
74 { MiscRegNum32(14, 0, 0, 2, 5), MISCREG_DBGBCR2 },
75 { MiscRegNum32(14, 0, 0, 2, 6), MISCREG_DBGWVR2 },
76 { MiscRegNum32(14, 0, 0, 2, 7), MISCREG_DBGWCR2 },
77 { MiscRegNum32(14, 0, 0, 3, 2), MISCREG_DBGDTRTXext },
78 { MiscRegNum32(14, 0, 0, 3, 4), MISCREG_DBGBVR3 },
79 { MiscRegNum32(14, 0, 0, 3, 5), MISCREG_DBGBCR3 },
80 { MiscRegNum32(14, 0, 0, 3, 6), MISCREG_DBGWVR3 },
81 { MiscRegNum32(14, 0, 0, 3, 7), MISCREG_DBGWCR3 },
82 { MiscRegNum32(14, 0, 0, 4, 4), MISCREG_DBGBVR4 },
83 { MiscRegNum32(14, 0, 0, 4, 5), MISCREG_DBGBCR4 },
84 { MiscRegNum32(14, 0, 0, 4, 6), MISCREG_DBGWVR4 },
85 { MiscRegNum32(14, 0, 0, 4, 7), MISCREG_DBGWCR4 },
86 { MiscRegNum32(14, 0, 0, 5, 4), MISCREG_DBGBVR5 },
87 { MiscRegNum32(14, 0, 0, 5, 5), MISCREG_DBGBCR5 },
88 { MiscRegNum32(14, 0, 0, 5, 6), MISCREG_DBGWVR5 },
89 { MiscRegNum32(14, 0, 0, 5, 7), MISCREG_DBGWCR5 },
90 { MiscRegNum32(14, 0, 0, 6, 2), MISCREG_DBGOSECCR },
91 { MiscRegNum32(14, 0, 0, 6, 4), MISCREG_DBGBVR6 },
92 { MiscRegNum32(14, 0, 0, 6, 5), MISCREG_DBGBCR6 },
93 { MiscRegNum32(14, 0, 0, 6, 6), MISCREG_DBGWVR6 },
94 { MiscRegNum32(14, 0, 0, 6, 7), MISCREG_DBGWCR6 },
95 { MiscRegNum32(14, 0, 0, 7, 0), MISCREG_DBGVCR },
96 { MiscRegNum32(14, 0, 0, 7, 4), MISCREG_DBGBVR7 },
97 { MiscRegNum32(14, 0, 0, 7, 5), MISCREG_DBGBCR7 },
98 { MiscRegNum32(14, 0, 0, 7, 6), MISCREG_DBGWVR7 },
99 { MiscRegNum32(14, 0, 0, 7, 7), MISCREG_DBGWCR7 },
100 { MiscRegNum32(14, 0, 0, 8, 4), MISCREG_DBGBVR8 },
101 { MiscRegNum32(14, 0, 0, 8, 5), MISCREG_DBGBCR8 },
102 { MiscRegNum32(14, 0, 0, 8, 6), MISCREG_DBGWVR8 },
103 { MiscRegNum32(14, 0, 0, 8, 7), MISCREG_DBGWCR8 },
104 { MiscRegNum32(14, 0, 0, 9, 4), MISCREG_DBGBVR9 },
105 { MiscRegNum32(14, 0, 0, 9, 5), MISCREG_DBGBCR9 },
106 { MiscRegNum32(14, 0, 0, 9, 6), MISCREG_DBGWVR9 },
107 { MiscRegNum32(14, 0, 0, 9, 7), MISCREG_DBGWCR9 },
108 { MiscRegNum32(14, 0, 0, 10, 4), MISCREG_DBGBVR10 },
109 { MiscRegNum32(14, 0, 0, 10, 5), MISCREG_DBGBCR10 },
110 { MiscRegNum32(14, 0, 0, 10, 6), MISCREG_DBGWVR10 },
111 { MiscRegNum32(14, 0, 0, 10, 7), MISCREG_DBGWCR10 },
112 { MiscRegNum32(14, 0, 0, 11, 4), MISCREG_DBGBVR11 },
113 { MiscRegNum32(14, 0, 0, 11, 5), MISCREG_DBGBCR11 },
114 { MiscRegNum32(14, 0, 0, 11, 6), MISCREG_DBGWVR11 },
115 { MiscRegNum32(14, 0, 0, 11, 7), MISCREG_DBGWCR11 },
116 { MiscRegNum32(14, 0, 0, 12, 4), MISCREG_DBGBVR12 },
117 { MiscRegNum32(14, 0, 0, 12, 5), MISCREG_DBGBCR12 },
118 { MiscRegNum32(14, 0, 0, 12, 6), MISCREG_DBGWVR12 },
119 { MiscRegNum32(14, 0, 0, 12, 7), MISCREG_DBGWCR12 },
120 { MiscRegNum32(14, 0, 0, 13, 4), MISCREG_DBGBVR13 },
121 { MiscRegNum32(14, 0, 0, 13, 5), MISCREG_DBGBCR13 },
122 { MiscRegNum32(14, 0, 0, 13, 6), MISCREG_DBGWVR13 },
123 { MiscRegNum32(14, 0, 0, 13, 7), MISCREG_DBGWCR13 },
124 { MiscRegNum32(14, 0, 0, 14, 4), MISCREG_DBGBVR14 },
125 { MiscRegNum32(14, 0, 0, 14, 5), MISCREG_DBGBCR14 },
126 { MiscRegNum32(14, 0, 0, 14, 6), MISCREG_DBGWVR14 },
127 { MiscRegNum32(14, 0, 0, 14, 7), MISCREG_DBGWCR14 },
128 { MiscRegNum32(14, 0, 0, 15, 4), MISCREG_DBGBVR15 },
129 { MiscRegNum32(14, 0, 0, 15, 5), MISCREG_DBGBCR15 },
130 { MiscRegNum32(14, 0, 0, 15, 6), MISCREG_DBGWVR15 },
131 { MiscRegNum32(14, 0, 0, 15, 7), MISCREG_DBGWCR15 },
132 { MiscRegNum32(14, 0, 1, 0, 1), MISCREG_DBGBXVR0 },
133 { MiscRegNum32(14, 0, 1, 0, 4), MISCREG_DBGOSLAR },
134 { MiscRegNum32(14, 0, 1, 1, 1), MISCREG_DBGBXVR1 },
135 { MiscRegNum32(14, 0, 1, 1, 4), MISCREG_DBGOSLSR },
136 { MiscRegNum32(14, 0, 1, 2, 1), MISCREG_DBGBXVR2 },
137 { MiscRegNum32(14, 0, 1, 3, 1), MISCREG_DBGBXVR3 },
138 { MiscRegNum32(14, 0, 1, 3, 4), MISCREG_DBGOSDLR },
139 { MiscRegNum32(14, 0, 1, 4, 1), MISCREG_DBGBXVR4 },
140 { MiscRegNum32(14, 0, 1, 4, 4), MISCREG_DBGPRCR },
141 { MiscRegNum32(14, 0, 1, 5, 1), MISCREG_DBGBXVR5 },
142 { MiscRegNum32(14, 0, 1, 6, 1), MISCREG_DBGBXVR6 },
143 { MiscRegNum32(14, 0, 1, 7, 1), MISCREG_DBGBXVR7 },
144 { MiscRegNum32(14, 0, 1, 8, 1), MISCREG_DBGBXVR8 },
145 { MiscRegNum32(14, 0, 1, 9, 1), MISCREG_DBGBXVR9 },
146 { MiscRegNum32(14, 0, 1, 10, 1), MISCREG_DBGBXVR10 },
147 { MiscRegNum32(14, 0, 1, 11, 1), MISCREG_DBGBXVR11 },
148 { MiscRegNum32(14, 0, 1, 12, 1), MISCREG_DBGBXVR12 },
149 { MiscRegNum32(14, 0, 1, 13, 1), MISCREG_DBGBXVR13 },
150 { MiscRegNum32(14, 0, 1, 14, 1), MISCREG_DBGBXVR14 },
151 { MiscRegNum32(14, 0, 1, 15, 1), MISCREG_DBGBXVR15 },
152 { MiscRegNum32(14, 6, 1, 0, 0), MISCREG_TEEHBR },
153 { MiscRegNum32(14, 7, 0, 0, 0), MISCREG_JIDR },
154 { MiscRegNum32(14, 7, 1, 0, 0), MISCREG_JOSCR },
155 { MiscRegNum32(14, 7, 2, 0, 0), MISCREG_JMCR },
156 { MiscRegNum32(15, 0, 0, 0, 0), MISCREG_MIDR },
157 { MiscRegNum32(15, 0, 0, 0, 1), MISCREG_CTR },
158 { MiscRegNum32(15, 0, 0, 0, 2), MISCREG_TCMTR },
159 { MiscRegNum32(15, 0, 0, 0, 3), MISCREG_TLBTR },
160 { MiscRegNum32(15, 0, 0, 0, 4), MISCREG_MIDR },
161 { MiscRegNum32(15, 0, 0, 0, 5), MISCREG_MPIDR },
162 { MiscRegNum32(15, 0, 0, 0, 6), MISCREG_REVIDR },
163 { MiscRegNum32(15, 0, 0, 0, 7), MISCREG_MIDR },
164 { MiscRegNum32(15, 0, 0, 1, 0), MISCREG_ID_PFR0 },
165 { MiscRegNum32(15, 0, 0, 1, 1), MISCREG_ID_PFR1 },
166 { MiscRegNum32(15, 0, 0, 1, 2), MISCREG_ID_DFR0 },
167 { MiscRegNum32(15, 0, 0, 1, 3), MISCREG_ID_AFR0 },
168 { MiscRegNum32(15, 0, 0, 1, 4), MISCREG_ID_MMFR0 },
169 { MiscRegNum32(15, 0, 0, 1, 5), MISCREG_ID_MMFR1 },
170 { MiscRegNum32(15, 0, 0, 1, 6), MISCREG_ID_MMFR2 },
171 { MiscRegNum32(15, 0, 0, 1, 7), MISCREG_ID_MMFR3 },
172 { MiscRegNum32(15, 0, 0, 2, 0), MISCREG_ID_ISAR0 },
173 { MiscRegNum32(15, 0, 0, 2, 1), MISCREG_ID_ISAR1 },
174 { MiscRegNum32(15, 0, 0, 2, 2), MISCREG_ID_ISAR2 },
175 { MiscRegNum32(15, 0, 0, 2, 3), MISCREG_ID_ISAR3 },
176 { MiscRegNum32(15, 0, 0, 2, 4), MISCREG_ID_ISAR4 },
177 { MiscRegNum32(15, 0, 0, 2, 5), MISCREG_ID_ISAR5 },
178 { MiscRegNum32(15, 0, 0, 2, 6), MISCREG_ID_MMFR4 },
179 { MiscRegNum32(15, 0, 0, 2, 7), MISCREG_ID_ISAR6 },
180 { MiscRegNum32(15, 0, 0, 3, 0), MISCREG_RAZ },
181 { MiscRegNum32(15, 0, 0, 3, 1), MISCREG_RAZ },
182 { MiscRegNum32(15, 0, 0, 3, 2), MISCREG_RAZ },
183 { MiscRegNum32(15, 0, 0, 3, 3), MISCREG_RAZ },
184 { MiscRegNum32(15, 0, 0, 3, 4), MISCREG_RAZ },
185 { MiscRegNum32(15, 0, 0, 3, 5), MISCREG_RAZ },
186 { MiscRegNum32(15, 0, 0, 3, 6), MISCREG_RAZ },
187 { MiscRegNum32(15, 0, 0, 3, 7), MISCREG_RAZ },
188 { MiscRegNum32(15, 0, 0, 4, 0), MISCREG_RAZ },
189 { MiscRegNum32(15, 0, 0, 4, 1), MISCREG_RAZ },
190 { MiscRegNum32(15, 0, 0, 4, 2), MISCREG_RAZ },
191 { MiscRegNum32(15, 0, 0, 4, 3), MISCREG_RAZ },
192 { MiscRegNum32(15, 0, 0, 4, 4), MISCREG_RAZ },
193 { MiscRegNum32(15, 0, 0, 4, 5), MISCREG_RAZ },
194 { MiscRegNum32(15, 0, 0, 4, 6), MISCREG_RAZ },
195 { MiscRegNum32(15, 0, 0, 4, 7), MISCREG_RAZ },
196 { MiscRegNum32(15, 0, 0, 5, 0), MISCREG_RAZ },
197 { MiscRegNum32(15, 0, 0, 5, 1), MISCREG_RAZ },
198 { MiscRegNum32(15, 0, 0, 5, 2), MISCREG_RAZ },
199 { MiscRegNum32(15, 0, 0, 5, 3), MISCREG_RAZ },
200 { MiscRegNum32(15, 0, 0, 5, 4), MISCREG_RAZ },
201 { MiscRegNum32(15, 0, 0, 5, 5), MISCREG_RAZ },
202 { MiscRegNum32(15, 0, 0, 5, 6), MISCREG_RAZ },
203 { MiscRegNum32(15, 0, 0, 5, 7), MISCREG_RAZ },
204 { MiscRegNum32(15, 0, 0, 6, 0), MISCREG_RAZ },
205 { MiscRegNum32(15, 0, 0, 6, 1), MISCREG_RAZ },
206 { MiscRegNum32(15, 0, 0, 6, 2), MISCREG_RAZ },
207 { MiscRegNum32(15, 0, 0, 6, 3), MISCREG_RAZ },
208 { MiscRegNum32(15, 0, 0, 6, 4), MISCREG_RAZ },
209 { MiscRegNum32(15, 0, 0, 6, 5), MISCREG_RAZ },
210 { MiscRegNum32(15, 0, 0, 6, 6), MISCREG_RAZ },
211 { MiscRegNum32(15, 0, 0, 6, 7), MISCREG_RAZ },
212 { MiscRegNum32(15, 0, 0, 7, 0), MISCREG_RAZ },
213 { MiscRegNum32(15, 0, 0, 7, 1), MISCREG_RAZ },
214 { MiscRegNum32(15, 0, 0, 7, 2), MISCREG_RAZ },
215 { MiscRegNum32(15, 0, 0, 7, 3), MISCREG_RAZ },
216 { MiscRegNum32(15, 0, 0, 7, 4), MISCREG_RAZ },
217 { MiscRegNum32(15, 0, 0, 7, 5), MISCREG_RAZ },
218 { MiscRegNum32(15, 0, 0, 7, 6), MISCREG_RAZ },
219 { MiscRegNum32(15, 0, 0, 7, 7), MISCREG_RAZ },
220 { MiscRegNum32(15, 0, 0, 8, 0), MISCREG_RAZ },
221 { MiscRegNum32(15, 0, 0, 8, 1), MISCREG_RAZ },
222 { MiscRegNum32(15, 0, 0, 8, 2), MISCREG_RAZ },
223 { MiscRegNum32(15, 0, 0, 8, 3), MISCREG_RAZ },
224 { MiscRegNum32(15, 0, 0, 8, 4), MISCREG_RAZ },
225 { MiscRegNum32(15, 0, 0, 8, 5), MISCREG_RAZ },
226 { MiscRegNum32(15, 0, 0, 8, 6), MISCREG_RAZ },
227 { MiscRegNum32(15, 0, 0, 8, 7), MISCREG_RAZ },
228 { MiscRegNum32(15, 0, 0, 9, 0), MISCREG_RAZ },
229 { MiscRegNum32(15, 0, 0, 9, 1), MISCREG_RAZ },
230 { MiscRegNum32(15, 0, 0, 9, 2), MISCREG_RAZ },
231 { MiscRegNum32(15, 0, 0, 9, 3), MISCREG_RAZ },
232 { MiscRegNum32(15, 0, 0, 9, 4), MISCREG_RAZ },
233 { MiscRegNum32(15, 0, 0, 9, 5), MISCREG_RAZ },
234 { MiscRegNum32(15, 0, 0, 9, 6), MISCREG_RAZ },
235 { MiscRegNum32(15, 0, 0, 9, 7), MISCREG_RAZ },
236 { MiscRegNum32(15, 0, 0, 10, 0), MISCREG_RAZ },
237 { MiscRegNum32(15, 0, 0, 10, 1), MISCREG_RAZ },
238 { MiscRegNum32(15, 0, 0, 10, 2), MISCREG_RAZ },
239 { MiscRegNum32(15, 0, 0, 10, 3), MISCREG_RAZ },
240 { MiscRegNum32(15, 0, 0, 10, 4), MISCREG_RAZ },
241 { MiscRegNum32(15, 0, 0, 10, 5), MISCREG_RAZ },
242 { MiscRegNum32(15, 0, 0, 10, 6), MISCREG_RAZ },
243 { MiscRegNum32(15, 0, 0, 10, 7), MISCREG_RAZ },
244 { MiscRegNum32(15, 0, 0, 11, 0), MISCREG_RAZ },
245 { MiscRegNum32(15, 0, 0, 11, 1), MISCREG_RAZ },
246 { MiscRegNum32(15, 0, 0, 11, 2), MISCREG_RAZ },
247 { MiscRegNum32(15, 0, 0, 11, 3), MISCREG_RAZ },
248 { MiscRegNum32(15, 0, 0, 11, 4), MISCREG_RAZ },
249 { MiscRegNum32(15, 0, 0, 11, 5), MISCREG_RAZ },
250 { MiscRegNum32(15, 0, 0, 11, 6), MISCREG_RAZ },
251 { MiscRegNum32(15, 0, 0, 11, 7), MISCREG_RAZ },
252 { MiscRegNum32(15, 0, 0, 12, 0), MISCREG_RAZ },
253 { MiscRegNum32(15, 0, 0, 12, 1), MISCREG_RAZ },
254 { MiscRegNum32(15, 0, 0, 12, 2), MISCREG_RAZ },
255 { MiscRegNum32(15, 0, 0, 12, 3), MISCREG_RAZ },
256 { MiscRegNum32(15, 0, 0, 12, 4), MISCREG_RAZ },
257 { MiscRegNum32(15, 0, 0, 12, 5), MISCREG_RAZ },
258 { MiscRegNum32(15, 0, 0, 12, 6), MISCREG_RAZ },
259 { MiscRegNum32(15, 0, 0, 12, 7), MISCREG_RAZ },
260 { MiscRegNum32(15, 0, 0, 13, 0), MISCREG_RAZ },
261 { MiscRegNum32(15, 0, 0, 13, 1), MISCREG_RAZ },
262 { MiscRegNum32(15, 0, 0, 13, 2), MISCREG_RAZ },
263 { MiscRegNum32(15, 0, 0, 13, 3), MISCREG_RAZ },
264 { MiscRegNum32(15, 0, 0, 13, 4), MISCREG_RAZ },
265 { MiscRegNum32(15, 0, 0, 13, 5), MISCREG_RAZ },
266 { MiscRegNum32(15, 0, 0, 13, 6), MISCREG_RAZ },
267 { MiscRegNum32(15, 0, 0, 13, 7), MISCREG_RAZ },
268 { MiscRegNum32(15, 0, 0, 14, 0), MISCREG_RAZ },
269 { MiscRegNum32(15, 0, 0, 14, 1), MISCREG_RAZ },
270 { MiscRegNum32(15, 0, 0, 14, 2), MISCREG_RAZ },
271 { MiscRegNum32(15, 0, 0, 14, 3), MISCREG_RAZ },
272 { MiscRegNum32(15, 0, 0, 14, 4), MISCREG_RAZ },
273 { MiscRegNum32(15, 0, 0, 14, 5), MISCREG_RAZ },
274 { MiscRegNum32(15, 0, 0, 14, 6), MISCREG_RAZ },
275 { MiscRegNum32(15, 0, 0, 14, 7), MISCREG_RAZ },
276 { MiscRegNum32(15, 0, 0, 15, 0), MISCREG_RAZ },
277 { MiscRegNum32(15, 0, 0, 15, 1), MISCREG_RAZ },
278 { MiscRegNum32(15, 0, 0, 15, 2), MISCREG_RAZ },
279 { MiscRegNum32(15, 0, 0, 15, 3), MISCREG_RAZ },
280 { MiscRegNum32(15, 0, 0, 15, 4), MISCREG_RAZ },
281 { MiscRegNum32(15, 0, 0, 15, 5), MISCREG_RAZ },
282 { MiscRegNum32(15, 0, 0, 15, 6), MISCREG_RAZ },
283 { MiscRegNum32(15, 0, 0, 15, 7), MISCREG_RAZ },
284 { MiscRegNum32(15, 0, 1, 0, 0), MISCREG_SCTLR },
285 { MiscRegNum32(15, 0, 1, 0, 1), MISCREG_ACTLR },
286 { MiscRegNum32(15, 0, 1, 0, 2), MISCREG_CPACR },
287 { MiscRegNum32(15, 0, 1, 1, 0), MISCREG_SCR },
288 { MiscRegNum32(15, 0, 1, 1, 1), MISCREG_SDER },
289 { MiscRegNum32(15, 0, 1, 1, 2), MISCREG_NSACR },
290 { MiscRegNum32(15, 0, 1, 3, 1), MISCREG_SDCR },
291 { MiscRegNum32(15, 0, 2, 0, 0), MISCREG_TTBR0 },
292 { MiscRegNum32(15, 0, 2, 0, 1), MISCREG_TTBR1 },
293 { MiscRegNum32(15, 0, 2, 0, 2), MISCREG_TTBCR },
294 { MiscRegNum32(15, 0, 3, 0, 0), MISCREG_DACR },
295 { MiscRegNum32(15, 0, 4, 6, 0), MISCREG_ICC_PMR },
296 { MiscRegNum32(15, 0, 5, 0, 0), MISCREG_DFSR },
297 { MiscRegNum32(15, 0, 5, 0, 1), MISCREG_IFSR },
298 { MiscRegNum32(15, 0, 5, 1, 0), MISCREG_ADFSR },
299 { MiscRegNum32(15, 0, 5, 1, 1), MISCREG_AIFSR },
300 { MiscRegNum32(15, 0, 6, 0, 0), MISCREG_DFAR },
301 { MiscRegNum32(15, 0, 6, 0, 2), MISCREG_IFAR },
302 { MiscRegNum32(15, 0, 7, 0, 4), MISCREG_NOP },
303 { MiscRegNum32(15, 0, 7, 1, 0), MISCREG_ICIALLUIS },
304 { MiscRegNum32(15, 0, 7, 1, 6), MISCREG_BPIALLIS },
305 { MiscRegNum32(15, 0, 7, 2, 7), MISCREG_DBGDEVID0 },
306 { MiscRegNum32(15, 0, 7, 4, 0), MISCREG_PAR },
307 { MiscRegNum32(15, 0, 7, 5, 0), MISCREG_ICIALLU },
308 { MiscRegNum32(15, 0, 7, 5, 1), MISCREG_ICIMVAU },
309 { MiscRegNum32(15, 0, 7, 5, 4), MISCREG_CP15ISB },
310 { MiscRegNum32(15, 0, 7, 5, 6), MISCREG_BPIALL },
311 { MiscRegNum32(15, 0, 7, 5, 7), MISCREG_BPIMVA },
312 { MiscRegNum32(15, 0, 7, 6, 1), MISCREG_DCIMVAC },
313 { MiscRegNum32(15, 0, 7, 6, 2), MISCREG_DCISW },
314 { MiscRegNum32(15, 0, 7, 8, 0), MISCREG_ATS1CPR },
315 { MiscRegNum32(15, 0, 7, 8, 1), MISCREG_ATS1CPW },
316 { MiscRegNum32(15, 0, 7, 8, 2), MISCREG_ATS1CUR },
317 { MiscRegNum32(15, 0, 7, 8, 3), MISCREG_ATS1CUW },
318 { MiscRegNum32(15, 0, 7, 8, 4), MISCREG_ATS12NSOPR },
319 { MiscRegNum32(15, 0, 7, 8, 5), MISCREG_ATS12NSOPW },
320 { MiscRegNum32(15, 0, 7, 8, 6), MISCREG_ATS12NSOUR },
321 { MiscRegNum32(15, 0, 7, 8, 7), MISCREG_ATS12NSOUW },
322 { MiscRegNum32(15, 0, 7, 10, 1), MISCREG_DCCMVAC },
323 { MiscRegNum32(15, 0, 7, 10, 2), MISCREG_DCCSW },
324 { MiscRegNum32(15, 0, 7, 10, 4), MISCREG_CP15DSB },
325 { MiscRegNum32(15, 0, 7, 10, 5), MISCREG_CP15DMB },
326 { MiscRegNum32(15, 0, 7, 11, 1), MISCREG_DCCMVAU },
327 { MiscRegNum32(15, 0, 7, 13, 1), MISCREG_NOP },
328 { MiscRegNum32(15, 0, 7, 14, 1), MISCREG_DCCIMVAC },
329 { MiscRegNum32(15, 0, 7, 14, 2), MISCREG_DCCISW },
330 { MiscRegNum32(15, 0, 8, 3, 0), MISCREG_TLBIALLIS },
331 { MiscRegNum32(15, 0, 8, 3, 1), MISCREG_TLBIMVAIS },
332 { MiscRegNum32(15, 0, 8, 3, 2), MISCREG_TLBIASIDIS },
333 { MiscRegNum32(15, 0, 8, 3, 3), MISCREG_TLBIMVAAIS },
334 { MiscRegNum32(15, 0, 8, 3, 5), MISCREG_TLBIMVALIS },
335 { MiscRegNum32(15, 0, 8, 3, 7), MISCREG_TLBIMVAALIS },
336 { MiscRegNum32(15, 0, 8, 5, 0), MISCREG_ITLBIALL },
337 { MiscRegNum32(15, 0, 8, 5, 1), MISCREG_ITLBIMVA },
338 { MiscRegNum32(15, 0, 8, 5, 2), MISCREG_ITLBIASID },
339 { MiscRegNum32(15, 0, 8, 6, 0), MISCREG_DTLBIALL },
340 { MiscRegNum32(15, 0, 8, 6, 1), MISCREG_DTLBIMVA },
341 { MiscRegNum32(15, 0, 8, 6, 2), MISCREG_DTLBIASID },
342 { MiscRegNum32(15, 0, 8, 7, 0), MISCREG_TLBIALL },
343 { MiscRegNum32(15, 0, 8, 7, 1), MISCREG_TLBIMVA },
344 { MiscRegNum32(15, 0, 8, 7, 2), MISCREG_TLBIASID },
345 { MiscRegNum32(15, 0, 8, 7, 3), MISCREG_TLBIMVAA },
346 { MiscRegNum32(15, 0, 8, 7, 5), MISCREG_TLBIMVAL },
347 { MiscRegNum32(15, 0, 8, 7, 7), MISCREG_TLBIMVAAL },
348 { MiscRegNum32(15, 0, 9, 12, 0), MISCREG_PMCR },
349 { MiscRegNum32(15, 0, 9, 12, 1), MISCREG_PMCNTENSET },
350 { MiscRegNum32(15, 0, 9, 12, 2), MISCREG_PMCNTENCLR },
351 { MiscRegNum32(15, 0, 9, 12, 3), MISCREG_PMOVSR },
352 { MiscRegNum32(15, 0, 9, 12, 4), MISCREG_PMSWINC },
353 { MiscRegNum32(15, 0, 9, 12, 5), MISCREG_PMSELR },
354 { MiscRegNum32(15, 0, 9, 12, 6), MISCREG_PMCEID0 },
355 { MiscRegNum32(15, 0, 9, 12, 7), MISCREG_PMCEID1 },
356 { MiscRegNum32(15, 0, 9, 13, 0), MISCREG_PMCCNTR },
357 { MiscRegNum32(15, 0, 9, 13, 1), MISCREG_PMXEVTYPER_PMCCFILTR },
358 { MiscRegNum32(15, 0, 9, 13, 2), MISCREG_PMXEVCNTR },
359 { MiscRegNum32(15, 0, 9, 14, 0), MISCREG_PMUSERENR },
360 { MiscRegNum32(15, 0, 9, 14, 1), MISCREG_PMINTENSET },
361 { MiscRegNum32(15, 0, 9, 14, 2), MISCREG_PMINTENCLR },
362 { MiscRegNum32(15, 0, 9, 14, 3), MISCREG_PMOVSSET },
363 { MiscRegNum32(15, 0, 10, 2, 0), MISCREG_PRRR_MAIR0 },
364 { MiscRegNum32(15, 0, 10, 2, 1), MISCREG_NMRR_MAIR1 },
365 { MiscRegNum32(15, 0, 10, 3, 0), MISCREG_AMAIR0 },
366 { MiscRegNum32(15, 0, 10, 3, 1), MISCREG_AMAIR1 },
367 { MiscRegNum32(15, 0, 12, 0, 0), MISCREG_VBAR },
368 { MiscRegNum32(15, 0, 12, 0, 1), MISCREG_MVBAR },
369 { MiscRegNum32(15, 0, 12, 1, 0), MISCREG_ISR },
370 { MiscRegNum32(15, 0, 12, 8, 0), MISCREG_ICC_IAR0 },
371 { MiscRegNum32(15, 0, 12, 8, 1), MISCREG_ICC_EOIR0 },
372 { MiscRegNum32(15, 0, 12, 8, 2), MISCREG_ICC_HPPIR0 },
373 { MiscRegNum32(15, 0, 12, 8, 3), MISCREG_ICC_BPR0 },
374 { MiscRegNum32(15, 0, 12, 8, 4), MISCREG_ICC_AP0R0 },
375 { MiscRegNum32(15, 0, 12, 8, 5), MISCREG_ICC_AP0R1 },
376 { MiscRegNum32(15, 0, 12, 8, 6), MISCREG_ICC_AP0R2 },
377 { MiscRegNum32(15, 0, 12, 8, 7), MISCREG_ICC_AP0R3 },
378 { MiscRegNum32(15, 0, 12, 9, 0), MISCREG_ICC_AP1R0 },
379 { MiscRegNum32(15, 0, 12, 9, 1), MISCREG_ICC_AP1R1 },
380 { MiscRegNum32(15, 0, 12, 9, 2), MISCREG_ICC_AP1R2 },
381 { MiscRegNum32(15, 0, 12, 9, 3), MISCREG_ICC_AP1R3 },
382 { MiscRegNum32(15, 0, 12, 11, 1), MISCREG_ICC_DIR },
383 { MiscRegNum32(15, 0, 12, 11, 3), MISCREG_ICC_RPR },
384 { MiscRegNum32(15, 0, 12, 12, 0), MISCREG_ICC_IAR1 },
385 { MiscRegNum32(15, 0, 12, 12, 1), MISCREG_ICC_EOIR1 },
386 { MiscRegNum32(15, 0, 12, 12, 2), MISCREG_ICC_HPPIR1 },
387 { MiscRegNum32(15, 0, 12, 12, 3), MISCREG_ICC_BPR1 },
388 { MiscRegNum32(15, 0, 12, 12, 4), MISCREG_ICC_CTLR },
389 { MiscRegNum32(15, 0, 12, 12, 5), MISCREG_ICC_SRE },
390 { MiscRegNum32(15, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0 },
391 { MiscRegNum32(15, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1 },
392 { MiscRegNum32(15, 0, 13, 0, 0), MISCREG_FCSEIDR },
393 { MiscRegNum32(15, 0, 13, 0, 1), MISCREG_CONTEXTIDR },
394 { MiscRegNum32(15, 0, 13, 0, 2), MISCREG_TPIDRURW },
395 { MiscRegNum32(15, 0, 13, 0, 3), MISCREG_TPIDRURO },
396 { MiscRegNum32(15, 0, 13, 0, 4), MISCREG_TPIDRPRW },
397 { MiscRegNum32(15, 0, 14, 0, 0), MISCREG_CNTFRQ },
398 { MiscRegNum32(15, 0, 14, 1, 0), MISCREG_CNTKCTL },
399 { MiscRegNum32(15, 0, 14, 2, 0), MISCREG_CNTP_TVAL },
400 { MiscRegNum32(15, 0, 14, 2, 1), MISCREG_CNTP_CTL },
401 { MiscRegNum32(15, 0, 14, 3, 0), MISCREG_CNTV_TVAL },
402 { MiscRegNum32(15, 0, 14, 3, 1), MISCREG_CNTV_CTL },
403 { MiscRegNum32(15, 1, 0, 0, 0), MISCREG_CCSIDR },
404 { MiscRegNum32(15, 1, 0, 0, 1), MISCREG_CLIDR },
405 { MiscRegNum32(15, 1, 0, 0, 7), MISCREG_AIDR },
406 { MiscRegNum32(15, 2, 0, 0, 0), MISCREG_CSSELR },
407 { MiscRegNum32(15, 4, 0, 0, 0), MISCREG_VPIDR },
408 { MiscRegNum32(15, 4, 0, 0, 5), MISCREG_VMPIDR },
409 { MiscRegNum32(15, 4, 1, 0, 0), MISCREG_HSCTLR },
410 { MiscRegNum32(15, 4, 1, 0, 1), MISCREG_HACTLR },
411 { MiscRegNum32(15, 4, 1, 1, 0), MISCREG_HCR },
412 { MiscRegNum32(15, 4, 1, 1, 1), MISCREG_HDCR },
413 { MiscRegNum32(15, 4, 1, 1, 2), MISCREG_HCPTR },
414 { MiscRegNum32(15, 4, 1, 1, 3), MISCREG_HSTR },
415 { MiscRegNum32(15, 4, 1, 1, 4), MISCREG_HCR2 },
416 { MiscRegNum32(15, 4, 1, 1, 7), MISCREG_HACR },
417 { MiscRegNum32(15, 4, 2, 0, 2), MISCREG_HTCR },
418 { MiscRegNum32(15, 4, 2, 1, 2), MISCREG_VTCR },
419 { MiscRegNum32(15, 4, 5, 1, 0), MISCREG_HADFSR },
420 { MiscRegNum32(15, 4, 5, 1, 1), MISCREG_HAIFSR },
421 { MiscRegNum32(15, 4, 5, 2, 0), MISCREG_HSR },
422 { MiscRegNum32(15, 4, 6, 0, 0), MISCREG_HDFAR },
423 { MiscRegNum32(15, 4, 6, 0, 2), MISCREG_HIFAR },
424 { MiscRegNum32(15, 4, 6, 0, 4), MISCREG_HPFAR },
425 { MiscRegNum32(15, 4, 7, 8, 0), MISCREG_ATS1HR },
426 { MiscRegNum32(15, 4, 7, 8, 1), MISCREG_ATS1HW },
427 { MiscRegNum32(15, 4, 8, 0, 1), MISCREG_TLBIIPAS2IS },
428 { MiscRegNum32(15, 4, 8, 0, 5), MISCREG_TLBIIPAS2LIS },
429 { MiscRegNum32(15, 4, 8, 3, 0), MISCREG_TLBIALLHIS },
430 { MiscRegNum32(15, 4, 8, 3, 1), MISCREG_TLBIMVAHIS },
431 { MiscRegNum32(15, 4, 8, 3, 4), MISCREG_TLBIALLNSNHIS },
432 { MiscRegNum32(15, 4, 8, 3, 5), MISCREG_TLBIMVALHIS },
433 { MiscRegNum32(15, 4, 8, 4, 1), MISCREG_TLBIIPAS2 },
434 { MiscRegNum32(15, 4, 8, 4, 5), MISCREG_TLBIIPAS2L },
435 { MiscRegNum32(15, 4, 8, 7, 0), MISCREG_TLBIALLH },
436 { MiscRegNum32(15, 4, 8, 7, 1), MISCREG_TLBIMVAH },
437 { MiscRegNum32(15, 4, 8, 7, 4), MISCREG_TLBIALLNSNH },
438 { MiscRegNum32(15, 4, 8, 7, 5), MISCREG_TLBIMVALH },
439 { MiscRegNum32(15, 4, 10, 2, 0), MISCREG_HMAIR0 },
440 { MiscRegNum32(15, 4, 10, 2, 1), MISCREG_HMAIR1 },
441 { MiscRegNum32(15, 4, 10, 3, 0), MISCREG_HAMAIR0 },
442 { MiscRegNum32(15, 4, 10, 3, 1), MISCREG_HAMAIR1 },
443 { MiscRegNum32(15, 4, 12, 0, 0), MISCREG_HVBAR },
444 { MiscRegNum32(15, 4, 12, 8, 0), MISCREG_ICH_AP0R0 },
445 { MiscRegNum32(15, 4, 12, 8, 1), MISCREG_ICH_AP0R1 },
446 { MiscRegNum32(15, 4, 12, 8, 2), MISCREG_ICH_AP0R2 },
447 { MiscRegNum32(15, 4, 12, 8, 3), MISCREG_ICH_AP0R3 },
448 { MiscRegNum32(15, 4, 12, 9, 0), MISCREG_ICH_AP1R0 },
449 { MiscRegNum32(15, 4, 12, 9, 1), MISCREG_ICH_AP1R1 },
450 { MiscRegNum32(15, 4, 12, 9, 2), MISCREG_ICH_AP1R2 },
451 { MiscRegNum32(15, 4, 12, 9, 3), MISCREG_ICH_AP1R3 },
452 { MiscRegNum32(15, 4, 12, 9, 5), MISCREG_ICC_HSRE },
453 { MiscRegNum32(15, 4, 12, 11, 0), MISCREG_ICH_HCR },
454 { MiscRegNum32(15, 4, 12, 11, 1), MISCREG_ICH_VTR },
455 { MiscRegNum32(15, 4, 12, 11, 2), MISCREG_ICH_MISR },
456 { MiscRegNum32(15, 4, 12, 11, 3), MISCREG_ICH_EISR },
457 { MiscRegNum32(15, 4, 12, 11, 5), MISCREG_ICH_ELRSR },
458 { MiscRegNum32(15, 4, 12, 11, 7), MISCREG_ICH_VMCR },
459 { MiscRegNum32(15, 4, 12, 12, 0), MISCREG_ICH_LR0 },
460 { MiscRegNum32(15, 4, 12, 12, 1), MISCREG_ICH_LR1 },
461 { MiscRegNum32(15, 4, 12, 12, 2), MISCREG_ICH_LR2 },
462 { MiscRegNum32(15, 4, 12, 12, 3), MISCREG_ICH_LR3 },
463 { MiscRegNum32(15, 4, 12, 12, 4), MISCREG_ICH_LR4 },
464 { MiscRegNum32(15, 4, 12, 12, 5), MISCREG_ICH_LR5 },
465 { MiscRegNum32(15, 4, 12, 12, 6), MISCREG_ICH_LR6 },
466 { MiscRegNum32(15, 4, 12, 12, 7), MISCREG_ICH_LR7 },
467 { MiscRegNum32(15, 4, 12, 13, 0), MISCREG_ICH_LR8 },
468 { MiscRegNum32(15, 4, 12, 13, 1), MISCREG_ICH_LR9 },
469 { MiscRegNum32(15, 4, 12, 13, 2), MISCREG_ICH_LR10 },
470 { MiscRegNum32(15, 4, 12, 13, 3), MISCREG_ICH_LR11 },
471 { MiscRegNum32(15, 4, 12, 13, 4), MISCREG_ICH_LR12 },
472 { MiscRegNum32(15, 4, 12, 13, 5), MISCREG_ICH_LR13 },
473 { MiscRegNum32(15, 4, 12, 13, 6), MISCREG_ICH_LR14 },
474 { MiscRegNum32(15, 4, 12, 13, 7), MISCREG_ICH_LR15 },
475 { MiscRegNum32(15, 4, 12, 14, 0), MISCREG_ICH_LRC0 },
476 { MiscRegNum32(15, 4, 12, 14, 1), MISCREG_ICH_LRC1 },
477 { MiscRegNum32(15, 4, 12, 14, 2), MISCREG_ICH_LRC2 },
478 { MiscRegNum32(15, 4, 12, 14, 3), MISCREG_ICH_LRC3 },
479 { MiscRegNum32(15, 4, 12, 14, 4), MISCREG_ICH_LRC4 },
480 { MiscRegNum32(15, 4, 12, 14, 5), MISCREG_ICH_LRC5 },
481 { MiscRegNum32(15, 4, 12, 14, 6), MISCREG_ICH_LRC6 },
482 { MiscRegNum32(15, 4, 12, 14, 7), MISCREG_ICH_LRC7 },
483 { MiscRegNum32(15, 4, 12, 15, 0), MISCREG_ICH_LRC8 },
484 { MiscRegNum32(15, 4, 12, 15, 1), MISCREG_ICH_LRC9 },
485 { MiscRegNum32(15, 4, 12, 15, 2), MISCREG_ICH_LRC10 },
486 { MiscRegNum32(15, 4, 12, 15, 3), MISCREG_ICH_LRC11 },
487 { MiscRegNum32(15, 4, 12, 15, 4), MISCREG_ICH_LRC12 },
488 { MiscRegNum32(15, 4, 12, 15, 5), MISCREG_ICH_LRC13 },
489 { MiscRegNum32(15, 4, 12, 15, 6), MISCREG_ICH_LRC14 },
490 { MiscRegNum32(15, 4, 12, 15, 7), MISCREG_ICH_LRC15 },
491 { MiscRegNum32(15, 4, 13, 0, 2), MISCREG_HTPIDR },
492 { MiscRegNum32(15, 4, 14, 1, 0), MISCREG_CNTHCTL },
493 { MiscRegNum32(15, 4, 14, 2, 0), MISCREG_CNTHP_TVAL },
494 { MiscRegNum32(15, 4, 14, 2, 1), MISCREG_CNTHP_CTL },
495 { MiscRegNum32(15, 6, 12, 12, 4), MISCREG_ICC_MCTLR },
496 { MiscRegNum32(15, 6, 12, 12, 5), MISCREG_ICC_MSRE },
497 { MiscRegNum32(15, 6, 12, 12, 7), MISCREG_ICC_MGRPEN1 },
498 // MCRR/MRRC regs
499 { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 },
500 { MiscRegNum32(15, 0, 7), MISCREG_PAR },
501 { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R },
502 { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT },
503 { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },
504 { MiscRegNum32(15, 1, 2), MISCREG_TTBR1 },
505 { MiscRegNum32(15, 1, 12), MISCREG_ICC_ASGI1R },
506 { MiscRegNum32(15, 1, 14), MISCREG_CNTVCT },
507 { MiscRegNum32(15, 1, 15), MISCREG_L2MERRSR },
508 { MiscRegNum32(15, 2, 12), MISCREG_ICC_SGI0R },
509 { MiscRegNum32(15, 2, 14), MISCREG_CNTP_CVAL },
510 { MiscRegNum32(15, 3, 14), MISCREG_CNTV_CVAL },
511 { MiscRegNum32(15, 4, 2), MISCREG_HTTBR },
512 { MiscRegNum32(15, 4, 14), MISCREG_CNTVOFF },
513 { MiscRegNum32(15, 6, 2), MISCREG_VTTBR },
514 { MiscRegNum32(15, 6, 14), MISCREG_CNTHP_CVAL },
515};
516
517}
518
519MiscRegIndex
520decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
521{
522 MiscRegNum32 cop_reg(14, opc1, crn, crm, opc2);
523 auto it = miscRegNum32ToIdx.find(cop_reg);
524 if (it != miscRegNum32ToIdx.end()) {
525 return it->second;
526 } else {
527 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
528 crn, opc1, crm, opc2);
529 return MISCREG_UNKNOWN;
530 }
531}
532
533MiscRegIndex
534decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
535{
536 MiscRegNum32 cop_reg(15, opc1, crn, crm, opc2);
537 auto it = miscRegNum32ToIdx.find(cop_reg);
538 if (it != miscRegNum32ToIdx.end()) {
539 return it->second;
540 } else {
541 if ((crn == 15) ||
542 (crn == 9 && (crm <= 2 || crm >= 5)) ||
543 (crn == 10 && opc1 == 0 && crm <= 1) ||
544 (crn == 11 && opc1 <= 7 && (crm <= 8 || crm ==15))) {
545 return MISCREG_IMPDEF_UNIMPL;
546 } else {
547 return MISCREG_UNKNOWN;
548 }
549 }
550}
551
552MiscRegIndex
553decodeCP15Reg64(unsigned crm, unsigned opc1)
554{
555 MiscRegNum32 cop_reg(15, opc1, crm);
556 auto it = miscRegNum32ToIdx.find(cop_reg);
557 if (it != miscRegNum32ToIdx.end()) {
558 return it->second;
559 } else {
560 return MISCREG_UNKNOWN;
561 }
562}
563
564std::tuple<bool, bool>
565canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
566{
567 bool secure = !scr.ns;
568 bool can_read = false;
569 bool undefined = false;
570 auto& miscreg_info = lookUpMiscReg[reg].info;
571
572 switch (cpsr.mode) {
573 case MODE_USER:
574 can_read = secure ? miscreg_info[MISCREG_USR_S_RD] :
575 miscreg_info[MISCREG_USR_NS_RD];
576 break;
577 case MODE_FIQ:
578 case MODE_IRQ:
579 case MODE_SVC:
580 case MODE_ABORT:
581 case MODE_UNDEFINED:
582 case MODE_SYSTEM:
583 can_read = secure ? miscreg_info[MISCREG_PRI_S_RD] :
584 miscreg_info[MISCREG_PRI_NS_RD];
585 break;
586 case MODE_MON:
587 can_read = secure ? miscreg_info[MISCREG_MON_NS0_RD] :
588 miscreg_info[MISCREG_MON_NS1_RD];
589 break;
590 case MODE_HYP:
591 can_read = miscreg_info[MISCREG_HYP_NS_RD];
592 break;
593 default:
594 undefined = true;
595 }
596
597 switch (reg) {
598 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
599 if (!undefined)
600 undefined = AArch32isUndefinedGenericTimer(reg, tc);
601 break;
602 default:
603 break;
604 }
605
606 // can't do permissions checkes on the root of a banked pair of regs
607 assert(!miscreg_info[MISCREG_BANKED]);
608 return std::make_tuple(can_read, undefined);
609}
610
611std::tuple<bool, bool>
612canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
613{
614 bool secure = !scr.ns;
615 bool can_write = false;
616 bool undefined = false;
617 const auto& miscreg_info = lookUpMiscReg[reg].info;
618
619 switch (cpsr.mode) {
620 case MODE_USER:
621 can_write = secure ? miscreg_info[MISCREG_USR_S_WR] :
622 miscreg_info[MISCREG_USR_NS_WR];
623 break;
624 case MODE_FIQ:
625 case MODE_IRQ:
626 case MODE_SVC:
627 case MODE_ABORT:
628 case MODE_UNDEFINED:
629 case MODE_SYSTEM:
630 can_write = secure ? miscreg_info[MISCREG_PRI_S_WR] :
631 miscreg_info[MISCREG_PRI_NS_WR];
632 break;
633 case MODE_MON:
634 can_write = secure ? miscreg_info[MISCREG_MON_NS0_WR] :
635 miscreg_info[MISCREG_MON_NS1_WR];
636 break;
637 case MODE_HYP:
638 can_write = miscreg_info[MISCREG_HYP_NS_WR];
639 break;
640 default:
641 undefined = true;
642 }
643
644 switch (reg) {
645 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
646 if (!undefined)
647 undefined = AArch32isUndefinedGenericTimer(reg, tc);
648 break;
649 default:
650 break;
651 }
652
653 // can't do permissions checkes on the root of a banked pair of regs
654 assert(!miscreg_info[MISCREG_BANKED]);
655 return std::make_tuple(can_write, undefined);
656}
657
658bool
659AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
660{
661 if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
662 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
663 bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
664 if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
665 return true;
666 }
667 return false;
668}
669
670int
671snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
672{
673 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
674 return snsBankedIndex(reg, tc, scr.ns);
675}
676
677int
678snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
679{
680 int reg_as_int = static_cast<int>(reg);
681 if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
682 reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
683 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
684 }
685 return reg_as_int;
686}
687
688int
689snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
690{
691 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
692 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
693 return isa->snsBankedIndex64(reg, scr.ns);
694}
695
704int unflattenResultMiscReg[NUM_MISCREGS];
705
706void
707preUnflattenMiscReg()
708{
709 int reg = -1;
710 for (int i = 0 ; i < NUM_MISCREGS; i++){
711 if (lookUpMiscReg[i].info[MISCREG_BANKED])
712 reg = i;
713 if (lookUpMiscReg[i].info[MISCREG_BANKED_CHILD])
714 unflattenResultMiscReg[i] = reg;
715 else
716 unflattenResultMiscReg[i] = i;
717 // if this assert fails, no parent was found, and something is broken
718 assert(unflattenResultMiscReg[i] > -1);
719 }
720}
721
722int
723unflattenMiscReg(int reg)
724{
725 return unflattenResultMiscReg[reg];
726}
727
728Fault
729checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr,
730 ThreadContext *tc, const MiscRegOp64 &inst)
731{
732 return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
733}
734
735std::vector<struct MiscRegLUTEntry> lookUpMiscReg(NUM_MISCREGS);
736
737namespace {
738
739// The map is translating a MiscRegIndex into AArch64 system register
740// numbers (op0, op1, crn, crm, op2)
741std::unordered_map<MiscRegIndex, MiscRegNum64> idxToMiscRegNum;
742
743// The map is translating AArch64 system register numbers
744// (op0, op1, crn, crm, op2) into a MiscRegIndex
745std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
746 { MiscRegNum64(1, 0, 7, 1, 0), MISCREG_IC_IALLUIS },
747 { MiscRegNum64(1, 0, 7, 5, 0), MISCREG_IC_IALLU },
748 { MiscRegNum64(1, 0, 7, 6, 1), MISCREG_DC_IVAC_Xt },
749 { MiscRegNum64(1, 0, 7, 6, 2), MISCREG_DC_ISW_Xt },
750 { MiscRegNum64(1, 0, 7, 8, 0), MISCREG_AT_S1E1R_Xt },
751 { MiscRegNum64(1, 0, 7, 8, 1), MISCREG_AT_S1E1W_Xt },
752 { MiscRegNum64(1, 0, 7, 8, 2), MISCREG_AT_S1E0R_Xt },
753 { MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt },
754 { MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
755 { MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
756 { MiscRegNum64(1, 0, 8, 1, 0), MISCREG_TLBI_VMALLE1OS },
757 { MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS_Xt },
758 { MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS_Xt },
759 { MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS_Xt },
760 { MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS_Xt },
761 { MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS_Xt },
762 { MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
763 { MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
764 { MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
765 { MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
766 { MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
767 { MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
768 { MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
769 { MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
770 { MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
771 { MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
772 { MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
773 { MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
774 { MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
775 { MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
776 { MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
777 { MiscRegNum64(1, 3, 7, 11, 1), MISCREG_DC_CVAU_Xt },
778 { MiscRegNum64(1, 3, 7, 14, 1), MISCREG_DC_CIVAC_Xt },
779 { MiscRegNum64(1, 4, 7, 8, 0), MISCREG_AT_S1E2R_Xt },
780 { MiscRegNum64(1, 4, 7, 8, 1), MISCREG_AT_S1E2W_Xt },
781 { MiscRegNum64(1, 4, 7, 8, 4), MISCREG_AT_S12E1R_Xt },
782 { MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
783 { MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
784 { MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
785 { MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
786 { MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
787 { MiscRegNum64(1, 4, 8, 1, 0), MISCREG_TLBI_ALLE2OS },
788 { MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS_Xt },
789 { MiscRegNum64(1, 4, 8, 1, 4), MISCREG_TLBI_ALLE1OS },
790 { MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS_Xt },
791 { MiscRegNum64(1, 4, 8, 1, 6), MISCREG_TLBI_VMALLS12E1OS },
792 { MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
793 { MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
794 { MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
795 { MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
796 { MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
797 { MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS_Xt },
798 { MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
799 { MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS_Xt },
800 { MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
801 { MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
802 { MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
803 { MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
804 { MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
805 { MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
806 { MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
807 { MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
808 { MiscRegNum64(1, 6, 8, 1, 0), MISCREG_TLBI_ALLE3OS },
809 { MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS_Xt },
810 { MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS_Xt },
811 { MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
812 { MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
813 { MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
814 { MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
815 { MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
816 { MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
817 { MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
818 { MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
819 { MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
820 { MiscRegNum64(2, 0, 0, 0, 6), MISCREG_DBGWVR0_EL1 },
821 { MiscRegNum64(2, 0, 0, 0, 7), MISCREG_DBGWCR0_EL1 },
822 { MiscRegNum64(2, 0, 0, 1, 4), MISCREG_DBGBVR1_EL1 },
823 { MiscRegNum64(2, 0, 0, 1, 5), MISCREG_DBGBCR1_EL1 },
824 { MiscRegNum64(2, 0, 0, 1, 6), MISCREG_DBGWVR1_EL1 },
825 { MiscRegNum64(2, 0, 0, 1, 7), MISCREG_DBGWCR1_EL1 },
826 { MiscRegNum64(2, 0, 0, 2, 0), MISCREG_MDCCINT_EL1 },
827 { MiscRegNum64(2, 0, 0, 2, 2), MISCREG_MDSCR_EL1 },
828 { MiscRegNum64(2, 0, 0, 2, 4), MISCREG_DBGBVR2_EL1 },
829 { MiscRegNum64(2, 0, 0, 2, 5), MISCREG_DBGBCR2_EL1 },
830 { MiscRegNum64(2, 0, 0, 2, 6), MISCREG_DBGWVR2_EL1 },
831 { MiscRegNum64(2, 0, 0, 2, 7), MISCREG_DBGWCR2_EL1 },
832 { MiscRegNum64(2, 0, 0, 3, 2), MISCREG_OSDTRTX_EL1 },
833 { MiscRegNum64(2, 0, 0, 3, 4), MISCREG_DBGBVR3_EL1 },
834 { MiscRegNum64(2, 0, 0, 3, 5), MISCREG_DBGBCR3_EL1 },
835 { MiscRegNum64(2, 0, 0, 3, 6), MISCREG_DBGWVR3_EL1 },
836 { MiscRegNum64(2, 0, 0, 3, 7), MISCREG_DBGWCR3_EL1 },
837 { MiscRegNum64(2, 0, 0, 4, 4), MISCREG_DBGBVR4_EL1 },
838 { MiscRegNum64(2, 0, 0, 4, 5), MISCREG_DBGBCR4_EL1 },
839 { MiscRegNum64(2, 0, 0, 4, 6), MISCREG_DBGWVR4_EL1 },
840 { MiscRegNum64(2, 0, 0, 4, 7), MISCREG_DBGWCR4_EL1 },
841 { MiscRegNum64(2, 0, 0, 5, 4), MISCREG_DBGBVR5_EL1 },
842 { MiscRegNum64(2, 0, 0, 5, 5), MISCREG_DBGBCR5_EL1 },
843 { MiscRegNum64(2, 0, 0, 5, 6), MISCREG_DBGWVR5_EL1 },
844 { MiscRegNum64(2, 0, 0, 5, 7), MISCREG_DBGWCR5_EL1 },
845 { MiscRegNum64(2, 0, 0, 6, 2), MISCREG_OSECCR_EL1 },
846 { MiscRegNum64(2, 0, 0, 6, 4), MISCREG_DBGBVR6_EL1 },
847 { MiscRegNum64(2, 0, 0, 6, 5), MISCREG_DBGBCR6_EL1 },
848 { MiscRegNum64(2, 0, 0, 6, 6), MISCREG_DBGWVR6_EL1 },
849 { MiscRegNum64(2, 0, 0, 6, 7), MISCREG_DBGWCR6_EL1 },
850 { MiscRegNum64(2, 0, 0, 7, 4), MISCREG_DBGBVR7_EL1 },
851 { MiscRegNum64(2, 0, 0, 7, 5), MISCREG_DBGBCR7_EL1 },
852 { MiscRegNum64(2, 0, 0, 7, 6), MISCREG_DBGWVR7_EL1 },
853 { MiscRegNum64(2, 0, 0, 7, 7), MISCREG_DBGWCR7_EL1 },
854 { MiscRegNum64(2, 0, 0, 8, 4), MISCREG_DBGBVR8_EL1 },
855 { MiscRegNum64(2, 0, 0, 8, 5), MISCREG_DBGBCR8_EL1 },
856 { MiscRegNum64(2, 0, 0, 8, 6), MISCREG_DBGWVR8_EL1 },
857 { MiscRegNum64(2, 0, 0, 8, 7), MISCREG_DBGWCR8_EL1 },
858 { MiscRegNum64(2, 0, 0, 9, 4), MISCREG_DBGBVR9_EL1 },
859 { MiscRegNum64(2, 0, 0, 9, 5), MISCREG_DBGBCR9_EL1 },
860 { MiscRegNum64(2, 0, 0, 9, 6), MISCREG_DBGWVR9_EL1 },
861 { MiscRegNum64(2, 0, 0, 9, 7), MISCREG_DBGWCR9_EL1 },
862 { MiscRegNum64(2, 0, 0, 10, 4), MISCREG_DBGBVR10_EL1 },
863 { MiscRegNum64(2, 0, 0, 10, 5), MISCREG_DBGBCR10_EL1 },
864 { MiscRegNum64(2, 0, 0, 10, 6), MISCREG_DBGWVR10_EL1 },
865 { MiscRegNum64(2, 0, 0, 10, 7), MISCREG_DBGWCR10_EL1 },
866 { MiscRegNum64(2, 0, 0, 11, 4), MISCREG_DBGBVR11_EL1 },
867 { MiscRegNum64(2, 0, 0, 11, 5), MISCREG_DBGBCR11_EL1 },
868 { MiscRegNum64(2, 0, 0, 11, 6), MISCREG_DBGWVR11_EL1 },
869 { MiscRegNum64(2, 0, 0, 11, 7), MISCREG_DBGWCR11_EL1 },
870 { MiscRegNum64(2, 0, 0, 12, 4), MISCREG_DBGBVR12_EL1 },
871 { MiscRegNum64(2, 0, 0, 12, 5), MISCREG_DBGBCR12_EL1 },
872 { MiscRegNum64(2, 0, 0, 12, 6), MISCREG_DBGWVR12_EL1 },
873 { MiscRegNum64(2, 0, 0, 12, 7), MISCREG_DBGWCR12_EL1 },
874 { MiscRegNum64(2, 0, 0, 13, 4), MISCREG_DBGBVR13_EL1 },
875 { MiscRegNum64(2, 0, 0, 13, 5), MISCREG_DBGBCR13_EL1 },
876 { MiscRegNum64(2, 0, 0, 13, 6), MISCREG_DBGWVR13_EL1 },
877 { MiscRegNum64(2, 0, 0, 13, 7), MISCREG_DBGWCR13_EL1 },
878 { MiscRegNum64(2, 0, 0, 14, 4), MISCREG_DBGBVR14_EL1 },
879 { MiscRegNum64(2, 0, 0, 14, 5), MISCREG_DBGBCR14_EL1 },
880 { MiscRegNum64(2, 0, 0, 14, 6), MISCREG_DBGWVR14_EL1 },
881 { MiscRegNum64(2, 0, 0, 14, 7), MISCREG_DBGWCR14_EL1 },
882 { MiscRegNum64(2, 0, 0, 15, 4), MISCREG_DBGBVR15_EL1 },
883 { MiscRegNum64(2, 0, 0, 15, 5), MISCREG_DBGBCR15_EL1 },
884 { MiscRegNum64(2, 0, 0, 15, 6), MISCREG_DBGWVR15_EL1 },
885 { MiscRegNum64(2, 0, 0, 15, 7), MISCREG_DBGWCR15_EL1 },
886 { MiscRegNum64(2, 0, 1, 0, 0), MISCREG_MDRAR_EL1 },
887 { MiscRegNum64(2, 0, 1, 0, 4), MISCREG_OSLAR_EL1 },
888 { MiscRegNum64(2, 0, 1, 1, 4), MISCREG_OSLSR_EL1 },
889 { MiscRegNum64(2, 0, 1, 3, 4), MISCREG_OSDLR_EL1 },
890 { MiscRegNum64(2, 0, 1, 4, 4), MISCREG_DBGPRCR_EL1 },
891 { MiscRegNum64(2, 0, 7, 8, 6), MISCREG_DBGCLAIMSET_EL1 },
892 { MiscRegNum64(2, 0, 7, 9, 6), MISCREG_DBGCLAIMCLR_EL1 },
893 { MiscRegNum64(2, 0, 7, 14, 6), MISCREG_DBGAUTHSTATUS_EL1 },
894 { MiscRegNum64(2, 2, 0, 0, 0), MISCREG_TEECR32_EL1 },
895 { MiscRegNum64(2, 2, 1, 0, 0), MISCREG_TEEHBR32_EL1 },
896 { MiscRegNum64(2, 3, 0, 1, 0), MISCREG_MDCCSR_EL0 },
897 { MiscRegNum64(2, 3, 0, 4, 0), MISCREG_MDDTR_EL0 },
898 { MiscRegNum64(2, 3, 0, 5, 0), MISCREG_MDDTRRX_EL0 },
899 { MiscRegNum64(2, 4, 0, 7, 0), MISCREG_DBGVCR32_EL2 },
900 { MiscRegNum64(3, 0, 0, 0, 0), MISCREG_MIDR_EL1 },
901 { MiscRegNum64(3, 0, 0, 0, 5), MISCREG_MPIDR_EL1 },
902 { MiscRegNum64(3, 0, 0, 0, 6), MISCREG_REVIDR_EL1 },
903 { MiscRegNum64(3, 0, 0, 1, 0), MISCREG_ID_PFR0_EL1 },
904 { MiscRegNum64(3, 0, 0, 1, 1), MISCREG_ID_PFR1_EL1 },
905 { MiscRegNum64(3, 0, 0, 1, 2), MISCREG_ID_DFR0_EL1 },
906 { MiscRegNum64(3, 0, 0, 1, 3), MISCREG_ID_AFR0_EL1 },
907 { MiscRegNum64(3, 0, 0, 1, 4), MISCREG_ID_MMFR0_EL1 },
908 { MiscRegNum64(3, 0, 0, 1, 5), MISCREG_ID_MMFR1_EL1 },
909 { MiscRegNum64(3, 0, 0, 1, 6), MISCREG_ID_MMFR2_EL1 },
910 { MiscRegNum64(3, 0, 0, 1, 7), MISCREG_ID_MMFR3_EL1 },
911 { MiscRegNum64(3, 0, 0, 2, 0), MISCREG_ID_ISAR0_EL1 },
912 { MiscRegNum64(3, 0, 0, 2, 1), MISCREG_ID_ISAR1_EL1 },
913 { MiscRegNum64(3, 0, 0, 2, 2), MISCREG_ID_ISAR2_EL1 },
914 { MiscRegNum64(3, 0, 0, 2, 3), MISCREG_ID_ISAR3_EL1 },
915 { MiscRegNum64(3, 0, 0, 2, 4), MISCREG_ID_ISAR4_EL1 },
916 { MiscRegNum64(3, 0, 0, 2, 5), MISCREG_ID_ISAR5_EL1 },
917 { MiscRegNum64(3, 0, 0, 2, 6), MISCREG_ID_MMFR4_EL1 },
918 { MiscRegNum64(3, 0, 0, 2, 7), MISCREG_ID_ISAR6_EL1 },
919 { MiscRegNum64(3, 0, 0, 3, 0), MISCREG_MVFR0_EL1 },
920 { MiscRegNum64(3, 0, 0, 3, 1), MISCREG_MVFR1_EL1 },
921 { MiscRegNum64(3, 0, 0, 3, 2), MISCREG_MVFR2_EL1 },
922 { MiscRegNum64(3, 0, 0, 3, 3), MISCREG_RAZ },
923 { MiscRegNum64(3, 0, 0, 3, 4), MISCREG_RAZ },
924 { MiscRegNum64(3, 0, 0, 3, 5), MISCREG_RAZ },
925 { MiscRegNum64(3, 0, 0, 3, 6), MISCREG_RAZ },
926 { MiscRegNum64(3, 0, 0, 3, 7), MISCREG_RAZ },
927 { MiscRegNum64(3, 0, 0, 4, 0), MISCREG_ID_AA64PFR0_EL1 },
928 { MiscRegNum64(3, 0, 0, 4, 1), MISCREG_ID_AA64PFR1_EL1 },
929 { MiscRegNum64(3, 0, 0, 4, 2), MISCREG_RAZ },
930 { MiscRegNum64(3, 0, 0, 4, 3), MISCREG_RAZ },
931 { MiscRegNum64(3, 0, 0, 4, 4), MISCREG_ID_AA64ZFR0_EL1 },
932 { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_ID_AA64SMFR0_EL1 },
933 { MiscRegNum64(3, 0, 0, 4, 6), MISCREG_RAZ },
934 { MiscRegNum64(3, 0, 0, 4, 7), MISCREG_RAZ },
935 { MiscRegNum64(3, 0, 0, 5, 0), MISCREG_ID_AA64DFR0_EL1 },
936 { MiscRegNum64(3, 0, 0, 5, 1), MISCREG_ID_AA64DFR1_EL1 },
937 { MiscRegNum64(3, 0, 0, 5, 2), MISCREG_RAZ },
938 { MiscRegNum64(3, 0, 0, 5, 3), MISCREG_RAZ },
939 { MiscRegNum64(3, 0, 0, 5, 4), MISCREG_ID_AA64AFR0_EL1 },
940 { MiscRegNum64(3, 0, 0, 5, 5), MISCREG_ID_AA64AFR1_EL1 },
941 { MiscRegNum64(3, 0, 0, 5, 6), MISCREG_RAZ },
942 { MiscRegNum64(3, 0, 0, 5, 7), MISCREG_RAZ },
943 { MiscRegNum64(3, 0, 0, 6, 0), MISCREG_ID_AA64ISAR0_EL1 },
944 { MiscRegNum64(3, 0, 0, 6, 1), MISCREG_ID_AA64ISAR1_EL1 },
945 { MiscRegNum64(3, 0, 0, 6, 2), MISCREG_RAZ },
946 { MiscRegNum64(3, 0, 0, 6, 3), MISCREG_RAZ },
947 { MiscRegNum64(3, 0, 0, 6, 4), MISCREG_RAZ },
948 { MiscRegNum64(3, 0, 0, 6, 5), MISCREG_RAZ },
949 { MiscRegNum64(3, 0, 0, 6, 6), MISCREG_RAZ },
950 { MiscRegNum64(3, 0, 0, 6, 7), MISCREG_RAZ },
951 { MiscRegNum64(3, 0, 0, 7, 0), MISCREG_ID_AA64MMFR0_EL1 },
952 { MiscRegNum64(3, 0, 0, 7, 1), MISCREG_ID_AA64MMFR1_EL1 },
953 { MiscRegNum64(3, 0, 0, 7, 2), MISCREG_ID_AA64MMFR2_EL1 },
954 { MiscRegNum64(3, 0, 0, 7, 3), MISCREG_RAZ },
955 { MiscRegNum64(3, 0, 0, 7, 4), MISCREG_RAZ },
956 { MiscRegNum64(3, 0, 0, 7, 5), MISCREG_RAZ },
957 { MiscRegNum64(3, 0, 0, 7, 6), MISCREG_RAZ },
958 { MiscRegNum64(3, 0, 0, 7, 7), MISCREG_RAZ },
959 { MiscRegNum64(3, 0, 1, 0, 0), MISCREG_SCTLR_EL1 },
960 { MiscRegNum64(3, 0, 1, 0, 1), MISCREG_ACTLR_EL1 },
961 { MiscRegNum64(3, 0, 1, 0, 2), MISCREG_CPACR_EL1 },
962 { MiscRegNum64(3, 0, 1, 2, 0), MISCREG_ZCR_EL1 },
963 { MiscRegNum64(3, 0, 1, 2, 4), MISCREG_SMPRI_EL1 },
964 { MiscRegNum64(3, 0, 1, 2, 6), MISCREG_SMCR_EL1 },
965 { MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
966 { MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
967 { MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
968 { MiscRegNum64(3, 0, 2, 1, 0), MISCREG_APIAKeyLo_EL1 },
969 { MiscRegNum64(3, 0, 2, 1, 1), MISCREG_APIAKeyHi_EL1 },
970 { MiscRegNum64(3, 0, 2, 1, 2), MISCREG_APIBKeyLo_EL1 },
971 { MiscRegNum64(3, 0, 2, 1, 3), MISCREG_APIBKeyHi_EL1 },
972 { MiscRegNum64(3, 0, 2, 2, 0), MISCREG_APDAKeyLo_EL1 },
973 { MiscRegNum64(3, 0, 2, 2, 1), MISCREG_APDAKeyHi_EL1 },
974 { MiscRegNum64(3, 0, 2, 2, 2), MISCREG_APDBKeyLo_EL1 },
975 { MiscRegNum64(3, 0, 2, 2, 3), MISCREG_APDBKeyHi_EL1 },
976 { MiscRegNum64(3, 0, 2, 3, 0), MISCREG_APGAKeyLo_EL1 },
977 { MiscRegNum64(3, 0, 2, 3, 1), MISCREG_APGAKeyHi_EL1 },
978 { MiscRegNum64(3, 0, 4, 0, 0), MISCREG_SPSR_EL1 },
979 { MiscRegNum64(3, 0, 4, 0, 1), MISCREG_ELR_EL1 },
980 { MiscRegNum64(3, 0, 4, 1, 0), MISCREG_SP_EL0 },
981 { MiscRegNum64(3, 0, 4, 2, 0), MISCREG_SPSEL },
982 { MiscRegNum64(3, 0, 4, 2, 2), MISCREG_CURRENTEL },
983 { MiscRegNum64(3, 0, 4, 2, 3), MISCREG_PAN },
984 { MiscRegNum64(3, 0, 4, 2, 4), MISCREG_UAO },
985 { MiscRegNum64(3, 0, 4, 6, 0), MISCREG_ICC_PMR_EL1 },
986 { MiscRegNum64(3, 0, 5, 1, 0), MISCREG_AFSR0_EL1 },
987 { MiscRegNum64(3, 0, 5, 1, 1), MISCREG_AFSR1_EL1 },
988 { MiscRegNum64(3, 0, 5, 2, 0), MISCREG_ESR_EL1 },
989 { MiscRegNum64(3, 0, 5, 3, 0), MISCREG_ERRIDR_EL1 },
990 { MiscRegNum64(3, 0, 5, 3, 1), MISCREG_ERRSELR_EL1 },
991 { MiscRegNum64(3, 0, 5, 4, 0), MISCREG_ERXFR_EL1 },
992 { MiscRegNum64(3, 0, 5, 4, 1), MISCREG_ERXCTLR_EL1 },
993 { MiscRegNum64(3, 0, 5, 4, 2), MISCREG_ERXSTATUS_EL1 },
994 { MiscRegNum64(3, 0, 5, 4, 3), MISCREG_ERXADDR_EL1 },
995 { MiscRegNum64(3, 0, 5, 5, 0), MISCREG_ERXMISC0_EL1 },
996 { MiscRegNum64(3, 0, 5, 5, 1), MISCREG_ERXMISC1_EL1 },
997 { MiscRegNum64(3, 0, 6, 0, 0), MISCREG_FAR_EL1 },
998 { MiscRegNum64(3, 0, 7, 4, 0), MISCREG_PAR_EL1 },
999 { MiscRegNum64(3, 0, 9, 14, 1), MISCREG_PMINTENSET_EL1 },
1000 { MiscRegNum64(3, 0, 9, 14, 2), MISCREG_PMINTENCLR_EL1 },
1001 { MiscRegNum64(3, 0, 10, 2, 0), MISCREG_MAIR_EL1 },
1002 { MiscRegNum64(3, 0, 10, 3, 0), MISCREG_AMAIR_EL1 },
1003 { MiscRegNum64(3, 0, 10, 5, 3), MISCREG_MPAMSM_EL1 },
1004 { MiscRegNum64(3, 0, 12, 0, 0), MISCREG_VBAR_EL1 },
1005 { MiscRegNum64(3, 0, 12, 0, 1), MISCREG_RVBAR_EL1 },
1006 { MiscRegNum64(3, 0, 12, 1, 0), MISCREG_ISR_EL1 },
1007 { MiscRegNum64(3, 0, 12, 1, 1), MISCREG_DISR_EL1 },
1008 { MiscRegNum64(3, 0, 12, 8, 0), MISCREG_ICC_IAR0_EL1 },
1009 { MiscRegNum64(3, 0, 12, 8, 1), MISCREG_ICC_EOIR0_EL1 },
1010 { MiscRegNum64(3, 0, 12, 8, 2), MISCREG_ICC_HPPIR0_EL1 },
1011 { MiscRegNum64(3, 0, 12, 8, 3), MISCREG_ICC_BPR0_EL1 },
1012 { MiscRegNum64(3, 0, 12, 8, 4), MISCREG_ICC_AP0R0_EL1 },
1013 { MiscRegNum64(3, 0, 12, 8, 5), MISCREG_ICC_AP0R1_EL1 },
1014 { MiscRegNum64(3, 0, 12, 8, 6), MISCREG_ICC_AP0R2_EL1 },
1015 { MiscRegNum64(3, 0, 12, 8, 7), MISCREG_ICC_AP0R3_EL1 },
1016 { MiscRegNum64(3, 0, 12, 9, 0), MISCREG_ICC_AP1R0_EL1 },
1017 { MiscRegNum64(3, 0, 12, 9, 1), MISCREG_ICC_AP1R1_EL1 },
1018 { MiscRegNum64(3, 0, 12, 9, 2), MISCREG_ICC_AP1R2_EL1 },
1019 { MiscRegNum64(3, 0, 12, 9, 3), MISCREG_ICC_AP1R3_EL1 },
1020 { MiscRegNum64(3, 0, 12, 11, 1), MISCREG_ICC_DIR_EL1 },
1021 { MiscRegNum64(3, 0, 12, 11, 3), MISCREG_ICC_RPR_EL1 },
1022 { MiscRegNum64(3, 0, 12, 11, 5), MISCREG_ICC_SGI1R_EL1 },
1023 { MiscRegNum64(3, 0, 12, 11, 6), MISCREG_ICC_ASGI1R_EL1 },
1024 { MiscRegNum64(3, 0, 12, 11, 7), MISCREG_ICC_SGI0R_EL1 },
1025 { MiscRegNum64(3, 0, 12, 12, 0), MISCREG_ICC_IAR1_EL1 },
1026 { MiscRegNum64(3, 0, 12, 12, 1), MISCREG_ICC_EOIR1_EL1 },
1027 { MiscRegNum64(3, 0, 12, 12, 2), MISCREG_ICC_HPPIR1_EL1 },
1028 { MiscRegNum64(3, 0, 12, 12, 3), MISCREG_ICC_BPR1_EL1 },
1029 { MiscRegNum64(3, 0, 12, 12, 4), MISCREG_ICC_CTLR_EL1 },
1030 { MiscRegNum64(3, 0, 12, 12, 5), MISCREG_ICC_SRE_EL1 },
1031 { MiscRegNum64(3, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0_EL1 },
1032 { MiscRegNum64(3, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL1 },
1033 { MiscRegNum64(3, 0, 13, 0, 1), MISCREG_CONTEXTIDR_EL1 },
1034 { MiscRegNum64(3, 0, 13, 0, 4), MISCREG_TPIDR_EL1 },
1035 { MiscRegNum64(3, 0, 14, 1, 0), MISCREG_CNTKCTL_EL1 },
1036 { MiscRegNum64(3, 0, 15, 0, 0), MISCREG_IL1DATA0_EL1 },
1037 { MiscRegNum64(3, 0, 15, 0, 1), MISCREG_IL1DATA1_EL1 },
1038 { MiscRegNum64(3, 0, 15, 0, 2), MISCREG_IL1DATA2_EL1 },
1039 { MiscRegNum64(3, 0, 15, 0, 3), MISCREG_IL1DATA3_EL1 },
1040 { MiscRegNum64(3, 0, 15, 1, 0), MISCREG_DL1DATA0_EL1 },
1041 { MiscRegNum64(3, 0, 15, 1, 1), MISCREG_DL1DATA1_EL1 },
1042 { MiscRegNum64(3, 0, 15, 1, 2), MISCREG_DL1DATA2_EL1 },
1043 { MiscRegNum64(3, 0, 15, 1, 3), MISCREG_DL1DATA3_EL1 },
1044 { MiscRegNum64(3, 0, 15, 1, 4), MISCREG_DL1DATA4_EL1 },
1045 { MiscRegNum64(3, 1, 0, 0, 0), MISCREG_CCSIDR_EL1 },
1046 { MiscRegNum64(3, 1, 0, 0, 1), MISCREG_CLIDR_EL1 },
1047 { MiscRegNum64(3, 1, 0, 0, 6), MISCREG_SMIDR_EL1 },
1048 { MiscRegNum64(3, 1, 0, 0, 7), MISCREG_AIDR_EL1 },
1049 { MiscRegNum64(3, 1, 11, 0, 2), MISCREG_L2CTLR_EL1 },
1050 { MiscRegNum64(3, 1, 11, 0, 3), MISCREG_L2ECTLR_EL1 },
1051 { MiscRegNum64(3, 1, 15, 0, 0), MISCREG_L2ACTLR_EL1 },
1052 { MiscRegNum64(3, 1, 15, 2, 0), MISCREG_CPUACTLR_EL1 },
1053 { MiscRegNum64(3, 1, 15, 2, 1), MISCREG_CPUECTLR_EL1 },
1054 { MiscRegNum64(3, 1, 15, 2, 2), MISCREG_CPUMERRSR_EL1 },
1055 { MiscRegNum64(3, 1, 15, 2, 3), MISCREG_L2MERRSR_EL1 },
1056 { MiscRegNum64(3, 1, 15, 3, 0), MISCREG_CBAR_EL1 },
1057 { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
1058 { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
1059 { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
1060 { MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
1061 { MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
1062 { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
1063 { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
1064 { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
1065 { MiscRegNum64(3, 3, 4, 4, 0), MISCREG_FPCR },
1066 { MiscRegNum64(3, 3, 4, 4, 1), MISCREG_FPSR },
1067 { MiscRegNum64(3, 3, 4, 5, 0), MISCREG_DSPSR_EL0 },
1068 { MiscRegNum64(3, 3, 4, 5, 1), MISCREG_DLR_EL0 },
1069 { MiscRegNum64(3, 3, 9, 12, 0), MISCREG_PMCR_EL0 },
1070 { MiscRegNum64(3, 3, 9, 12, 1), MISCREG_PMCNTENSET_EL0 },
1071 { MiscRegNum64(3, 3, 9, 12, 2), MISCREG_PMCNTENCLR_EL0 },
1072 { MiscRegNum64(3, 3, 9, 12, 3), MISCREG_PMOVSCLR_EL0 },
1073 { MiscRegNum64(3, 3, 9, 12, 4), MISCREG_PMSWINC_EL0 },
1074 { MiscRegNum64(3, 3, 9, 12, 5), MISCREG_PMSELR_EL0 },
1075 { MiscRegNum64(3, 3, 9, 12, 6), MISCREG_PMCEID0_EL0 },
1076 { MiscRegNum64(3, 3, 9, 12, 7), MISCREG_PMCEID1_EL0 },
1077 { MiscRegNum64(3, 3, 9, 13, 0), MISCREG_PMCCNTR_EL0 },
1078 { MiscRegNum64(3, 3, 9, 13, 1), MISCREG_PMXEVTYPER_EL0 },
1079 { MiscRegNum64(3, 3, 9, 13, 2), MISCREG_PMXEVCNTR_EL0 },
1080 { MiscRegNum64(3, 3, 9, 14, 0), MISCREG_PMUSERENR_EL0 },
1081 { MiscRegNum64(3, 3, 9, 14, 3), MISCREG_PMOVSSET_EL0 },
1082 { MiscRegNum64(3, 3, 13, 0, 2), MISCREG_TPIDR_EL0 },
1083 { MiscRegNum64(3, 3, 13, 0, 3), MISCREG_TPIDRRO_EL0 },
1084 { MiscRegNum64(3, 3, 13, 0, 5), MISCREG_TPIDR2_EL0 },
1085 { MiscRegNum64(3, 3, 14, 0, 0), MISCREG_CNTFRQ_EL0 },
1086 { MiscRegNum64(3, 3, 14, 0, 1), MISCREG_CNTPCT_EL0 },
1087 { MiscRegNum64(3, 3, 14, 0, 2), MISCREG_CNTVCT_EL0 },
1088 { MiscRegNum64(3, 3, 14, 2, 0), MISCREG_CNTP_TVAL_EL0 },
1089 { MiscRegNum64(3, 3, 14, 2, 1), MISCREG_CNTP_CTL_EL0 },
1090 { MiscRegNum64(3, 3, 14, 2, 2), MISCREG_CNTP_CVAL_EL0 },
1091 { MiscRegNum64(3, 3, 14, 3, 0), MISCREG_CNTV_TVAL_EL0 },
1092 { MiscRegNum64(3, 3, 14, 3, 1), MISCREG_CNTV_CTL_EL0 },
1093 { MiscRegNum64(3, 3, 14, 3, 2), MISCREG_CNTV_CVAL_EL0 },
1094 { MiscRegNum64(3, 3, 14, 8, 0), MISCREG_PMEVCNTR0_EL0 },
1095 { MiscRegNum64(3, 3, 14, 8, 1), MISCREG_PMEVCNTR1_EL0 },
1096 { MiscRegNum64(3, 3, 14, 8, 2), MISCREG_PMEVCNTR2_EL0 },
1097 { MiscRegNum64(3, 3, 14, 8, 3), MISCREG_PMEVCNTR3_EL0 },
1098 { MiscRegNum64(3, 3, 14, 8, 4), MISCREG_PMEVCNTR4_EL0 },
1099 { MiscRegNum64(3, 3, 14, 8, 5), MISCREG_PMEVCNTR5_EL0 },
1100 { MiscRegNum64(3, 3, 14, 12, 0), MISCREG_PMEVTYPER0_EL0 },
1101 { MiscRegNum64(3, 3, 14, 12, 1), MISCREG_PMEVTYPER1_EL0 },
1102 { MiscRegNum64(3, 3, 14, 12, 2), MISCREG_PMEVTYPER2_EL0 },
1103 { MiscRegNum64(3, 3, 14, 12, 3), MISCREG_PMEVTYPER3_EL0 },
1104 { MiscRegNum64(3, 3, 14, 12, 4), MISCREG_PMEVTYPER4_EL0 },
1105 { MiscRegNum64(3, 3, 14, 12, 5), MISCREG_PMEVTYPER5_EL0 },
1106 { MiscRegNum64(3, 3, 14, 15, 7), MISCREG_PMCCFILTR_EL0 },
1107 { MiscRegNum64(3, 4, 0, 0, 0), MISCREG_VPIDR_EL2 },
1108 { MiscRegNum64(3, 4, 0, 0, 5), MISCREG_VMPIDR_EL2 },
1109 { MiscRegNum64(3, 4, 1, 0, 0), MISCREG_SCTLR_EL2 },
1110 { MiscRegNum64(3, 4, 1, 0, 1), MISCREG_ACTLR_EL2 },
1111 { MiscRegNum64(3, 4, 1, 1, 0), MISCREG_HCR_EL2 },
1112 { MiscRegNum64(3, 4, 1, 1, 1), MISCREG_MDCR_EL2 },
1113 { MiscRegNum64(3, 4, 1, 1, 2), MISCREG_CPTR_EL2 },
1114 { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
1115 { MiscRegNum64(3, 4, 1, 1, 4), MISCREG_HFGRTR_EL2 },
1116 { MiscRegNum64(3, 4, 1, 1, 5), MISCREG_HFGWTR_EL2 },
1117 { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
1118 { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
1119 { MiscRegNum64(3, 4, 1, 2, 2), MISCREG_HCRX_EL2 },
1120 { MiscRegNum64(3, 4, 1, 2, 5), MISCREG_SMPRIMAP_EL2 },
1121 { MiscRegNum64(3, 4, 1, 2, 6), MISCREG_SMCR_EL2 },
1122 { MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
1123 { MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
1124 { MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
1125 { MiscRegNum64(3, 4, 2, 1, 0), MISCREG_VTTBR_EL2 },
1126 { MiscRegNum64(3, 4, 2, 1, 2), MISCREG_VTCR_EL2 },
1127 { MiscRegNum64(3, 4, 2, 6, 0), MISCREG_VSTTBR_EL2 },
1128 { MiscRegNum64(3, 4, 2, 6, 2), MISCREG_VSTCR_EL2 },
1129 { MiscRegNum64(3, 4, 3, 0, 0), MISCREG_DACR32_EL2 },
1130 { MiscRegNum64(3, 4, 4, 0, 0), MISCREG_SPSR_EL2 },
1131 { MiscRegNum64(3, 4, 4, 0, 1), MISCREG_ELR_EL2 },
1132 { MiscRegNum64(3, 4, 4, 1, 0), MISCREG_SP_EL1 },
1133 { MiscRegNum64(3, 4, 4, 3, 0), MISCREG_SPSR_IRQ_AA64 },
1134 { MiscRegNum64(3, 4, 4, 3, 1), MISCREG_SPSR_ABT_AA64 },
1135 { MiscRegNum64(3, 4, 4, 3, 2), MISCREG_SPSR_UND_AA64 },
1136 { MiscRegNum64(3, 4, 4, 3, 3), MISCREG_SPSR_FIQ_AA64 },
1137 { MiscRegNum64(3, 4, 5, 0, 1), MISCREG_IFSR32_EL2 },
1138 { MiscRegNum64(3, 4, 5, 1, 0), MISCREG_AFSR0_EL2 },
1139 { MiscRegNum64(3, 4, 5, 1, 1), MISCREG_AFSR1_EL2 },
1140 { MiscRegNum64(3, 4, 5, 2, 0), MISCREG_ESR_EL2 },
1141 { MiscRegNum64(3, 4, 5, 2, 3), MISCREG_VSESR_EL2 },
1142 { MiscRegNum64(3, 4, 5, 3, 0), MISCREG_FPEXC32_EL2 },
1143 { MiscRegNum64(3, 4, 6, 0, 0), MISCREG_FAR_EL2 },
1144 { MiscRegNum64(3, 4, 6, 0, 4), MISCREG_HPFAR_EL2 },
1145 { MiscRegNum64(3, 4, 10, 2, 0), MISCREG_MAIR_EL2 },
1146 { MiscRegNum64(3, 4, 10, 3, 0), MISCREG_AMAIR_EL2 },
1147 { MiscRegNum64(3, 4, 12, 0, 0), MISCREG_VBAR_EL2 },
1148 { MiscRegNum64(3, 4, 12, 0, 1), MISCREG_RVBAR_EL2 },
1149 { MiscRegNum64(3, 4, 12, 1, 1), MISCREG_VDISR_EL2 },
1150 { MiscRegNum64(3, 4, 12, 8, 0), MISCREG_ICH_AP0R0_EL2 },
1151 { MiscRegNum64(3, 4, 12, 8, 1), MISCREG_ICH_AP0R1_EL2 },
1152 { MiscRegNum64(3, 4, 12, 8, 2), MISCREG_ICH_AP0R2_EL2 },
1153 { MiscRegNum64(3, 4, 12, 8, 3), MISCREG_ICH_AP0R3_EL2 },
1154 { MiscRegNum64(3, 4, 12, 9, 0), MISCREG_ICH_AP1R0_EL2 },
1155 { MiscRegNum64(3, 4, 12, 9, 1), MISCREG_ICH_AP1R1_EL2 },
1156 { MiscRegNum64(3, 4, 12, 9, 2), MISCREG_ICH_AP1R2_EL2 },
1157 { MiscRegNum64(3, 4, 12, 9, 3), MISCREG_ICH_AP1R3_EL2 },
1158 { MiscRegNum64(3, 4, 12, 9, 5), MISCREG_ICC_SRE_EL2 },
1159 { MiscRegNum64(3, 4, 12, 11, 0), MISCREG_ICH_HCR_EL2 },
1160 { MiscRegNum64(3, 4, 12, 11, 1), MISCREG_ICH_VTR_EL2 },
1161 { MiscRegNum64(3, 4, 12, 11, 2), MISCREG_ICH_MISR_EL2 },
1162 { MiscRegNum64(3, 4, 12, 11, 3), MISCREG_ICH_EISR_EL2 },
1163 { MiscRegNum64(3, 4, 12, 11, 5), MISCREG_ICH_ELRSR_EL2 },
1164 { MiscRegNum64(3, 4, 12, 11, 7), MISCREG_ICH_VMCR_EL2 },
1165 { MiscRegNum64(3, 4, 12, 12, 0), MISCREG_ICH_LR0_EL2 },
1166 { MiscRegNum64(3, 4, 12, 12, 1), MISCREG_ICH_LR1_EL2 },
1167 { MiscRegNum64(3, 4, 12, 12, 2), MISCREG_ICH_LR2_EL2 },
1168 { MiscRegNum64(3, 4, 12, 12, 3), MISCREG_ICH_LR3_EL2 },
1169 { MiscRegNum64(3, 4, 12, 12, 4), MISCREG_ICH_LR4_EL2 },
1170 { MiscRegNum64(3, 4, 12, 12, 5), MISCREG_ICH_LR5_EL2 },
1171 { MiscRegNum64(3, 4, 12, 12, 6), MISCREG_ICH_LR6_EL2 },
1172 { MiscRegNum64(3, 4, 12, 12, 7), MISCREG_ICH_LR7_EL2 },
1173 { MiscRegNum64(3, 4, 12, 13, 0), MISCREG_ICH_LR8_EL2 },
1174 { MiscRegNum64(3, 4, 12, 13, 1), MISCREG_ICH_LR9_EL2 },
1175 { MiscRegNum64(3, 4, 12, 13, 2), MISCREG_ICH_LR10_EL2 },
1176 { MiscRegNum64(3, 4, 12, 13, 3), MISCREG_ICH_LR11_EL2 },
1177 { MiscRegNum64(3, 4, 12, 13, 4), MISCREG_ICH_LR12_EL2 },
1178 { MiscRegNum64(3, 4, 12, 13, 5), MISCREG_ICH_LR13_EL2 },
1179 { MiscRegNum64(3, 4, 12, 13, 6), MISCREG_ICH_LR14_EL2 },
1180 { MiscRegNum64(3, 4, 12, 13, 7), MISCREG_ICH_LR15_EL2 },
1181 { MiscRegNum64(3, 4, 13, 0, 1), MISCREG_CONTEXTIDR_EL2 },
1182 { MiscRegNum64(3, 4, 13, 0, 2), MISCREG_TPIDR_EL2 },
1183 { MiscRegNum64(3, 4, 14, 0, 3), MISCREG_CNTVOFF_EL2 },
1184 { MiscRegNum64(3, 4, 14, 1, 0), MISCREG_CNTHCTL_EL2 },
1185 { MiscRegNum64(3, 4, 14, 2, 0), MISCREG_CNTHP_TVAL_EL2 },
1186 { MiscRegNum64(3, 4, 14, 2, 1), MISCREG_CNTHP_CTL_EL2 },
1187 { MiscRegNum64(3, 4, 14, 2, 2), MISCREG_CNTHP_CVAL_EL2 },
1188 { MiscRegNum64(3, 4, 14, 3, 0), MISCREG_CNTHV_TVAL_EL2 },
1189 { MiscRegNum64(3, 4, 14, 3, 1), MISCREG_CNTHV_CTL_EL2 },
1190 { MiscRegNum64(3, 4, 14, 3, 2), MISCREG_CNTHV_CVAL_EL2 },
1191 { MiscRegNum64(3, 4, 14, 4, 0), MISCREG_CNTHVS_TVAL_EL2 },
1192 { MiscRegNum64(3, 4, 14, 4, 1), MISCREG_CNTHVS_CTL_EL2 },
1193 { MiscRegNum64(3, 4, 14, 4, 2), MISCREG_CNTHVS_CVAL_EL2 },
1194 { MiscRegNum64(3, 4, 14, 5, 0), MISCREG_CNTHPS_TVAL_EL2 },
1195 { MiscRegNum64(3, 4, 14, 5, 1), MISCREG_CNTHPS_CTL_EL2 },
1196 { MiscRegNum64(3, 4, 14, 5, 2), MISCREG_CNTHPS_CVAL_EL2 },
1197 { MiscRegNum64(3, 5, 1, 0, 0), MISCREG_SCTLR_EL12 },
1198 { MiscRegNum64(3, 5, 1, 0, 2), MISCREG_CPACR_EL12 },
1199 { MiscRegNum64(3, 5, 1, 2, 0), MISCREG_ZCR_EL12 },
1200 { MiscRegNum64(3, 5, 1, 2, 6), MISCREG_SMCR_EL12 },
1201 { MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
1202 { MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
1203 { MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
1204 { MiscRegNum64(3, 5, 4, 0, 0), MISCREG_SPSR_EL12 },
1205 { MiscRegNum64(3, 5, 4, 0, 1), MISCREG_ELR_EL12 },
1206 { MiscRegNum64(3, 5, 5, 1, 0), MISCREG_AFSR0_EL12 },
1207 { MiscRegNum64(3, 5, 5, 1, 1), MISCREG_AFSR1_EL12 },
1208 { MiscRegNum64(3, 5, 5, 2, 0), MISCREG_ESR_EL12 },
1209 { MiscRegNum64(3, 5, 6, 0, 0), MISCREG_FAR_EL12 },
1210 { MiscRegNum64(3, 5, 10, 2, 0), MISCREG_MAIR_EL12 },
1211 { MiscRegNum64(3, 5, 10, 3, 0), MISCREG_AMAIR_EL12 },
1212 { MiscRegNum64(3, 5, 12, 0, 0), MISCREG_VBAR_EL12 },
1213 { MiscRegNum64(3, 5, 13, 0, 1), MISCREG_CONTEXTIDR_EL12 },
1214 { MiscRegNum64(3, 5, 14, 1, 0), MISCREG_CNTKCTL_EL12 },
1215 { MiscRegNum64(3, 5, 14, 2, 0), MISCREG_CNTP_TVAL_EL02 },
1216 { MiscRegNum64(3, 5, 14, 2, 1), MISCREG_CNTP_CTL_EL02 },
1217 { MiscRegNum64(3, 5, 14, 2, 2), MISCREG_CNTP_CVAL_EL02 },
1218 { MiscRegNum64(3, 5, 14, 3, 0), MISCREG_CNTV_TVAL_EL02 },
1219 { MiscRegNum64(3, 5, 14, 3, 1), MISCREG_CNTV_CTL_EL02 },
1220 { MiscRegNum64(3, 5, 14, 3, 2), MISCREG_CNTV_CVAL_EL02 },
1221 { MiscRegNum64(3, 6, 1, 0, 0), MISCREG_SCTLR_EL3 },
1222 { MiscRegNum64(3, 6, 1, 0, 1), MISCREG_ACTLR_EL3 },
1223 { MiscRegNum64(3, 6, 1, 1, 0), MISCREG_SCR_EL3 },
1224 { MiscRegNum64(3, 6, 1, 1, 1), MISCREG_SDER32_EL3 },
1225 { MiscRegNum64(3, 6, 1, 1, 2), MISCREG_CPTR_EL3 },
1226 { MiscRegNum64(3, 6, 1, 2, 0), MISCREG_ZCR_EL3 },
1227 { MiscRegNum64(3, 6, 1, 2, 6), MISCREG_SMCR_EL3 },
1228 { MiscRegNum64(3, 6, 1, 3, 1), MISCREG_MDCR_EL3 },
1229 { MiscRegNum64(3, 6, 2, 0, 0), MISCREG_TTBR0_EL3 },
1230 { MiscRegNum64(3, 6, 2, 0, 2), MISCREG_TCR_EL3 },
1231 { MiscRegNum64(3, 6, 4, 0, 0), MISCREG_SPSR_EL3 },
1232 { MiscRegNum64(3, 6, 4, 0, 1), MISCREG_ELR_EL3 },
1233 { MiscRegNum64(3, 6, 4, 1, 0), MISCREG_SP_EL2 },
1234 { MiscRegNum64(3, 6, 5, 1, 0), MISCREG_AFSR0_EL3 },
1235 { MiscRegNum64(3, 6, 5, 1, 1), MISCREG_AFSR1_EL3 },
1236 { MiscRegNum64(3, 6, 5, 2, 0), MISCREG_ESR_EL3 },
1237 { MiscRegNum64(3, 6, 6, 0, 0), MISCREG_FAR_EL3 },
1238 { MiscRegNum64(3, 6, 10, 2, 0), MISCREG_MAIR_EL3 },
1239 { MiscRegNum64(3, 6, 10, 3, 0), MISCREG_AMAIR_EL3 },
1240 { MiscRegNum64(3, 6, 12, 0, 0), MISCREG_VBAR_EL3 },
1241 { MiscRegNum64(3, 6, 12, 0, 1), MISCREG_RVBAR_EL3 },
1242 { MiscRegNum64(3, 6, 12, 0, 2), MISCREG_RMR_EL3 },
1243 { MiscRegNum64(3, 6, 12, 12, 4), MISCREG_ICC_CTLR_EL3 },
1244 { MiscRegNum64(3, 6, 12, 12, 5), MISCREG_ICC_SRE_EL3 },
1245 { MiscRegNum64(3, 6, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL3 },
1246 { MiscRegNum64(3, 6, 13, 0, 2), MISCREG_TPIDR_EL3 },
1247 { MiscRegNum64(3, 7, 14, 2, 0), MISCREG_CNTPS_TVAL_EL1 },
1248 { MiscRegNum64(3, 7, 14, 2, 1), MISCREG_CNTPS_CTL_EL1 },
1249 { MiscRegNum64(3, 7, 14, 2, 2), MISCREG_CNTPS_CVAL_EL1 }
1250};
1251
1252Fault
1253faultSpEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1254 const MiscRegOp64 &inst)
1255{
1256 if (tc->readMiscReg(MISCREG_SPSEL) == 0)
1257 return inst.undefined();
1258 else
1259 return NoFault;
1260}
1261
1262Fault
1263faultDaif(const MiscRegLUTEntry &entry, ThreadContext *tc,
1264 const MiscRegOp64 &inst)
1265{
1266 const bool el2_enabled = EL2Enabled(tc);
1267 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1268 const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1269 if ((el2_enabled && hcr.e2h && hcr.tge) || sctlr.uma == 0) {
1270 if (el2_enabled && hcr.tge) {
1271 return inst.generateTrap(EL2);
1272 } else {
1273 return inst.generateTrap(EL1);
1274 }
1275 } else {
1276 return NoFault;
1277 }
1278}
1279
1280Fault
1281faultDczvaEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1282 const MiscRegOp64 &inst)
1283{
1284 if (!FullSystem)
1285 return NoFault;
1286
1287 const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1288 const SCTLR sctlr2 = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2);
1289 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1290
1291 const bool el2_enabled = EL2Enabled(tc);
1292 const bool in_host = hcr.e2h && hcr.tge;
1293 if (!(el2_enabled && in_host) && !sctlr.dze) {
1294 if (el2_enabled && hcr.tge) {
1295 return inst.generateTrap(EL2);
1296 } else {
1297 return inst.generateTrap(EL1);
1298 }
1299 } else if (el2_enabled && !in_host && hcr.tdz) {
1300 return inst.generateTrap(EL2);
1301 } else if (el2_enabled && in_host && !sctlr2.dze) {
1302 return inst.generateTrap(EL2);
1303 } else {
1304 return NoFault;
1305 }
1306}
1307
1308Fault
1309faultCvacEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1310 const MiscRegOp64 &inst)
1311{
1312 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1313 const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1314 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1315
1316 const bool el2_enabled = EL2Enabled(tc);
1317 const bool in_host = hcr.e2h && hcr.tge;
1318 if (!(el2_enabled && in_host) && !sctlr.uci) {
1319 if (el2_enabled && hcr.tge) {
1320 return inst.generateTrap(EL2);
1321 } else {
1322 return inst.generateTrap(EL1);
1323 }
1324 } else if (el2_enabled && !in_host && hcr.tpc) {
1325 return inst.generateTrap(EL2);
1326 } else if (el2_enabled && in_host && !sctlr2.uci) {
1327 return inst.generateTrap(EL2);
1328 } else {
1329 return NoFault;
1330 }
1331}
1332
1333Fault
1334faultFpcrEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1335 const MiscRegOp64 &inst)
1336{
1337 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1338 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1339 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1340
1341 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1342 const bool el2_enabled = EL2Enabled(tc);
1343 const bool in_host = hcr.e2h && hcr.tge;
1344 if (!(el2_enabled && in_host) && cpacr.fpen != 0b11) {
1345 if (el2_enabled && hcr.tge) {
1346 return inst.generateTrap(EL2, ExceptionClass::UNKNOWN, inst.iss());
1347 } else {
1348 return inst.generateTrap(EL1,
1349 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1350 }
1351 } else if (el2_enabled && in_host && cptr_el2.fpen != 0b11) {
1352 return inst.generateTrap(EL2,
1353 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1354 } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1355 return inst.generateTrap(EL2,
1356 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1357 } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1358 return inst.generateTrap(EL2,
1359 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1360 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1361 return inst.generateTrap(EL3,
1362 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1363 } else {
1364 return NoFault;
1365 }
1366}
1367
1368Fault
1369faultFpcrEL1(const MiscRegLUTEntry &entry, ThreadContext *tc,
1370 const MiscRegOp64 &inst)
1371{
1372 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1373 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1374 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1375
1376 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1377 const bool el2_enabled = EL2Enabled(tc);
1378 if ((cpacr.fpen & 0b1) == 0b0) {
1379 return inst.generateTrap(EL1,
1380 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1381 } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1382 return inst.generateTrap(EL2,
1383 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1384 } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1385 return inst.generateTrap(EL2,
1386 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1387 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1388 return inst.generateTrap(EL3,
1389 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1390 } else {
1391 return NoFault;
1392 }
1393}
1394
1395Fault
1396faultFpcrEL2(const MiscRegLUTEntry &entry, ThreadContext *tc,
1397 const MiscRegOp64 &inst)
1398{
1399 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1400 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1401
1402 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1403 if (!hcr.e2h && cptr_el2.tfp) {
1404 return inst.generateTrap(EL2,
1405 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1406 } else if (hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1407 return inst.generateTrap(EL2,
1408 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1409 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1410 return inst.generateTrap(EL3,
1411 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1412 } else {
1413 return NoFault;
1414 }
1415}
1416
1417Fault
1418faultFpcrEL3(const MiscRegLUTEntry &entry,
1419 ThreadContext *tc, const MiscRegOp64 &inst)
1420{
1421 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1422 if (cptr_el3.tfp) {
1423 return inst.generateTrap(EL3,
1424 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1425 } else {
1426 return NoFault;
1427 }
1428}
1429
1430Fault
1431faultPouEL0(const MiscRegLUTEntry &entry,
1432 ThreadContext *tc, const MiscRegOp64 &inst)
1433{
1434 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1435 const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1436 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1437
1438 const bool el2_enabled = EL2Enabled(tc);
1439 const bool in_host = hcr.e2h && hcr.tge;
1440 if (!(el2_enabled && in_host) && !sctlr.uci) {
1441 if (el2_enabled && hcr.tge) {
1442 return inst.generateTrap(EL2);
1443 } else {
1444 return inst.generateTrap(EL1);
1445 }
1446 } else if (el2_enabled && !in_host && hcr.tpu) {
1447 return inst.generateTrap(EL2);
1448 } else if (el2_enabled && !in_host &&
1449 HaveExt(tc, ArmExtension::FEAT_EVT) && hcr.tocu) {
1450 return inst.generateTrap(EL2);
1451 } else if (el2_enabled && in_host && !sctlr2.uci) {
1452 return inst.generateTrap(EL2);
1453 } else {
1454 return NoFault;
1455 }
1456}
1457
1458Fault
1459faultPouEL1(const MiscRegLUTEntry &entry,
1460 ThreadContext *tc, const MiscRegOp64 &inst)
1461{
1462 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1463 const bool el2_enabled = EL2Enabled(tc);
1464 if (el2_enabled && hcr.tpu) {
1465 return inst.generateTrap(EL2);
1466 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1467 hcr.tocu) {
1468 return inst.generateTrap(EL2);
1469 } else {
1470 return NoFault;
1471 }
1472}
1473
1474Fault
1475faultPouIsEL1(const MiscRegLUTEntry &entry,
1476 ThreadContext *tc, const MiscRegOp64 &inst)
1477{
1478 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1479 const bool el2_enabled = EL2Enabled(tc);
1480 if (el2_enabled && hcr.tpu) {
1481 return inst.generateTrap(EL2);
1482 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1483 hcr.ticab) {
1484 return inst.generateTrap(EL2);
1485 } else {
1486 return NoFault;
1487 }
1488}
1489
1490Fault
1491faultCtrEL0(const MiscRegLUTEntry &entry,
1492 ThreadContext *tc, const MiscRegOp64 &inst)
1493{
1494 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1495 const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1496 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1497
1498 const bool el2_enabled = EL2Enabled(tc);
1499 const bool in_host = hcr.e2h && hcr.tge;
1500 if (!(el2_enabled && in_host) && !sctlr.uct) {
1501 if (el2_enabled && hcr.tge) {
1502 return inst.generateTrap(EL2);
1503 } else {
1504 return inst.generateTrap(EL1);
1505 }
1506 } else if (el2_enabled && !in_host && hcr.tid2) {
1507 return inst.generateTrap(EL2);
1508 } else if (el2_enabled && in_host && !sctlr2.uct) {
1509 return inst.generateTrap(EL2);
1510 } else {
1511 return NoFault;
1512 }
1513}
1514
1515Fault
1516faultMdccsrEL0(const MiscRegLUTEntry &entry,
1517 ThreadContext *tc, const MiscRegOp64 &inst)
1518{
1519 const DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
1520 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1521 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1522
1523 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1524 const bool el2_enabled = EL2Enabled(tc);
1525 if (mdscr.tdcc) {
1526 if (el2_enabled && hcr.tge) {
1527 return inst.generateTrap(EL2);
1528 } else {
1529 return inst.generateTrap(EL1);
1530 }
1531 } else if (el2_enabled && mdcr_el2.tdcc) {
1532 return inst.generateTrap(EL2);
1533 } else if (el2_enabled && (hcr.tge || (mdcr_el2.tde || mdcr_el2.tda))) {
1534 return inst.generateTrap(EL2);
1535 } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1536 return inst.generateTrap(EL3);
1537 } else {
1538 return NoFault;
1539 }
1540}
1541
1542Fault
1543faultMdccsrEL1(const MiscRegLUTEntry &entry,
1544 ThreadContext *tc, const MiscRegOp64 &inst)
1545{
1546 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1547 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1548
1549 const bool el2_enabled = EL2Enabled(tc);
1550 if (el2_enabled && mdcr_el2.tdcc) {
1551 return inst.generateTrap(EL2);
1552 } else if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1553 return inst.generateTrap(EL2);
1554 } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1555 return inst.generateTrap(EL3);
1556 } else {
1557 return NoFault;
1558 }
1559}
1560
1561Fault
1562faultMdccsrEL2(const MiscRegLUTEntry &entry,
1563 ThreadContext *tc, const MiscRegOp64 &inst)
1564{
1565 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1566 if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1567 return inst.generateTrap(EL3);
1568 } else {
1569 return NoFault;
1570 }
1571}
1572
1573Fault
1574faultDebugEL1(const MiscRegLUTEntry &entry,
1575 ThreadContext *tc, const MiscRegOp64 &inst)
1576{
1577 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1578 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1579
1580 const bool el2_enabled = EL2Enabled(tc);
1581 if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1582 return inst.generateTrap(EL2);
1583 } else if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1584 return inst.generateTrap(EL3);
1585 } else {
1586 return NoFault;
1587 }
1588}
1589
1590Fault
1591faultDebugEL2(const MiscRegLUTEntry &entry,
1592 ThreadContext *tc, const MiscRegOp64 &inst)
1593{
1594 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1595 if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1596 return inst.generateTrap(EL3);
1597 } else {
1598 return NoFault;
1599 }
1600}
1601
1602Fault
1603faultHcrxEL2(const MiscRegLUTEntry &entry,
1604 ThreadContext *tc, const MiscRegOp64 &inst)
1605{
1606 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1607 if (ArmSystem::haveEL(tc, EL3) && !scr.hxen) {
1608 return inst.generateTrap(EL3);
1609 } else {
1610 return NoFault;
1611 }
1612}
1613
1614Fault
1615faultZcrEL1(const MiscRegLUTEntry &entry,
1616 ThreadContext *tc, const MiscRegOp64 &inst)
1617{
1618 const CPACR cpacr_el1 = tc->readMiscReg(MISCREG_CPACR_EL1);
1619 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1620 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1621
1622 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1623 const bool el2_enabled = EL2Enabled(tc);
1624 if (!(cpacr_el1.zen & 0x1)) {
1625 return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SVE, 0);
1626 } else if (el2_enabled && !hcr.e2h && cptr_el2.tz) {
1627 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1628 } else if (el2_enabled && hcr.e2h && !(cptr_el2.zen & 0x1)) {
1629 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1630 } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
1631 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1632 } else {
1633 return NoFault;
1634 }
1635}
1636
1637Fault
1638faultZcrEL2(const MiscRegLUTEntry &entry,
1639 ThreadContext *tc, const MiscRegOp64 &inst)
1640{
1641 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1642 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1643
1644 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1645 if (!hcr.e2h && cptr_el2.tz) {
1646 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1647 } else if (hcr.e2h && !(cptr_el2.zen & 0x1)) {
1648 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
1649 } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
1650 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1651 } else {
1652 return NoFault;
1653 }
1654}
1655
1656Fault
1657faultZcrEL3(const MiscRegLUTEntry &entry,
1658 ThreadContext *tc, const MiscRegOp64 &inst)
1659{
1660 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1661 if (!cptr_el3.ez) {
1662 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
1663 } else {
1664 return NoFault;
1665 }
1666}
1667
1668Fault
1669faultGicv3(const MiscRegLUTEntry &entry,
1670 ThreadContext *tc, const MiscRegOp64 &inst)
1671{
1672 auto gic = static_cast<ArmSystem*>(tc->getSystemPtr())->getGIC();
1673 if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
1674 return inst.undefined();
1675 } else {
1676 return NoFault;
1677 }
1678}
1679
1680Fault
1681faultIccSgiEL1(const MiscRegLUTEntry &entry,
1682 ThreadContext *tc, const MiscRegOp64 &inst)
1683{
1684 if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
1685 return fault;
1686 }
1687
1688 const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
1689 tc->readMiscReg(MISCREG_ICH_HCR_EL2);
1690 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1691 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1692 if (EL2Enabled(tc) && (hcr.fmo || hcr.imo || ich_hcr.TC)) {
1693 return inst.generateTrap(EL2);
1694 } else if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
1695 return inst.generateTrap(EL3);
1696 } else {
1697 return NoFault;
1698 }
1699}
1700
1701Fault
1702faultIccSgiEL2(const MiscRegLUTEntry &entry,
1703 ThreadContext *tc, const MiscRegOp64 &inst)
1704{
1705 if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
1706 return fault;
1707 }
1708
1709 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1710 if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
1711 return inst.generateTrap(EL3);
1712 } else {
1713 return NoFault;
1714 }
1715}
1716
1717Fault
1718faultCpacrEL1(const MiscRegLUTEntry &entry,
1719 ThreadContext *tc, const MiscRegOp64 &inst)
1720{
1721 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1722 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1723 if (EL2Enabled(tc) && cptr_el2.tcpac) {
1724 return inst.generateTrap(EL2);
1725 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
1726 return inst.generateTrap(EL3);
1727 } else {
1728 return NoFault;
1729 }
1730}
1731
1732Fault
1733faultCpacrEL2(const MiscRegLUTEntry &entry,
1734 ThreadContext *tc, const MiscRegOp64 &inst)
1735{
1736 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1737 if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
1738 return inst.generateTrap(EL3);
1739 } else {
1740 return NoFault;
1741 }
1742}
1743
1744Fault
1745faultCpacrVheEL2(const MiscRegLUTEntry &entry,
1746 ThreadContext *tc, const MiscRegOp64 &inst)
1747{
1748 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1749 if (hcr.e2h) {
1750 return faultCpacrEL2(entry, tc, inst);
1751 } else {
1752 return inst.undefined();
1753 }
1754}
1755
1756#define HCR_TRAP(bitfield) [] (const MiscRegLUTEntry &entry, \
1757 ThreadContext *tc, const MiscRegOp64 &inst) -> Fault \
1758{ \
1759 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); \
1760 if (EL2Enabled(tc) && hcr.bitfield) { \
1761 return inst.generateTrap(EL2); \
1762 } else { \
1763 return NoFault; \
1764 } \
1765}
1766
1767Fault
1768faultTlbiOsEL1(const MiscRegLUTEntry &entry,
1769 ThreadContext *tc, const MiscRegOp64 &inst)
1770{
1771 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1772 const bool el2_enabled = EL2Enabled(tc);
1773 if (el2_enabled && hcr.ttlb) {
1774 return inst.generateTrap(EL2);
1775 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1776 hcr.ttlbos) {
1777 return inst.generateTrap(EL2);
1778 } else {
1779 return NoFault;
1780 }
1781}
1782
1783Fault
1784faultTlbiIsEL1(const MiscRegLUTEntry &entry,
1785 ThreadContext *tc, const MiscRegOp64 &inst)
1786{
1787 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1788 const bool el2_enabled = EL2Enabled(tc);
1789 if (el2_enabled && hcr.ttlb) {
1790 return inst.generateTrap(EL2);
1791 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1792 hcr.ttlbis) {
1793 return inst.generateTrap(EL2);
1794 } else {
1795 return NoFault;
1796 }
1797}
1798
1799Fault
1800faultCacheEL1(const MiscRegLUTEntry &entry,
1801 ThreadContext *tc, const MiscRegOp64 &inst)
1802{
1803 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1804 const bool el2_enabled = EL2Enabled(tc);
1805 if (el2_enabled && hcr.tid2) {
1806 return inst.generateTrap(EL2);
1807 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1808 hcr.tid4) {
1809 return inst.generateTrap(EL2);
1810 } else {
1811 return NoFault;
1812 }
1813}
1814
1815Fault
1816faultPauthEL1(const MiscRegLUTEntry &entry,
1817 ThreadContext *tc, const MiscRegOp64 &inst)
1818{
1819 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1820 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1821 if (EL2Enabled(tc) && !hcr.apk) {
1822 return inst.generateTrap(EL2);
1823 } else if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
1824 return inst.generateTrap(EL3);
1825 } else {
1826 return NoFault;
1827 }
1828}
1829
1830Fault
1831faultPauthEL2(const MiscRegLUTEntry &entry,
1832 ThreadContext *tc, const MiscRegOp64 &inst)
1833{
1834 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1835 if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
1836 return inst.generateTrap(EL3);
1837 } else {
1838 return NoFault;
1839 }
1840}
1841
1842Fault
1843faultGenericTimerEL0(const MiscRegLUTEntry &entry,
1844 ThreadContext *tc, const MiscRegOp64 &inst)
1845{
1846 const bool el2_enabled = EL2Enabled(tc);
1847 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1848 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1849 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1850 const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1851 if (!(in_host) && !cntkctl_el1.el0pcten && !cntkctl_el1.el0vcten) {
1852 if (el2_enabled && hcr.tge)
1853 return inst.generateTrap(EL2);
1854 else
1855 return inst.generateTrap(EL1);
1856 } else if (in_host && !cnthctl_el2.el0pcten && !cnthctl_el2.el0vcten) {
1857 return inst.generateTrap(EL2);
1858 } else {
1859 return NoFault;
1860 }
1861}
1862
1863Fault
1864faultCntpctEL0(const MiscRegLUTEntry &entry,
1865 ThreadContext *tc, const MiscRegOp64 &inst)
1866{
1867 const bool el2_enabled = EL2Enabled(tc);
1868 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1869 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1870 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1871 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1872 if (!(in_host) && !cntkctl_el1.el0pcten) {
1873 if (el2_enabled && hcr.tge)
1874 return inst.generateTrap(EL2);
1875 else
1876 return inst.generateTrap(EL1);
1877 } else if (el2_enabled && !hcr.e2h &&
1878 !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
1879 return inst.generateTrap(EL2);
1880 } else if (el2_enabled && hcr.e2h && !hcr.tge &&
1881 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
1882 return inst.generateTrap(EL2);
1883 } else if (in_host &&
1884 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pcten) {
1885 return inst.generateTrap(EL2);
1886 } else {
1887 return NoFault;
1888 }
1889}
1890
1891Fault
1892faultCntpctEL1(const MiscRegLUTEntry &entry,
1893 ThreadContext *tc, const MiscRegOp64 &inst)
1894{
1895 const bool el2_enabled = EL2Enabled(tc);
1896 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1897 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1898 if (el2_enabled && hcr.e2h &&
1899 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
1900 return inst.generateTrap(EL2);
1901 } else if (el2_enabled && !hcr.e2h &&
1902 !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
1903 return inst.generateTrap(EL2);
1904 } else {
1905 return NoFault;
1906 }
1907}
1908
1909Fault
1910faultCntvctEL0(const MiscRegLUTEntry &entry,
1911 ThreadContext *tc, const MiscRegOp64 &inst)
1912{
1913 const bool el2_enabled = EL2Enabled(tc);
1914 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1915 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1916 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1917 const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1918 if (!(in_host) && !cntkctl_el1.el0vcten) {
1919 if (el2_enabled && hcr.tge)
1920 return inst.generateTrap(EL2);
1921 else
1922 return inst.generateTrap(EL1);
1923 } else if (in_host && !cnthctl_el2.el0vcten) {
1924 return inst.generateTrap(EL2);
1925 } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvct) {
1926 return inst.generateTrap(EL2);
1927 } else {
1928 return NoFault;
1929 }
1930}
1931
1932Fault
1933faultCntvctEL1(const MiscRegLUTEntry &entry,
1934 ThreadContext *tc, const MiscRegOp64 &inst)
1935{
1936 const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1937 if (EL2Enabled(tc) && cnthctl_el2.el1tvct) {
1938 return inst.generateTrap(EL2);
1939 } else {
1940 return NoFault;
1941 }
1942}
1943
1944//TODO: See faultCntpctEL0
1945Fault
1946faultCntpCtlEL0(const MiscRegLUTEntry &entry,
1947 ThreadContext *tc, const MiscRegOp64 &inst)
1948{
1949 const bool el2_enabled = EL2Enabled(tc);
1950 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1951 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1952 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
1953 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1954 if (!(in_host) && !cntkctl_el1.el0pten) {
1955 if (el2_enabled && hcr.tge)
1956 return inst.generateTrap(EL2);
1957 else
1958 return inst.generateTrap(EL1);
1959 } else if (el2_enabled && !hcr.e2h &&
1960 !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
1961 return inst.generateTrap(EL2);
1962 } else if (el2_enabled && hcr.e2h && !hcr.tge &&
1963 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
1964 return inst.generateTrap(EL2);
1965 } else if (in_host &&
1966 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pten) {
1967 return inst.generateTrap(EL2);
1968 } else {
1969 return NoFault;
1970 }
1971}
1972
1973Fault
1974faultCntpCtlEL1(const MiscRegLUTEntry &entry,
1975 ThreadContext *tc, const MiscRegOp64 &inst)
1976{
1977 const bool el2_enabled = EL2Enabled(tc);
1978 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1979 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
1980 if (el2_enabled && !hcr.e2h &&
1981 !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
1982 return inst.generateTrap(EL2);
1983 } else if (el2_enabled && hcr.e2h &&
1984 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
1985 return inst.generateTrap(EL2);
1986 } else {
1987 return NoFault;
1988 }
1989}
1990
1991// TODO: see faultCntvctEL0
1992Fault
1993faultCntvCtlEL0(const MiscRegLUTEntry &entry,
1994 ThreadContext *tc, const MiscRegOp64 &inst)
1995{
1996 const bool el2_enabled = EL2Enabled(tc);
1997 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1998 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
1999 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
2000 const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2001 if (!(in_host) && !cntkctl_el1.el0vten) {
2002 if (el2_enabled && hcr.tge)
2003 return inst.generateTrap(EL2);
2004 else
2005 return inst.generateTrap(EL1);
2006 } else if (in_host && !cnthctl_el2.el0vten) {
2007 return inst.generateTrap(EL2);
2008 } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvt) {
2009 return inst.generateTrap(EL2);
2010 } else {
2011 return NoFault;
2012 }
2013}
2014
2015Fault
2016faultCntvCtlEL1(const MiscRegLUTEntry &entry,
2017 ThreadContext *tc, const MiscRegOp64 &inst)
2018{
2019 const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2020 if (EL2Enabled(tc) && cnthctl_el2.el1tvt) {
2021 return inst.generateTrap(EL2);
2022 } else {
2023 return NoFault;
2024 }
2025}
2026
2027Fault
2028faultCntpsCtlEL1(const MiscRegLUTEntry &entry,
2029 ThreadContext *tc, const MiscRegOp64 &inst)
2030{
2031 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2032 if (ArmSystem::haveEL(tc, EL3) && !scr.ns) {
2033 if (scr.eel2)
2034 return inst.undefined();
2035 else if (!scr.st)
2036 return inst.generateTrap(EL3);
2037 else
2038 return NoFault;
2039 } else {
2040 return inst.undefined();
2041 }
2042}
2043
2044Fault
2045faultUnimplemented(const MiscRegLUTEntry &entry,
2046 ThreadContext *tc, const MiscRegOp64 &inst)
2047{
2048 if (entry.info[MISCREG_WARN_NOT_FAIL]) {
2049 return NoFault;
2050 } else {
2051 return inst.undefined();
2052 }
2053}
2054
2055Fault
2056faultImpdefUnimplEL1(const MiscRegLUTEntry &entry,
2057 ThreadContext *tc, const MiscRegOp64 &inst)
2058{
2059 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2060 if (EL2Enabled(tc) && hcr.tidcp) {
2061 return inst.generateTrap(EL2);
2062 } else {
2063 return faultUnimplemented(entry, tc, inst);
2064 }
2065}
2066
2067Fault
2068faultEsm(const MiscRegLUTEntry &entry,
2069 ThreadContext *tc, const MiscRegOp64 &inst)
2070{
2071 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2072 if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.esm) {
2073 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SME, 0);
2074 } else {
2075 return NoFault;
2076 }
2077}
2078
2079Fault
2080faultTsmSmen(const MiscRegLUTEntry &entry,
2081 ThreadContext *tc, const MiscRegOp64 &inst)
2082{
2083 const HCR hcr_el2 = tc->readMiscReg(MISCREG_HCR_EL2);
2084 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2085 const bool el2_enabled = EL2Enabled(tc);
2086 if (el2_enabled && !hcr_el2.e2h && cptr_el2.tsm) {
2087 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2088 } else if (el2_enabled && hcr_el2.e2h && !(cptr_el2.smen & 0b1)) {
2089 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2090 } else {
2091 return faultEsm(entry, tc, inst);
2092 }
2093}
2094
2095Fault
2096faultSmenEL1(const MiscRegLUTEntry &entry,
2097 ThreadContext *tc, const MiscRegOp64 &inst)
2098{
2099 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
2100 if (!(cpacr.smen & 0b1)) {
2101 return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
2102 } else {
2103 return faultTsmSmen(entry, tc, inst);
2104 }
2105}
2106
2107Fault
2108faultSmenEL0(const MiscRegLUTEntry &entry,
2109 ThreadContext *tc, const MiscRegOp64 &inst)
2110{
2111 const bool el2_enabled = EL2Enabled(tc);
2112 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2113 const bool in_host = hcr.e2h && hcr.tge;
2114
2115 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
2116 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2117 if (!(el2_enabled && in_host) && cpacr.smen != 0b11) {
2118 if (el2_enabled && hcr.tge)
2119 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2120 else
2121 return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
2122 } else if (el2_enabled && in_host && cptr_el2.smen != 0b11) {
2123 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2124 } else {
2125 return faultTsmSmen(entry, tc, inst);
2126 }
2127}
2128
2129Fault
2130faultRng(const MiscRegLUTEntry &entry,
2131 ThreadContext *tc, const MiscRegOp64 &inst)
2132{
2133 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2134 if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
2135 return inst.generateTrap(EL3);
2136 } else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
2137 return inst.undefined();
2138 } else {
2139 return NoFault;
2140 }
2141}
2142
2143Fault
2144faultIdst(const MiscRegLUTEntry &entry,
2145 ThreadContext *tc, const MiscRegOp64 &inst)
2146{
2147 if (HaveExt(tc, ArmExtension::FEAT_IDST)) {
2148 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2149 if (EL2Enabled(tc) && hcr.tge) {
2150 return inst.generateTrap(EL2);
2151 } else {
2152 return inst.generateTrap(EL1);
2153 }
2154 } else {
2155 return inst.undefined();
2156 }
2157}
2158
2159}
2160
2161MiscRegIndex
2162decodeAArch64SysReg(unsigned op0, unsigned op1,
2163 unsigned crn, unsigned crm,
2164 unsigned op2)
2165{
2166 MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
2167 return decodeAArch64SysReg(sys_reg);
2168}
2169
2170MiscRegIndex
2171decodeAArch64SysReg(const MiscRegNum64 &sys_reg)
2172{
2173 auto it = miscRegNumToIdx.find(sys_reg);
2174 if (it != miscRegNumToIdx.end()) {
2175 return it->second;
2176 } else {
2177 // Check for a pseudo register before returning MISCREG_UNKNOWN
2178 if ((sys_reg.op0 == 1 || sys_reg.op0 == 3) &&
2179 (sys_reg.crn == 11 || sys_reg.crn == 15)) {
2180 return MISCREG_IMPDEF_UNIMPL;
2181 } else {
2182 return MISCREG_UNKNOWN;
2183 }
2184 }
2185}
2186
2187MiscRegNum64
2188encodeAArch64SysReg(MiscRegIndex misc_reg)
2189{
2190 if (auto it = idxToMiscRegNum.find(misc_reg);
2191 it != idxToMiscRegNum.end()) {
2192 return it->second;
2193 } else {
2194 panic("Invalid MiscRegIndex: %d\n", misc_reg);
2195 }
2196}
2197
2198Fault
2199MiscRegLUTEntry::checkFault(ThreadContext *tc,
2200 const MiscRegOp64 &inst, ExceptionLevel el)
2201{
2202 return !inst.miscRead() ? faultWrite[el](*this, tc, inst) :
2203 faultRead[el](*this, tc, inst);
2204}
2205
2206template <MiscRegInfo Sec, MiscRegInfo NonSec>
2207Fault
2208MiscRegLUTEntry::defaultFault(const MiscRegLUTEntry &entry,
2209 ThreadContext *tc, const MiscRegOp64 &inst)
2210{
2211 if (isSecureBelowEL3(tc) ? entry.info[Sec] : entry.info[NonSec]) {
2212 return NoFault;
2213 } else {
2214 return inst.undefined();
2215 }
2216}
2217
2218static Fault
2219defaultFaultE2H_EL2(const MiscRegLUTEntry &entry,
2220 ThreadContext *tc, const MiscRegOp64 &inst)
2221{
2222 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2223 if (hcr.e2h) {
2224 return NoFault;
2225 } else {
2226 return inst.undefined();
2227 }
2228}
2229
2230static Fault
2231defaultFaultE2H_EL3(const MiscRegLUTEntry &entry,
2232 ThreadContext *tc, const MiscRegOp64 &inst)
2233{
2234 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2235 const bool el2_host = EL2Enabled(tc) && hcr.e2h;
2236 if (el2_host) {
2237 return NoFault;
2238 } else {
2239 return inst.undefined();
2240 }
2241}
2242
2243MiscRegLUTEntryInitializer::chain
2244MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2245{
2246 switch (FullSystem ? sys->highestEL() : EL1) {
2247 case EL0:
2248 case EL1: priv(); break;
2249 case EL2: hyp(); break;
2250 case EL3: mon(); break;
2251 }
2252 return *this;
2253}
2254
2255static CPSR
2256resetCPSR(ArmSystem *system)
2257{
2258 CPSR cpsr = 0;
2259 if (!FullSystem) {
2260 cpsr.mode = MODE_USER;
2261 } else {
2262 switch (system->highestEL()) {
2263 // Set initial EL to highest implemented EL using associated stack
2264 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
2265 // value
2266 case EL3:
2267 cpsr.mode = MODE_EL3H;
2268 break;
2269 case EL2:
2270 cpsr.mode = MODE_EL2H;
2271 break;
2272 case EL1:
2273 cpsr.mode = MODE_EL1H;
2274 break;
2275 default:
2276 panic("Invalid highest implemented exception level");
2277 break;
2278 }
2279
2280 // Initialize rest of CPSR
2281 cpsr.daif = 0xf; // Mask all interrupts
2282 cpsr.ss = 0;
2283 cpsr.il = 0;
2284 }
2285 return cpsr;
2286}
2287
2288void
2289ISA::initializeMiscRegMetadata()
2290{
2291 // the MiscReg metadata tables are shared across all instances of the
2292 // ISA object, so there's no need to initialize them multiple times.
2293 static bool completed = false;
2294 if (completed)
2295 return;
2296
2297 // This boolean variable specifies if the system is running in aarch32 at
2298 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2299 // is running in aarch64 (aarch32EL3 = false)
2300 bool aarch32EL3 = release->has(ArmExtension::SECURITY) && !highestELIs64;
2301
2302 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2303 // unsupported
2304 bool SPAN = false;
2305
2306 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2307 bool IESB = false;
2308
2309 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2310 // unsupported
2311 bool LSMAOE = false;
2312
2313 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2314 bool nTLSMD = false;
2315
2316 // Pointer authentication (Arm 8.3+), unsupported
2317 bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2318 bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2319 bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2320 bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2321
2322 const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE);
2323 const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2);
2324
2325 const Params &p(params());
2326
2327 uint32_t midr;
2328 if (p.midr != 0x0)
2329 midr = p.midr;
2330 else if (highestELIs64)
2331 // Cortex-A57 TRM r0p0 MIDR
2332 midr = 0x410fd070;
2333 else
2334 // Cortex-A15 TRM r0p0 MIDR
2335 midr = 0x410fc0f0;
2336
2350 InitReg(MISCREG_CPSR)
2351 .reset(resetCPSR(system))
2352 .allPrivileges();
2353 InitReg(MISCREG_SPSR)
2354 .allPrivileges();
2355 InitReg(MISCREG_SPSR_FIQ)
2356 .allPrivileges();
2357 InitReg(MISCREG_SPSR_IRQ)
2358 .allPrivileges();
2359 InitReg(MISCREG_SPSR_SVC)
2360 .allPrivileges();
2361 InitReg(MISCREG_SPSR_MON)
2362 .allPrivileges();
2363 InitReg(MISCREG_SPSR_ABT)
2364 .allPrivileges();
2365 InitReg(MISCREG_SPSR_HYP)
2366 .allPrivileges();
2367 InitReg(MISCREG_SPSR_UND)
2368 .allPrivileges();
2369 InitReg(MISCREG_ELR_HYP)
2370 .allPrivileges();
2371 InitReg(MISCREG_FPSID)
2372 .reset(p.fpsid)
2373 .allPrivileges();
2374 InitReg(MISCREG_FPSCR)
2375 .res0(mask(14, 13) | mask(6, 5))
2376 .allPrivileges();
2377 InitReg(MISCREG_MVFR1)
2378 .reset([] () {
2379 MVFR1 mvfr1 = 0;
2380 mvfr1.flushToZero = 1;
2381 mvfr1.defaultNaN = 1;
2382 mvfr1.advSimdLoadStore = 1;
2383 mvfr1.advSimdInteger = 1;
2384 mvfr1.advSimdSinglePrecision = 1;
2385 mvfr1.advSimdHalfPrecision = 1;
2386 mvfr1.vfpHalfPrecision = 1;
2387 return mvfr1;
2388 }())
2389 .allPrivileges();
2390 InitReg(MISCREG_MVFR0)
2391 .reset([] () {
2392 MVFR0 mvfr0 = 0;
2393 mvfr0.advSimdRegisters = 2;
2394 mvfr0.singlePrecision = 2;
2395 mvfr0.doublePrecision = 2;
2396 mvfr0.vfpExceptionTrapping = 0;
2397 mvfr0.divide = 1;
2398 mvfr0.squareRoot = 1;
2399 mvfr0.shortVectors = 1;
2400 mvfr0.roundingModes = 1;
2401 return mvfr0;
2402 }())
2403 .allPrivileges();
2404 InitReg(MISCREG_FPEXC)
2405 .allPrivileges();
2406
2407 // Helper registers
2408 InitReg(MISCREG_CPSR_MODE)
2409 .allPrivileges();
2410 InitReg(MISCREG_CPSR_Q)
2411 .allPrivileges();
2412 InitReg(MISCREG_FPSCR_EXC)
2413 .allPrivileges();
2414 InitReg(MISCREG_FPSCR_QC)
2415 .allPrivileges();
2416 InitReg(MISCREG_LOCKADDR)
2417 .allPrivileges();
2418 InitReg(MISCREG_LOCKFLAG)
2419 .allPrivileges();
2420 InitReg(MISCREG_PRRR_MAIR0)
2421 .mutex()
2422 .banked();
2423 InitReg(MISCREG_PRRR_MAIR0_NS)
2424 .mutex()
2425 .privSecure(!aarch32EL3)
2426 .bankedChild();
2427 InitReg(MISCREG_PRRR_MAIR0_S)
2428 .mutex()
2429 .bankedChild();
2430 InitReg(MISCREG_NMRR_MAIR1)
2431 .mutex()
2432 .banked();
2433 InitReg(MISCREG_NMRR_MAIR1_NS)
2434 .mutex()
2435 .privSecure(!aarch32EL3)
2436 .bankedChild();
2437 InitReg(MISCREG_NMRR_MAIR1_S)
2438 .mutex()
2439 .bankedChild();
2440 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2441 .mutex();
2442 InitReg(MISCREG_SEV_MAILBOX)
2443 .reset(1) // Start with an event in the mailbox
2444 .allPrivileges();
2445 InitReg(MISCREG_TLBINEEDSYNC)
2446 .allPrivileges().exceptUserMode();
2447
2448 // AArch32 CP14 registers
2449 InitReg(MISCREG_DBGDIDR)
2450 .reset(0x6 << 16) // Armv8 Debug architecture
2451 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2452 InitReg(MISCREG_DBGDSCRint)
2453 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2454 InitReg(MISCREG_DBGDCCINT)
2455 .unimplemented()
2456 .allPrivileges();
2457 InitReg(MISCREG_DBGDTRTXint)
2458 .unimplemented()
2459 .allPrivileges();
2460 InitReg(MISCREG_DBGDTRRXint)
2461 .unimplemented()
2462 .allPrivileges();
2463 InitReg(MISCREG_DBGWFAR)
2464 .unimplemented()
2465 .allPrivileges();
2466 InitReg(MISCREG_DBGVCR)
2467 .allPrivileges().exceptUserMode();
2468 InitReg(MISCREG_DBGDTRRXext)
2469 .unimplemented()
2470 .allPrivileges();
2471 InitReg(MISCREG_DBGDSCRext)
2472 .allPrivileges();
2473 InitReg(MISCREG_DBGDTRTXext)
2474 .unimplemented()
2475 .allPrivileges();
2476 InitReg(MISCREG_DBGOSECCR)
2477 .unimplemented()
2478 .allPrivileges();
2479 InitReg(MISCREG_DBGBVR0)
2480 .allPrivileges().exceptUserMode();
2481 InitReg(MISCREG_DBGBVR1)
2482 .allPrivileges().exceptUserMode();
2483 InitReg(MISCREG_DBGBVR2)
2484 .allPrivileges().exceptUserMode();
2485 InitReg(MISCREG_DBGBVR3)
2486 .allPrivileges().exceptUserMode();
2487 InitReg(MISCREG_DBGBVR4)
2488 .allPrivileges().exceptUserMode();
2489 InitReg(MISCREG_DBGBVR5)
2490 .allPrivileges().exceptUserMode();
2491 InitReg(MISCREG_DBGBVR6)
2492 .allPrivileges().exceptUserMode();
2493 InitReg(MISCREG_DBGBVR7)
2494 .allPrivileges().exceptUserMode();
2495 InitReg(MISCREG_DBGBVR8)
2496 .allPrivileges().exceptUserMode();
2497 InitReg(MISCREG_DBGBVR9)
2498 .allPrivileges().exceptUserMode();
2499 InitReg(MISCREG_DBGBVR10)
2500 .allPrivileges().exceptUserMode();
2501 InitReg(MISCREG_DBGBVR11)
2502 .allPrivileges().exceptUserMode();
2503 InitReg(MISCREG_DBGBVR12)
2504 .allPrivileges().exceptUserMode();
2505 InitReg(MISCREG_DBGBVR13)
2506 .allPrivileges().exceptUserMode();
2507 InitReg(MISCREG_DBGBVR14)
2508 .allPrivileges().exceptUserMode();
2509 InitReg(MISCREG_DBGBVR15)
2510 .allPrivileges().exceptUserMode();
2511 InitReg(MISCREG_DBGBCR0)
2512 .allPrivileges().exceptUserMode();
2513 InitReg(MISCREG_DBGBCR1)
2514 .allPrivileges().exceptUserMode();
2515 InitReg(MISCREG_DBGBCR2)
2516 .allPrivileges().exceptUserMode();
2517 InitReg(MISCREG_DBGBCR3)
2518 .allPrivileges().exceptUserMode();
2519 InitReg(MISCREG_DBGBCR4)
2520 .allPrivileges().exceptUserMode();
2521 InitReg(MISCREG_DBGBCR5)
2522 .allPrivileges().exceptUserMode();
2523 InitReg(MISCREG_DBGBCR6)
2524 .allPrivileges().exceptUserMode();
2525 InitReg(MISCREG_DBGBCR7)
2526 .allPrivileges().exceptUserMode();
2527 InitReg(MISCREG_DBGBCR8)
2528 .allPrivileges().exceptUserMode();
2529 InitReg(MISCREG_DBGBCR9)
2530 .allPrivileges().exceptUserMode();
2531 InitReg(MISCREG_DBGBCR10)
2532 .allPrivileges().exceptUserMode();
2533 InitReg(MISCREG_DBGBCR11)
2534 .allPrivileges().exceptUserMode();
2535 InitReg(MISCREG_DBGBCR12)
2536 .allPrivileges().exceptUserMode();
2537 InitReg(MISCREG_DBGBCR13)
2538 .allPrivileges().exceptUserMode();
2539 InitReg(MISCREG_DBGBCR14)
2540 .allPrivileges().exceptUserMode();
2541 InitReg(MISCREG_DBGBCR15)
2542 .allPrivileges().exceptUserMode();
2543 InitReg(MISCREG_DBGWVR0)
2544 .allPrivileges().exceptUserMode();
2545 InitReg(MISCREG_DBGWVR1)
2546 .allPrivileges().exceptUserMode();
2547 InitReg(MISCREG_DBGWVR2)
2548 .allPrivileges().exceptUserMode();
2549 InitReg(MISCREG_DBGWVR3)
2550 .allPrivileges().exceptUserMode();
2551 InitReg(MISCREG_DBGWVR4)
2552 .allPrivileges().exceptUserMode();
2553 InitReg(MISCREG_DBGWVR5)
2554 .allPrivileges().exceptUserMode();
2555 InitReg(MISCREG_DBGWVR6)
2556 .allPrivileges().exceptUserMode();
2557 InitReg(MISCREG_DBGWVR7)
2558 .allPrivileges().exceptUserMode();
2559 InitReg(MISCREG_DBGWVR8)
2560 .allPrivileges().exceptUserMode();
2561 InitReg(MISCREG_DBGWVR9)
2562 .allPrivileges().exceptUserMode();
2563 InitReg(MISCREG_DBGWVR10)
2564 .allPrivileges().exceptUserMode();
2565 InitReg(MISCREG_DBGWVR11)
2566 .allPrivileges().exceptUserMode();
2567 InitReg(MISCREG_DBGWVR12)
2568 .allPrivileges().exceptUserMode();
2569 InitReg(MISCREG_DBGWVR13)
2570 .allPrivileges().exceptUserMode();
2571 InitReg(MISCREG_DBGWVR14)
2572 .allPrivileges().exceptUserMode();
2573 InitReg(MISCREG_DBGWVR15)
2574 .allPrivileges().exceptUserMode();
2575 InitReg(MISCREG_DBGWCR0)
2576 .allPrivileges().exceptUserMode();
2577 InitReg(MISCREG_DBGWCR1)
2578 .allPrivileges().exceptUserMode();
2579 InitReg(MISCREG_DBGWCR2)
2580 .allPrivileges().exceptUserMode();
2581 InitReg(MISCREG_DBGWCR3)
2582 .allPrivileges().exceptUserMode();
2583 InitReg(MISCREG_DBGWCR4)
2584 .allPrivileges().exceptUserMode();
2585 InitReg(MISCREG_DBGWCR5)
2586 .allPrivileges().exceptUserMode();
2587 InitReg(MISCREG_DBGWCR6)
2588 .allPrivileges().exceptUserMode();
2589 InitReg(MISCREG_DBGWCR7)
2590 .allPrivileges().exceptUserMode();
2591 InitReg(MISCREG_DBGWCR8)
2592 .allPrivileges().exceptUserMode();
2593 InitReg(MISCREG_DBGWCR9)
2594 .allPrivileges().exceptUserMode();
2595 InitReg(MISCREG_DBGWCR10)
2596 .allPrivileges().exceptUserMode();
2597 InitReg(MISCREG_DBGWCR11)
2598 .allPrivileges().exceptUserMode();
2599 InitReg(MISCREG_DBGWCR12)
2600 .allPrivileges().exceptUserMode();
2601 InitReg(MISCREG_DBGWCR13)
2602 .allPrivileges().exceptUserMode();
2603 InitReg(MISCREG_DBGWCR14)
2604 .allPrivileges().exceptUserMode();
2605 InitReg(MISCREG_DBGWCR15)
2606 .allPrivileges().exceptUserMode();
2607 InitReg(MISCREG_DBGDRAR)
2608 .unimplemented()
2609 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2610 InitReg(MISCREG_DBGBXVR0)
2611 .allPrivileges().exceptUserMode();
2612 InitReg(MISCREG_DBGBXVR1)
2613 .allPrivileges().exceptUserMode();
2614 InitReg(MISCREG_DBGBXVR2)
2615 .allPrivileges().exceptUserMode();
2616 InitReg(MISCREG_DBGBXVR3)
2617 .allPrivileges().exceptUserMode();
2618 InitReg(MISCREG_DBGBXVR4)
2619 .allPrivileges().exceptUserMode();
2620 InitReg(MISCREG_DBGBXVR5)
2621 .allPrivileges().exceptUserMode();
2622 InitReg(MISCREG_DBGBXVR0)
2623 .allPrivileges().exceptUserMode();
2624 InitReg(MISCREG_DBGBXVR6)
2625 .allPrivileges().exceptUserMode();
2626 InitReg(MISCREG_DBGBXVR7)
2627 .allPrivileges().exceptUserMode();
2628 InitReg(MISCREG_DBGBXVR8)
2629 .allPrivileges().exceptUserMode();
2630 InitReg(MISCREG_DBGBXVR9)
2631 .allPrivileges().exceptUserMode();
2632 InitReg(MISCREG_DBGBXVR10)
2633 .allPrivileges().exceptUserMode();
2634 InitReg(MISCREG_DBGBXVR11)
2635 .allPrivileges().exceptUserMode();
2636 InitReg(MISCREG_DBGBXVR12)
2637 .allPrivileges().exceptUserMode();
2638 InitReg(MISCREG_DBGBXVR13)
2639 .allPrivileges().exceptUserMode();
2640 InitReg(MISCREG_DBGBXVR14)
2641 .allPrivileges().exceptUserMode();
2642 InitReg(MISCREG_DBGBXVR15)
2643 .allPrivileges().exceptUserMode();
2644 InitReg(MISCREG_DBGOSLAR)
2645 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2646 InitReg(MISCREG_DBGOSLSR)
2647 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2648 InitReg(MISCREG_DBGOSDLR)
2649 .unimplemented()
2650 .warnNotFail()
2651 .allPrivileges();
2652 InitReg(MISCREG_DBGPRCR)
2653 .unimplemented()
2654 .allPrivileges();
2655 InitReg(MISCREG_DBGDSAR)
2656 .unimplemented()
2657 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2658 InitReg(MISCREG_DBGCLAIMSET)
2659 .unimplemented()
2660 .allPrivileges();
2661 InitReg(MISCREG_DBGCLAIMCLR)
2662 .unimplemented()
2663 .allPrivileges();
2664 InitReg(MISCREG_DBGAUTHSTATUS)
2665 .unimplemented()
2666 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2667 InitReg(MISCREG_DBGDEVID2)
2668 .unimplemented()
2669 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2670 InitReg(MISCREG_DBGDEVID1)
2671 .unimplemented()
2672 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2673 InitReg(MISCREG_DBGDEVID0)
2674 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2675 InitReg(MISCREG_TEECR)
2676 .unimplemented()
2677 .allPrivileges();
2678 InitReg(MISCREG_JIDR)
2679 .raz() // Jazelle trivial implementation, RAZ/WI
2680 .allPrivileges();
2681 InitReg(MISCREG_TEEHBR)
2682 .allPrivileges();
2683 InitReg(MISCREG_JOSCR)
2684 .raz() // Jazelle trivial implementation, RAZ/WI
2685 .allPrivileges();
2686 InitReg(MISCREG_JMCR)
2687 .raz() // Jazelle trivial implementation, RAZ/WI
2688 .allPrivileges();
2689
2690 // AArch32 CP15 registers
2691 InitReg(MISCREG_MIDR)
2692 .reset(midr)
2693 .allPrivileges().exceptUserMode().writes(0);
2694 InitReg(MISCREG_CTR)
2695 .reset([system=p.system](){
2696 //all caches have the same line size in gem5
2697 //4 byte words in ARM
2698 unsigned line_size_words =
2699 system->cacheLineSize() / 4;
2700 unsigned log2_line_size_words = 0;
2701
2702 while (line_size_words >>= 1) {
2703 ++log2_line_size_words;
2704 }
2705
2706 CTR ctr = 0;
2707 //log2 of minimun i-cache line size (words)
2708 ctr.iCacheLineSize = log2_line_size_words;
2709 //b11 - gem5 uses pipt
2710 ctr.l1IndexPolicy = 0x3;
2711 //log2 of minimum d-cache line size (words)
2712 ctr.dCacheLineSize = log2_line_size_words;
2713 //log2 of max reservation size (words)
2714 ctr.erg = log2_line_size_words;
2715 //log2 of max writeback size (words)
2716 ctr.cwg = log2_line_size_words;
2717 //b100 - gem5 format is ARMv7
2718 ctr.format = 0x4;
2719
2720 return ctr;
2721 }())
2722 .unserialize(0)
2723 .allPrivileges().exceptUserMode().writes(0);
2724 InitReg(MISCREG_TCMTR)
2725 .raz() // No TCM's
2726 .allPrivileges().exceptUserMode().writes(0);
2727 InitReg(MISCREG_TLBTR)
2728 .reset(1) // Separate Instruction and Data TLBs
2729 .allPrivileges().exceptUserMode().writes(0);
2730 InitReg(MISCREG_MPIDR)
2731 .reset(0x80000000)
2732 .allPrivileges().exceptUserMode().writes(0);
2733 InitReg(MISCREG_REVIDR)
2734 .unimplemented()
2735 .warnNotFail()
2736 .allPrivileges().exceptUserMode().writes(0);
2737 InitReg(MISCREG_ID_PFR0)
2738 .reset(0x00000031) // !ThumbEE | !Jazelle | Thumb | ARM
2739 .allPrivileges().exceptUserMode().writes(0);
2740 InitReg(MISCREG_ID_PFR1)
2741 .reset([release=release,system=system](){
2742 // Timer | Virti | !M Profile | TrustZone | ARMv4
2743 bool have_timer = (system && system->getGenericTimer() != nullptr);
2744 return 0x00000001 |
2745 (release->has(ArmExtension::SECURITY) ?
2746 0x00000010 : 0x0) |
2747 (release->has(ArmExtension::VIRTUALIZATION) ?
2748 0x00001000 : 0x0) |
2749 (have_timer ? 0x00010000 : 0x0);
2750 }())
2751 .unserialize(0)
2752 .allPrivileges().exceptUserMode().writes(0);
2753 InitReg(MISCREG_ID_DFR0)
2754 .reset(p.pmu ? 0x03000000 : 0)
2755 .allPrivileges().exceptUserMode().writes(0);
2756 InitReg(MISCREG_ID_AFR0)
2757 .allPrivileges().exceptUserMode().writes(0);
2758 InitReg(MISCREG_ID_MMFR0)
2759 .reset([p,release=release](){
2760 RegVal mmfr0 = p.id_mmfr0;
2761 if (release->has(ArmExtension::LPAE))
2762 mmfr0 = (mmfr0 & ~0xf) | 0x5;
2763 return mmfr0;
2764 }())
2765 .allPrivileges().exceptUserMode().writes(0);
2766 InitReg(MISCREG_ID_MMFR1)
2767 .reset(p.id_mmfr1)
2768 .allPrivileges().exceptUserMode().writes(0);
2769 InitReg(MISCREG_ID_MMFR2)
2770 .reset(p.id_mmfr2)
2771 .allPrivileges().exceptUserMode().writes(0);
2772 InitReg(MISCREG_ID_MMFR3)
2773 .reset(p.id_mmfr3)
2774 .allPrivileges().exceptUserMode().writes(0);
2775 InitReg(MISCREG_ID_MMFR4)
2776 .reset(p.id_mmfr4)
2777 .allPrivileges().exceptUserMode().writes(0);
2778 InitReg(MISCREG_ID_ISAR0)
2779 .reset(p.id_isar0)
2780 .allPrivileges().exceptUserMode().writes(0);
2781 InitReg(MISCREG_ID_ISAR1)
2782 .reset(p.id_isar1)
2783 .allPrivileges().exceptUserMode().writes(0);
2784 InitReg(MISCREG_ID_ISAR2)
2785 .reset(p.id_isar2)
2786 .allPrivileges().exceptUserMode().writes(0);
2787 InitReg(MISCREG_ID_ISAR3)
2788 .reset(p.id_isar3)
2789 .allPrivileges().exceptUserMode().writes(0);
2790 InitReg(MISCREG_ID_ISAR4)
2791 .reset(p.id_isar4)
2792 .allPrivileges().exceptUserMode().writes(0);
2793 InitReg(MISCREG_ID_ISAR5)
2794 .reset([p,release=release] () {
2795 ISAR5 isar5 = p.id_isar5;
2796 if (release->has(ArmExtension::CRYPTO)) {
2797 isar5.crc32 = 1;
2798 isar5.sha2 = 1;
2799 isar5.sha1 = 1;
2800 isar5.aes = 2;
2801 } else {
2802 isar5.crc32 = 0;
2803 isar5.sha2 = 0;
2804 isar5.sha1 = 0;
2805 isar5.aes = 0;
2806 }
2807 isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
2808 isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
2809 return isar5;
2810 }())
2811 .allPrivileges().exceptUserMode().writes(0);
2812 InitReg(MISCREG_ID_ISAR6)
2813 .reset([p,release=release] () {
2814 ISAR6 isar6 = p.id_isar6;
2815 isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
2816 return isar6;
2817 }())
2818 .allPrivileges().exceptUserMode().writes(0);
2819 InitReg(MISCREG_CCSIDR)
2820 .allPrivileges().exceptUserMode().writes(0);
2821 InitReg(MISCREG_CLIDR)
2822 .allPrivileges().exceptUserMode().writes(0);
2823 InitReg(MISCREG_AIDR)
2824 .raz() // AUX ID set to 0
2825 .allPrivileges().exceptUserMode().writes(0);
2826 InitReg(MISCREG_CSSELR)
2827 .banked();
2828 InitReg(MISCREG_CSSELR_NS)
2829 .bankedChild()
2830 .privSecure(!aarch32EL3)
2831 .nonSecure().exceptUserMode();
2832 InitReg(MISCREG_CSSELR_S)
2833 .bankedChild()
2834 .secure().exceptUserMode();
2835 InitReg(MISCREG_VPIDR)
2836 .reset(midr)
2837 .hyp().monNonSecure();
2838 InitReg(MISCREG_VMPIDR)
2839 .res1(mask(31, 31))
2840 .hyp().monNonSecure();
2841 InitReg(MISCREG_SCTLR)
2842 .banked()
2843 // readMiscRegNoEffect() uses this metadata
2844 // despite using children (below) as backing store
2845 .res0(0x8d22c600)
2846 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
2847 | (LSMAOE ? 0 : 0x10)
2848 | (nTLSMD ? 0 : 0x8));
2849
2850 auto sctlr_reset = [aarch64=highestELIs64] ()
2851 {
2852 SCTLR sctlr = 0;
2853 if (aarch64) {
2854 sctlr.afe = 1;
2855 sctlr.tre = 1;
2856 sctlr.span = 1;
2857 sctlr.uwxn = 1;
2858 sctlr.ntwe = 1;
2859 sctlr.ntwi = 1;
2860 sctlr.cp15ben = 1;
2861 sctlr.sa0 = 1;
2862 } else {
2863 sctlr.u = 1;
2864 sctlr.xp = 1;
2865 sctlr.uci = 1;
2866 sctlr.dze = 1;
2867 sctlr.rao2 = 1;
2868 sctlr.rao3 = 1;
2869 sctlr.rao4 = 0xf;
2870 }
2871 return sctlr;
2872 }();
2873 InitReg(MISCREG_SCTLR_NS)
2874 .reset(sctlr_reset)
2875 .bankedChild()
2876 .privSecure(!aarch32EL3)
2877 .nonSecure().exceptUserMode();
2878 InitReg(MISCREG_SCTLR_S)
2879 .reset(sctlr_reset)
2880 .bankedChild()
2881 .secure().exceptUserMode();
2882 InitReg(MISCREG_ACTLR)
2883 .banked();
2884 InitReg(MISCREG_ACTLR_NS)
2885 .bankedChild()
2886 .privSecure(!aarch32EL3)
2887 .nonSecure().exceptUserMode();
2888 InitReg(MISCREG_ACTLR_S)
2889 .bankedChild()
2890 .secure().exceptUserMode();
2891 InitReg(MISCREG_CPACR)
2892 .allPrivileges().exceptUserMode();
2893 InitReg(MISCREG_SDCR)
2894 .mon();
2895 InitReg(MISCREG_SCR)
2896 .reset(release->has(ArmExtension::SECURITY) ? 0 : 1)
2897 .mon().secure().exceptUserMode()
2898 .res0(0xff40) // [31:16], [6]
2899 .res1(0x0030); // [5:4]
2900 InitReg(MISCREG_SDER)
2901 .mon();
2902 InitReg(MISCREG_NSACR)
2903 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2904 InitReg(MISCREG_HSCTLR)
2905 .reset(0x30c50830)
2906 .hyp().monNonSecure()
2907 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2908 | (IESB ? 0 : 0x200000)
2909 | (EnDA ? 0 : 0x8000000)
2910 | (EnIB ? 0 : 0x40000000)
2911 | (EnIA ? 0 : 0x80000000))
2912 .res1(0x30c50830);
2913 InitReg(MISCREG_HACTLR)
2914 .hyp().monNonSecure();
2915 InitReg(MISCREG_HCR)
2916 .hyp().monNonSecure()
2917 .res0(release->has(ArmExtension::VIRTUALIZATION) ?
2918 0x90000000 : mask(31, 0));
2919 InitReg(MISCREG_HCR2)
2920 .hyp().monNonSecure()
2921 .res0(release->has(ArmExtension::VIRTUALIZATION) ?
2922 0xffa9ff8c : mask(31, 0));
2923 InitReg(MISCREG_HDCR)
2924 .hyp().monNonSecure();
2925 InitReg(MISCREG_HCPTR)
2926 .res0(mask(29, 21) | mask(19, 16) | mask(14, 14))
2927 .res1(mask(13, 12) | mask(9, 0))
2928 .hyp().monNonSecure();
2929 InitReg(MISCREG_HSTR)
2930 .hyp().monNonSecure();
2931 InitReg(MISCREG_HACR)
2932 .unimplemented()
2933 .warnNotFail()
2934 .hyp().monNonSecure();
2935 InitReg(MISCREG_TTBR0)
2936 .banked();
2937 InitReg(MISCREG_TTBR0_NS)
2938 .bankedChild()
2939 .privSecure(!aarch32EL3)
2940 .nonSecure().exceptUserMode();
2941 InitReg(MISCREG_TTBR0_S)
2942 .bankedChild()
2943 .secure().exceptUserMode();
2944 InitReg(MISCREG_TTBR1)
2945 .banked();
2946 InitReg(MISCREG_TTBR1_NS)
2947 .bankedChild()
2948 .privSecure(!aarch32EL3)
2949 .nonSecure().exceptUserMode();
2950 InitReg(MISCREG_TTBR1_S)
2951 .bankedChild()
2952 .secure().exceptUserMode();
2953 InitReg(MISCREG_TTBCR)
2954 .banked();
2955 InitReg(MISCREG_TTBCR_NS)
2956 .bankedChild()
2957 .privSecure(!aarch32EL3)
2958 .nonSecure().exceptUserMode();
2959 InitReg(MISCREG_TTBCR_S)
2960 .bankedChild()
2961 .secure().exceptUserMode();
2962 InitReg(MISCREG_HTCR)
2963 .hyp().monNonSecure();
2964 InitReg(MISCREG_VTCR)
2965 .hyp().monNonSecure();
2966 InitReg(MISCREG_DACR)
2967 .banked();
2968 InitReg(MISCREG_DACR_NS)
2969 .bankedChild()
2970 .privSecure(!aarch32EL3)
2971 .nonSecure().exceptUserMode();
2972 InitReg(MISCREG_DACR_S)
2973 .bankedChild()
2974 .secure().exceptUserMode();
2975 InitReg(MISCREG_DFSR)
2976 .banked()
2977 .res0(mask(31, 14) | mask(8, 8));
2978 InitReg(MISCREG_DFSR_NS)
2979 .bankedChild()
2980 .privSecure(!aarch32EL3)
2981 .nonSecure().exceptUserMode();
2982 InitReg(MISCREG_DFSR_S)
2983 .bankedChild()
2984 .secure().exceptUserMode();
2985 InitReg(MISCREG_IFSR)
2986 .banked()
2987 .res0(mask(31, 13) | mask(11, 11) | mask(8, 6));
2988 InitReg(MISCREG_IFSR_NS)
2989 .bankedChild()
2990 .privSecure(!aarch32EL3)
2991 .nonSecure().exceptUserMode();
2992 InitReg(MISCREG_IFSR_S)
2993 .bankedChild()
2994 .secure().exceptUserMode();
2995 InitReg(MISCREG_ADFSR)
2996 .unimplemented()
2997 .warnNotFail()
2998 .banked();
2999 InitReg(MISCREG_ADFSR_NS)
3000 .unimplemented()
3001 .warnNotFail()
3002 .bankedChild()
3003 .privSecure(!aarch32EL3)
3004 .nonSecure().exceptUserMode();
3005 InitReg(MISCREG_ADFSR_S)
3006 .unimplemented()
3007 .warnNotFail()
3008 .bankedChild()
3009 .secure().exceptUserMode();
3010 InitReg(MISCREG_AIFSR)
3011 .unimplemented()
3012 .warnNotFail()
3013 .banked();
3014 InitReg(MISCREG_AIFSR_NS)
3015 .unimplemented()
3016 .warnNotFail()
3017 .bankedChild()
3018 .privSecure(!aarch32EL3)
3019 .nonSecure().exceptUserMode();
3020 InitReg(MISCREG_AIFSR_S)
3021 .unimplemented()
3022 .warnNotFail()
3023 .bankedChild()
3024 .secure().exceptUserMode();
3025 InitReg(MISCREG_HADFSR)
3026 .hyp().monNonSecure();
3027 InitReg(MISCREG_HAIFSR)
3028 .hyp().monNonSecure();
3029 InitReg(MISCREG_HSR)
3030 .hyp().monNonSecure();
3031 InitReg(MISCREG_DFAR)
3032 .banked();
3033 InitReg(MISCREG_DFAR_NS)
3034 .bankedChild()
3035 .privSecure(!aarch32EL3)
3036 .nonSecure().exceptUserMode();
3037 InitReg(MISCREG_DFAR_S)
3038 .bankedChild()
3039 .secure().exceptUserMode();
3040 InitReg(MISCREG_IFAR)
3041 .banked();
3042 InitReg(MISCREG_IFAR_NS)
3043 .bankedChild()
3044 .privSecure(!aarch32EL3)
3045 .nonSecure().exceptUserMode();
3046 InitReg(MISCREG_IFAR_S)
3047 .bankedChild()
3048 .secure().exceptUserMode();
3049 InitReg(MISCREG_HDFAR)
3050 .hyp().monNonSecure();
3051 InitReg(MISCREG_HIFAR)
3052 .hyp().monNonSecure();
3053 InitReg(MISCREG_HPFAR)
3054 .hyp().monNonSecure();
3055 InitReg(MISCREG_ICIALLUIS)
3056 .unimplemented()
3057 .warnNotFail()
3058 .writes(1).exceptUserMode();
3059 InitReg(MISCREG_BPIALLIS)
3060 .unimplemented()
3061 .warnNotFail()
3062 .writes(1).exceptUserMode();
3063 InitReg(MISCREG_PAR)
3064 .banked();
3065 InitReg(MISCREG_PAR_NS)
3066 .bankedChild()
3067 .privSecure(!aarch32EL3)
3068 .nonSecure().exceptUserMode();
3069 InitReg(MISCREG_PAR_S)
3070 .bankedChild()
3071 .secure().exceptUserMode();
3072 InitReg(MISCREG_ICIALLU)
3073 .writes(1).exceptUserMode();
3074 InitReg(MISCREG_ICIMVAU)
3075 .unimplemented()
3076 .warnNotFail()
3077 .writes(1).exceptUserMode();
3078 InitReg(MISCREG_CP15ISB)
3079 .writes(1);
3080 InitReg(MISCREG_BPIALL)
3081 .unimplemented()
3082 .warnNotFail()
3083 .writes(1).exceptUserMode();
3084 InitReg(MISCREG_BPIMVA)
3085 .unimplemented()
3086 .warnNotFail()
3087 .writes(1).exceptUserMode();
3088 InitReg(MISCREG_DCIMVAC)
3089 .unimplemented()
3090 .warnNotFail()
3091 .writes(1).exceptUserMode();
3092 InitReg(MISCREG_DCISW)
3093 .unimplemented()
3094 .warnNotFail()
3095 .writes(1).exceptUserMode();
3096 InitReg(MISCREG_ATS1CPR)
3097 .writes(1).exceptUserMode();
3098 InitReg(MISCREG_ATS1CPW)
3099 .writes(1).exceptUserMode();
3100 InitReg(MISCREG_ATS1CUR)
3101 .writes(1).exceptUserMode();
3102 InitReg(MISCREG_ATS1CUW)
3103 .writes(1).exceptUserMode();
3104 InitReg(MISCREG_ATS12NSOPR)
3105 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3106 InitReg(MISCREG_ATS12NSOPW)
3107 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3108 InitReg(MISCREG_ATS12NSOUR)
3109 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3110 InitReg(MISCREG_ATS12NSOUW)
3111 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3112 InitReg(MISCREG_DCCMVAC)
3113 .writes(1).exceptUserMode();
3114 InitReg(MISCREG_DCCSW)
3115 .unimplemented()
3116 .warnNotFail()
3117 .writes(1).exceptUserMode();
3118 InitReg(MISCREG_CP15DSB)
3119 .writes(1);
3120 InitReg(MISCREG_CP15DMB)
3121 .writes(1);
3122 InitReg(MISCREG_DCCMVAU)
3123 .unimplemented()
3124 .warnNotFail()
3125 .writes(1).exceptUserMode();
3126 InitReg(MISCREG_DCCIMVAC)
3127 .unimplemented()
3128 .warnNotFail()
3129 .writes(1).exceptUserMode();
3130 InitReg(MISCREG_DCCISW)
3131 .unimplemented()
3132 .warnNotFail()
3133 .writes(1).exceptUserMode();
3134 InitReg(MISCREG_ATS1HR)
3135 .monNonSecureWrite().hypWrite();
3136 InitReg(MISCREG_ATS1HW)
3137 .monNonSecureWrite().hypWrite();
3138 InitReg(MISCREG_TLBIALLIS)
3139 .writes(1).exceptUserMode();
3140 InitReg(MISCREG_TLBIMVAIS)
3141 .writes(1).exceptUserMode();
3142 InitReg(MISCREG_TLBIASIDIS)
3143 .writes(1).exceptUserMode();
3144 InitReg(MISCREG_TLBIMVAAIS)
3145 .writes(1).exceptUserMode();
3146 InitReg(MISCREG_TLBIMVALIS)
3147 .writes(1).exceptUserMode();
3148 InitReg(MISCREG_TLBIMVAALIS)
3149 .writes(1).exceptUserMode();
3150 InitReg(MISCREG_ITLBIALL)
3151 .writes(1).exceptUserMode();
3152 InitReg(MISCREG_ITLBIMVA)
3153 .writes(1).exceptUserMode();
3154 InitReg(MISCREG_ITLBIASID)
3155 .writes(1).exceptUserMode();
3156 InitReg(MISCREG_DTLBIALL)
3157 .writes(1).exceptUserMode();
3158 InitReg(MISCREG_DTLBIMVA)
3159 .writes(1).exceptUserMode();
3160 InitReg(MISCREG_DTLBIASID)
3161 .writes(1).exceptUserMode();
3162 InitReg(MISCREG_TLBIALL)
3163 .writes(1).exceptUserMode();
3164 InitReg(MISCREG_TLBIMVA)
3165 .writes(1).exceptUserMode();
3166 InitReg(MISCREG_TLBIASID)
3167 .writes(1).exceptUserMode();
3168 InitReg(MISCREG_TLBIMVAA)
3169 .writes(1).exceptUserMode();
3170 InitReg(MISCREG_TLBIMVAL)
3171 .writes(1).exceptUserMode();
3172 InitReg(MISCREG_TLBIMVAAL)
3173 .writes(1).exceptUserMode();
3174 InitReg(MISCREG_TLBIIPAS2IS)
3175 .monNonSecureWrite().hypWrite();
3176 InitReg(MISCREG_TLBIIPAS2LIS)
3177 .monNonSecureWrite().hypWrite();
3178 InitReg(MISCREG_TLBIALLHIS)
3179 .monNonSecureWrite().hypWrite();
3180 InitReg(MISCREG_TLBIMVAHIS)
3181 .monNonSecureWrite().hypWrite();
3182 InitReg(MISCREG_TLBIALLNSNHIS)
3183 .monNonSecureWrite().hypWrite();
3184 InitReg(MISCREG_TLBIMVALHIS)
3185 .monNonSecureWrite().hypWrite();
3186 InitReg(MISCREG_TLBIIPAS2)
3187 .monNonSecureWrite().hypWrite();
3188 InitReg(MISCREG_TLBIIPAS2L)
3189 .monNonSecureWrite().hypWrite();
3190 InitReg(MISCREG_TLBIALLH)
3191 .monNonSecureWrite().hypWrite();
3192 InitReg(MISCREG_TLBIMVAH)
3193 .monNonSecureWrite().hypWrite();
3194 InitReg(MISCREG_TLBIALLNSNH)
3195 .monNonSecureWrite().hypWrite();
3196 InitReg(MISCREG_TLBIMVALH)
3197 .monNonSecureWrite().hypWrite();
3198 InitReg(MISCREG_PMCR)
3199 .allPrivileges();
3200 InitReg(MISCREG_PMCNTENSET)
3201 .allPrivileges();
3202 InitReg(MISCREG_PMCNTENCLR)
3203 .allPrivileges();
3204 InitReg(MISCREG_PMOVSR)
3205 .allPrivileges();
3206 InitReg(MISCREG_PMSWINC)
3207 .allPrivileges();
3208 InitReg(MISCREG_PMSELR)
3209 .allPrivileges();
3210 InitReg(MISCREG_PMCEID0)
3211 .allPrivileges();
3212 InitReg(MISCREG_PMCEID1)
3213 .allPrivileges();
3214 InitReg(MISCREG_PMCCNTR)
3215 .allPrivileges();
3216 InitReg(MISCREG_PMXEVTYPER)
3217 .allPrivileges();
3218 InitReg(MISCREG_PMCCFILTR)
3219 .allPrivileges();
3220 InitReg(MISCREG_PMXEVCNTR)
3221 .allPrivileges();
3222 InitReg(MISCREG_PMUSERENR)
3223 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3224 InitReg(MISCREG_PMINTENSET)
3225 .allPrivileges().exceptUserMode();
3226 InitReg(MISCREG_PMINTENCLR)
3227 .allPrivileges().exceptUserMode();
3228 InitReg(MISCREG_PMOVSSET)
3229 .unimplemented()
3230 .allPrivileges();
3231 InitReg(MISCREG_L2CTLR)
3232 .allPrivileges().exceptUserMode();
3233 InitReg(MISCREG_L2ECTLR)
3234 .unimplemented()
3235 .allPrivileges().exceptUserMode();
3236 InitReg(MISCREG_PRRR)
3237 .banked();
3238 InitReg(MISCREG_PRRR_NS)
3239 .bankedChild()
3240 .reset(
3241 (1 << 19) | // 19
3242 (0 << 18) | // 18
3243 (0 << 17) | // 17
3244 (1 << 16) | // 16
3245 (2 << 14) | // 15:14
3246 (0 << 12) | // 13:12
3247 (2 << 10) | // 11:10
3248 (2 << 8) | // 9:8
3249 (2 << 6) | // 7:6
3250 (2 << 4) | // 5:4
3251 (1 << 2) | // 3:2
3252 0)
3253 .privSecure(!aarch32EL3)
3254 .nonSecure().exceptUserMode();
3255 InitReg(MISCREG_PRRR_S)
3256 .bankedChild()
3257 .secure().exceptUserMode();
3258 InitReg(MISCREG_MAIR0)
3259 .banked();
3260 InitReg(MISCREG_MAIR0_NS)
3261 .bankedChild()
3262 .privSecure(!aarch32EL3)
3263 .nonSecure().exceptUserMode();
3264 InitReg(MISCREG_MAIR0_S)
3265 .bankedChild()
3266 .secure().exceptUserMode();
3267 InitReg(MISCREG_NMRR)
3268 .banked();
3269 InitReg(MISCREG_NMRR_NS)
3270 .bankedChild()
3271 .reset(
3272 (1 << 30) | // 31:30
3273 (0 << 26) | // 27:26
3274 (0 << 24) | // 25:24
3275 (3 << 22) | // 23:22
3276 (2 << 20) | // 21:20
3277 (0 << 18) | // 19:18
3278 (0 << 16) | // 17:16
3279 (1 << 14) | // 15:14
3280 (0 << 12) | // 13:12
3281 (2 << 10) | // 11:10
3282 (0 << 8) | // 9:8
3283 (3 << 6) | // 7:6
3284 (2 << 4) | // 5:4
3285 (0 << 2) | // 3:2
3286 0)
3287 .privSecure(!aarch32EL3)
3288 .nonSecure().exceptUserMode();
3289 InitReg(MISCREG_NMRR_S)
3290 .bankedChild()
3291 .secure().exceptUserMode();
3292 InitReg(MISCREG_MAIR1)
3293 .banked();
3294 InitReg(MISCREG_MAIR1_NS)
3295 .bankedChild()
3296 .privSecure(!aarch32EL3)
3297 .nonSecure().exceptUserMode();
3298 InitReg(MISCREG_MAIR1_S)
3299 .bankedChild()
3300 .secure().exceptUserMode();
3301 InitReg(MISCREG_AMAIR0)
3302 .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
3303 .banked();
3304 InitReg(MISCREG_AMAIR0_NS)
3305 .bankedChild()
3306 .privSecure(!aarch32EL3)
3307 .nonSecure().exceptUserMode();
3308 InitReg(MISCREG_AMAIR0_S)
3309 .bankedChild()
3310 .secure().exceptUserMode();
3311 InitReg(MISCREG_AMAIR1)
3312 .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
3313 .banked();
3314 InitReg(MISCREG_AMAIR1_NS)
3315 .bankedChild()
3316 .privSecure(!aarch32EL3)
3317 .nonSecure().exceptUserMode();
3318 InitReg(MISCREG_AMAIR1_S)
3319 .bankedChild()
3320 .secure().exceptUserMode();
3321 InitReg(MISCREG_HMAIR0)
3322 .hyp().monNonSecure();
3323 InitReg(MISCREG_HMAIR1)
3324 .hyp().monNonSecure();
3325 InitReg(MISCREG_HAMAIR0)
3326 .unimplemented()
3327 .warnNotFail()
3328 .hyp().monNonSecure();
3329 InitReg(MISCREG_HAMAIR1)
3330 .unimplemented()
3331 .warnNotFail()
3332 .hyp().monNonSecure();
3333 InitReg(MISCREG_VBAR)
3334 .banked();
3335 InitReg(MISCREG_VBAR_NS)
3336 .bankedChild()
3337 .privSecure(!aarch32EL3)
3338 .nonSecure().exceptUserMode();
3339 InitReg(MISCREG_VBAR_S)
3340 .bankedChild()
3341 .secure().exceptUserMode();
3342 InitReg(MISCREG_MVBAR)
3343 .reset(FullSystem ? system->resetAddr() : 0)
3344 .mon().secure()
3345 .hypRead(FullSystem && system->highestEL() == EL2)
3346 .privRead(FullSystem && system->highestEL() == EL1)
3347 .exceptUserMode();
3348 InitReg(MISCREG_RMR)
3349 .unimplemented()
3350 .mon().secure().exceptUserMode();
3351 InitReg(MISCREG_ISR)
3352 .allPrivileges().exceptUserMode().writes(0);
3353 InitReg(MISCREG_HVBAR)
3354 .hyp().monNonSecure()
3355 .res0(0x1f);
3356 InitReg(MISCREG_FCSEIDR)
3357 .unimplemented()
3358 .warnNotFail()
3359 .allPrivileges().exceptUserMode();
3360 InitReg(MISCREG_CONTEXTIDR)
3361 .banked();
3362 InitReg(MISCREG_CONTEXTIDR_NS)
3363 .bankedChild()
3364 .privSecure(!aarch32EL3)
3365 .nonSecure().exceptUserMode();
3366 InitReg(MISCREG_CONTEXTIDR_S)
3367 .bankedChild()
3368 .secure().exceptUserMode();
3369 InitReg(MISCREG_TPIDRURW)
3370 .banked();
3371 InitReg(MISCREG_TPIDRURW_NS)
3372 .bankedChild()
3373 .allPrivileges()
3374 .privSecure(!aarch32EL3)
3375 .monSecure(0);
3376 InitReg(MISCREG_TPIDRURW_S)
3377 .bankedChild()
3378 .secure();
3379 InitReg(MISCREG_TPIDRURO)
3380 .banked();
3381 InitReg(MISCREG_TPIDRURO_NS)
3382 .bankedChild()
3383 .allPrivileges()
3384 .userNonSecureWrite(0).userSecureRead(1)
3385 .privSecure(!aarch32EL3)
3386 .monSecure(0);
3387 InitReg(MISCREG_TPIDRURO_S)
3388 .bankedChild()
3389 .secure().userSecureWrite(0);
3390 InitReg(MISCREG_TPIDRPRW)
3391 .banked();
3392 InitReg(MISCREG_TPIDRPRW_NS)
3393 .bankedChild()
3394 .nonSecure().exceptUserMode()
3395 .privSecure(!aarch32EL3);
3396 InitReg(MISCREG_TPIDRPRW_S)
3397 .bankedChild()
3398 .secure().exceptUserMode();
3399 InitReg(MISCREG_HTPIDR)
3400 .hyp().monNonSecure();
3401 // BEGIN Generic Timer (AArch32)
3402 InitReg(MISCREG_CNTFRQ)
3403 .reads(1)
3404 .highest(system)
3405 .privSecureWrite(aarch32EL3);
3406 InitReg(MISCREG_CNTPCT)
3407 .unverifiable()
3408 .reads(1);
3409 InitReg(MISCREG_CNTVCT)
3410 .unverifiable()
3411 .reads(1);
3412 InitReg(MISCREG_CNTP_CTL)
3413 .banked();
3414 InitReg(MISCREG_CNTP_CTL_NS)
3415 .bankedChild()
3416 .nonSecure()
3417 .privSecure(!aarch32EL3)
3418 .userSecureRead(!aarch32EL3)
3419 .userSecureWrite(!aarch32EL3)
3420 .res0(0xfffffff8);
3421 InitReg(MISCREG_CNTP_CTL_S)
3422 .bankedChild()
3423 .secure()
3424 .privSecure(aarch32EL3)
3425 .res0(0xfffffff8);
3426 InitReg(MISCREG_CNTP_CVAL)
3427 .banked();
3428 InitReg(MISCREG_CNTP_CVAL_NS)
3429 .bankedChild()
3430 .nonSecure()
3431 .privSecure(!aarch32EL3)
3432 .userSecureRead(!aarch32EL3)
3433 .userSecureWrite(!aarch32EL3);
3434 InitReg(MISCREG_CNTP_CVAL_S)
3435 .bankedChild()
3436 .secure()
3437 .privSecure(aarch32EL3);
3438 InitReg(MISCREG_CNTP_TVAL)
3439 .banked();
3440 InitReg(MISCREG_CNTP_TVAL_NS)
3441 .bankedChild()
3442 .nonSecure()
3443 .privSecure(!aarch32EL3)
3444 .userSecureRead(!aarch32EL3)
3445 .userSecureWrite(!aarch32EL3);
3446 InitReg(MISCREG_CNTP_TVAL_S)
3447 .bankedChild()
3448 .secure()
3449 .privSecure(aarch32EL3);
3450 InitReg(MISCREG_CNTV_CTL)
3451 .allPrivileges()
3452 .res0(0xfffffff8);
3453 InitReg(MISCREG_CNTV_CVAL)
3454 .allPrivileges();
3455 InitReg(MISCREG_CNTV_TVAL)
3456 .allPrivileges();
3457 InitReg(MISCREG_CNTKCTL)
3458 .allPrivileges()
3459 .exceptUserMode()
3460 .res0(0xfffdfc00);
3461 InitReg(MISCREG_CNTHCTL)
3462 .monNonSecure()
3463 .hyp()
3464 .res0(0xfffdff00);
3465 InitReg(MISCREG_CNTHP_CTL)
3466 .monNonSecure()
3467 .hyp()
3468 .res0(0xfffffff8);
3469 InitReg(MISCREG_CNTHP_CVAL)
3470 .monNonSecure()
3471 .hyp();
3472 InitReg(MISCREG_CNTHP_TVAL)
3473 .monNonSecure()
3474 .hyp();
3475 InitReg(MISCREG_CNTVOFF)
3476 .monNonSecure()
3477 .hyp();
3478 // END Generic Timer (AArch32)
3479 InitReg(MISCREG_IL1DATA0)
3480 .unimplemented()
3481 .allPrivileges().exceptUserMode();
3482 InitReg(MISCREG_IL1DATA1)
3483 .unimplemented()
3484 .allPrivileges().exceptUserMode();
3485 InitReg(MISCREG_IL1DATA2)
3486 .unimplemented()
3487 .allPrivileges().exceptUserMode();
3488 InitReg(MISCREG_IL1DATA3)
3489 .unimplemented()
3490 .allPrivileges().exceptUserMode();
3491 InitReg(MISCREG_DL1DATA0)
3492 .unimplemented()
3493 .allPrivileges().exceptUserMode();
3494 InitReg(MISCREG_DL1DATA1)
3495 .unimplemented()
3496 .allPrivileges().exceptUserMode();
3497 InitReg(MISCREG_DL1DATA2)
3498 .unimplemented()
3499 .allPrivileges().exceptUserMode();
3500 InitReg(MISCREG_DL1DATA3)
3501 .unimplemented()
3502 .allPrivileges().exceptUserMode();
3503 InitReg(MISCREG_DL1DATA4)
3504 .unimplemented()
3505 .allPrivileges().exceptUserMode();
3506 InitReg(MISCREG_RAMINDEX)
3507 .unimplemented()
3508 .writes(1).exceptUserMode();
3509 InitReg(MISCREG_L2ACTLR)
3510 .unimplemented()
3511 .allPrivileges().exceptUserMode();
3512 InitReg(MISCREG_CBAR)
3513 .unimplemented()
3514 .allPrivileges().exceptUserMode().writes(0);
3515 InitReg(MISCREG_HTTBR)
3516 .hyp().monNonSecure();
3517 InitReg(MISCREG_VTTBR)
3518 .hyp().monNonSecure();
3519 InitReg(MISCREG_CPUMERRSR)
3520 .unimplemented()
3521 .allPrivileges().exceptUserMode();
3522 InitReg(MISCREG_L2MERRSR)
3523 .unimplemented()
3524 .warnNotFail()
3525 .allPrivileges().exceptUserMode();
3526
3527 // AArch64 registers (Op0=2);
3528 InitReg(MISCREG_MDCCINT_EL1)
3529 .fault(EL1, faultMdccsrEL1)
3530 .fault(EL2, faultMdccsrEL2)
3531 .allPrivileges();
3532 InitReg(MISCREG_OSDTRRX_EL1)
3533 .allPrivileges()
3534 .mapsTo(MISCREG_DBGDTRRXext);
3535 InitReg(MISCREG_MDSCR_EL1)
3536 .allPrivileges()
3537 .mapsTo(MISCREG_DBGDSCRext);
3538 InitReg(MISCREG_OSDTRTX_EL1)
3539 .allPrivileges()
3540 .mapsTo(MISCREG_DBGDTRTXext);
3541 InitReg(MISCREG_OSECCR_EL1)
3542 .allPrivileges()
3543 .mapsTo(MISCREG_DBGOSECCR);
3544 InitReg(MISCREG_DBGBVR0_EL1)
3545 .allPrivileges().exceptUserMode()
3546 .fault(EL1, faultDebugEL1)
3547 .fault(EL2, faultDebugEL2)
3548 .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
3549 InitReg(MISCREG_DBGBVR1_EL1)
3550 .allPrivileges().exceptUserMode()
3551 .fault(EL1, faultDebugEL1)
3552 .fault(EL2, faultDebugEL2)
3553 .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
3554 InitReg(MISCREG_DBGBVR2_EL1)
3555 .allPrivileges().exceptUserMode()
3556 .fault(EL1, faultDebugEL1)
3557 .fault(EL2, faultDebugEL2)
3558 .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
3559 InitReg(MISCREG_DBGBVR3_EL1)
3560 .allPrivileges().exceptUserMode()
3561 .fault(EL1, faultDebugEL1)
3562 .fault(EL2, faultDebugEL2)
3563 .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
3564 InitReg(MISCREG_DBGBVR4_EL1)
3565 .allPrivileges().exceptUserMode()
3566 .fault(EL1, faultDebugEL1)
3567 .fault(EL2, faultDebugEL2)
3568 .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
3569 InitReg(MISCREG_DBGBVR5_EL1)
3570 .allPrivileges().exceptUserMode()
3571 .fault(EL1, faultDebugEL1)
3572 .fault(EL2, faultDebugEL2)
3573 .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
3574 InitReg(MISCREG_DBGBVR6_EL1)
3575 .allPrivileges().exceptUserMode()
3576 .fault(EL1, faultDebugEL1)
3577 .fault(EL2, faultDebugEL2)
3578 .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
3579 InitReg(MISCREG_DBGBVR7_EL1)
3580 .allPrivileges().exceptUserMode()
3581 .fault(EL1, faultDebugEL1)
3582 .fault(EL2, faultDebugEL2)
3583 .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
3584 InitReg(MISCREG_DBGBVR8_EL1)
3585 .allPrivileges().exceptUserMode()
3586 .fault(EL1, faultDebugEL1)
3587 .fault(EL2, faultDebugEL2)
3588 .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
3589 InitReg(MISCREG_DBGBVR9_EL1)
3590 .allPrivileges().exceptUserMode()
3591 .fault(EL1, faultDebugEL1)
3592 .fault(EL2, faultDebugEL2)
3593 .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
3594 InitReg(MISCREG_DBGBVR10_EL1)
3595 .allPrivileges().exceptUserMode()
3596 .fault(EL1, faultDebugEL1)
3597 .fault(EL2, faultDebugEL2)
3598 .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
3599 InitReg(MISCREG_DBGBVR11_EL1)
3600 .allPrivileges().exceptUserMode()
3601 .fault(EL1, faultDebugEL1)
3602 .fault(EL2, faultDebugEL2)
3603 .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
3604 InitReg(MISCREG_DBGBVR12_EL1)
3605 .allPrivileges().exceptUserMode()
3606 .fault(EL1, faultDebugEL1)
3607 .fault(EL2, faultDebugEL2)
3608 .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
3609 InitReg(MISCREG_DBGBVR13_EL1)
3610 .allPrivileges().exceptUserMode()
3611 .fault(EL1, faultDebugEL1)
3612 .fault(EL2, faultDebugEL2)
3613 .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
3614 InitReg(MISCREG_DBGBVR14_EL1)
3615 .allPrivileges().exceptUserMode()
3616 .fault(EL1, faultDebugEL1)
3617 .fault(EL2, faultDebugEL2)
3618 .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
3619 InitReg(MISCREG_DBGBVR15_EL1)
3620 .allPrivileges().exceptUserMode()
3621 .fault(EL1, faultDebugEL1)
3622 .fault(EL2, faultDebugEL2)
3623 .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
3624 InitReg(MISCREG_DBGBCR0_EL1)
3625 .allPrivileges().exceptUserMode()
3626 .fault(EL1, faultDebugEL1)
3627 .fault(EL2, faultDebugEL2)
3628 .mapsTo(MISCREG_DBGBCR0);
3629 InitReg(MISCREG_DBGBCR1_EL1)
3630 .allPrivileges().exceptUserMode()
3631 .fault(EL1, faultDebugEL1)
3632 .fault(EL2, faultDebugEL2)
3633 .mapsTo(MISCREG_DBGBCR1);
3634 InitReg(MISCREG_DBGBCR2_EL1)
3635 .allPrivileges().exceptUserMode()
3636 .fault(EL1, faultDebugEL1)
3637 .fault(EL2, faultDebugEL2)
3638 .mapsTo(MISCREG_DBGBCR2);
3639 InitReg(MISCREG_DBGBCR3_EL1)
3640 .allPrivileges().exceptUserMode()
3641 .fault(EL1, faultDebugEL1)
3642 .fault(EL2, faultDebugEL2)
3643 .mapsTo(MISCREG_DBGBCR3);
3644 InitReg(MISCREG_DBGBCR4_EL1)
3645 .allPrivileges().exceptUserMode()
3646 .fault(EL1, faultDebugEL1)
3647 .fault(EL2, faultDebugEL2)
3648 .mapsTo(MISCREG_DBGBCR4);
3649 InitReg(MISCREG_DBGBCR5_EL1)
3650 .allPrivileges().exceptUserMode()
3651 .fault(EL1, faultDebugEL1)
3652 .fault(EL2, faultDebugEL2)
3653 .mapsTo(MISCREG_DBGBCR5);
3654 InitReg(MISCREG_DBGBCR6_EL1)
3655 .allPrivileges().exceptUserMode()
3656 .fault(EL1, faultDebugEL1)
3657 .fault(EL2, faultDebugEL2)
3658 .mapsTo(MISCREG_DBGBCR6);
3659 InitReg(MISCREG_DBGBCR7_EL1)
3660 .allPrivileges().exceptUserMode()
3661 .fault(EL1, faultDebugEL1)
3662 .fault(EL2, faultDebugEL2)
3663 .mapsTo(MISCREG_DBGBCR7);
3664 InitReg(MISCREG_DBGBCR8_EL1)
3665 .allPrivileges().exceptUserMode()
3666 .fault(EL1, faultDebugEL1)
3667 .fault(EL2, faultDebugEL2)
3668 .mapsTo(MISCREG_DBGBCR8);
3669 InitReg(MISCREG_DBGBCR9_EL1)
3670 .allPrivileges().exceptUserMode()
3671 .fault(EL1, faultDebugEL1)
3672 .fault(EL2, faultDebugEL2)
3673 .mapsTo(MISCREG_DBGBCR9);
3674 InitReg(MISCREG_DBGBCR10_EL1)
3675 .allPrivileges().exceptUserMode()
3676 .fault(EL1, faultDebugEL1)
3677 .fault(EL2, faultDebugEL2)
3678 .mapsTo(MISCREG_DBGBCR10);
3679 InitReg(MISCREG_DBGBCR11_EL1)
3680 .allPrivileges().exceptUserMode()
3681 .fault(EL1, faultDebugEL1)
3682 .fault(EL2, faultDebugEL2)
3683 .mapsTo(MISCREG_DBGBCR11);
3684 InitReg(MISCREG_DBGBCR12_EL1)
3685 .allPrivileges().exceptUserMode()
3686 .fault(EL1, faultDebugEL1)
3687 .fault(EL2, faultDebugEL2)
3688 .mapsTo(MISCREG_DBGBCR12);
3689 InitReg(MISCREG_DBGBCR13_EL1)
3690 .allPrivileges().exceptUserMode()
3691 .fault(EL1, faultDebugEL1)
3692 .fault(EL2, faultDebugEL2)
3693 .mapsTo(MISCREG_DBGBCR13);
3694 InitReg(MISCREG_DBGBCR14_EL1)
3695 .allPrivileges().exceptUserMode()
3696 .fault(EL1, faultDebugEL1)
3697 .fault(EL2, faultDebugEL2)
3698 .mapsTo(MISCREG_DBGBCR14);
3699 InitReg(MISCREG_DBGBCR15_EL1)
3700 .allPrivileges().exceptUserMode()
3701 .fault(EL1, faultDebugEL1)
3702 .fault(EL2, faultDebugEL2)
3703 .mapsTo(MISCREG_DBGBCR15);
3704 InitReg(MISCREG_DBGWVR0_EL1)
3705 .allPrivileges().exceptUserMode()
3706 .fault(EL1, faultDebugEL1)
3707 .fault(EL2, faultDebugEL2)
3708 .mapsTo(MISCREG_DBGWVR0);
3709 InitReg(MISCREG_DBGWVR1_EL1)
3710 .allPrivileges().exceptUserMode()
3711 .fault(EL1, faultDebugEL1)
3712 .fault(EL2, faultDebugEL2)
3713 .mapsTo(MISCREG_DBGWVR1);
3714 InitReg(MISCREG_DBGWVR2_EL1)
3715 .allPrivileges().exceptUserMode()
3716 .fault(EL1, faultDebugEL1)
3717 .fault(EL2, faultDebugEL2)
3718 .mapsTo(MISCREG_DBGWVR2);
3719 InitReg(MISCREG_DBGWVR3_EL1)
3720 .allPrivileges().exceptUserMode()
3721 .fault(EL1, faultDebugEL1)
3722 .fault(EL2, faultDebugEL2)
3723 .mapsTo(MISCREG_DBGWVR3);
3724 InitReg(MISCREG_DBGWVR4_EL1)
3725 .allPrivileges().exceptUserMode()
3726 .fault(EL1, faultDebugEL1)
3727 .fault(EL2, faultDebugEL2)
3728 .mapsTo(MISCREG_DBGWVR4);
3729 InitReg(MISCREG_DBGWVR5_EL1)
3730 .allPrivileges().exceptUserMode()
3731 .fault(EL1, faultDebugEL1)
3732 .fault(EL2, faultDebugEL2)
3733 .mapsTo(MISCREG_DBGWVR5);
3734 InitReg(MISCREG_DBGWVR6_EL1)
3735 .allPrivileges().exceptUserMode()
3736 .fault(EL1, faultDebugEL1)
3737 .fault(EL2, faultDebugEL2)
3738 .mapsTo(MISCREG_DBGWVR6);
3739 InitReg(MISCREG_DBGWVR7_EL1)
3740 .allPrivileges().exceptUserMode()
3741 .fault(EL1, faultDebugEL1)
3742 .fault(EL2, faultDebugEL2)
3743 .mapsTo(MISCREG_DBGWVR7);
3744 InitReg(MISCREG_DBGWVR8_EL1)
3745 .allPrivileges().exceptUserMode()
3746 .fault(EL1, faultDebugEL1)
3747 .fault(EL2, faultDebugEL2)
3748 .mapsTo(MISCREG_DBGWVR8);
3749 InitReg(MISCREG_DBGWVR9_EL1)
3750 .allPrivileges().exceptUserMode()
3751 .fault(EL1, faultDebugEL1)
3752 .fault(EL2, faultDebugEL2)
3753 .mapsTo(MISCREG_DBGWVR9);
3754 InitReg(MISCREG_DBGWVR10_EL1)
3755 .allPrivileges().exceptUserMode()
3756 .fault(EL1, faultDebugEL1)
3757 .fault(EL2, faultDebugEL2)
3758 .mapsTo(MISCREG_DBGWVR10);
3759 InitReg(MISCREG_DBGWVR11_EL1)
3760 .allPrivileges().exceptUserMode()
3761 .fault(EL1, faultDebugEL1)
3762 .fault(EL2, faultDebugEL2)
3763 .mapsTo(MISCREG_DBGWVR11);
3764 InitReg(MISCREG_DBGWVR12_EL1)
3765 .allPrivileges().exceptUserMode()
3766 .fault(EL1, faultDebugEL1)
3767 .fault(EL2, faultDebugEL2)
3768 .mapsTo(MISCREG_DBGWVR12);
3769 InitReg(MISCREG_DBGWVR13_EL1)
3770 .allPrivileges().exceptUserMode()
3771 .fault(EL1, faultDebugEL1)
3772 .fault(EL2, faultDebugEL2)
3773 .mapsTo(MISCREG_DBGWVR13);
3774 InitReg(MISCREG_DBGWVR14_EL1)
3775 .allPrivileges().exceptUserMode()
3776 .fault(EL1, faultDebugEL1)
3777 .fault(EL2, faultDebugEL2)
3778 .mapsTo(MISCREG_DBGWVR14);
3779 InitReg(MISCREG_DBGWVR15_EL1)
3780 .allPrivileges().exceptUserMode()
3781 .fault(EL1, faultDebugEL1)
3782 .fault(EL2, faultDebugEL2)
3783 .mapsTo(MISCREG_DBGWVR15);
3784 InitReg(MISCREG_DBGWCR0_EL1)
3785 .allPrivileges().exceptUserMode()
3786 .fault(EL1, faultDebugEL1)
3787 .fault(EL2, faultDebugEL2)
3788 .mapsTo(MISCREG_DBGWCR0);
3789 InitReg(MISCREG_DBGWCR1_EL1)
3790 .allPrivileges().exceptUserMode()
3791 .fault(EL1, faultDebugEL1)
3792 .fault(EL2, faultDebugEL2)
3793 .mapsTo(MISCREG_DBGWCR1);
3794 InitReg(MISCREG_DBGWCR2_EL1)
3795 .allPrivileges().exceptUserMode()
3796 .fault(EL1, faultDebugEL1)
3797 .fault(EL2, faultDebugEL2)
3798 .mapsTo(MISCREG_DBGWCR2);
3799 InitReg(MISCREG_DBGWCR3_EL1)
3800 .allPrivileges().exceptUserMode()
3801 .fault(EL1, faultDebugEL1)
3802 .fault(EL2, faultDebugEL2)
3803 .mapsTo(MISCREG_DBGWCR3);
3804 InitReg(MISCREG_DBGWCR4_EL1)
3805 .allPrivileges().exceptUserMode()
3806 .fault(EL1, faultDebugEL1)
3807 .fault(EL2, faultDebugEL2)
3808 .mapsTo(MISCREG_DBGWCR4);
3809 InitReg(MISCREG_DBGWCR5_EL1)
3810 .allPrivileges().exceptUserMode()
3811 .fault(EL1, faultDebugEL1)
3812 .fault(EL2, faultDebugEL2)
3813 .mapsTo(MISCREG_DBGWCR5);
3814 InitReg(MISCREG_DBGWCR6_EL1)
3815 .allPrivileges().exceptUserMode()
3816 .fault(EL1, faultDebugEL1)
3817 .fault(EL2, faultDebugEL2)
3818 .mapsTo(MISCREG_DBGWCR6);
3819 InitReg(MISCREG_DBGWCR7_EL1)
3820 .allPrivileges().exceptUserMode()
3821 .fault(EL1, faultDebugEL1)
3822 .fault(EL2, faultDebugEL2)
3823 .mapsTo(MISCREG_DBGWCR7);
3824 InitReg(MISCREG_DBGWCR8_EL1)
3825 .allPrivileges().exceptUserMode()
3826 .fault(EL1, faultDebugEL1)
3827 .fault(EL2, faultDebugEL2)
3828 .mapsTo(MISCREG_DBGWCR8);
3829 InitReg(MISCREG_DBGWCR9_EL1)
3830 .allPrivileges().exceptUserMode()
3831 .fault(EL1, faultDebugEL1)
3832 .fault(EL2, faultDebugEL2)
3833 .mapsTo(MISCREG_DBGWCR9);
3834 InitReg(MISCREG_DBGWCR10_EL1)
3835 .allPrivileges().exceptUserMode()
3836 .fault(EL1, faultDebugEL1)
3837 .fault(EL2, faultDebugEL2)
3838 .mapsTo(MISCREG_DBGWCR10);
3839 InitReg(MISCREG_DBGWCR11_EL1)
3840 .allPrivileges().exceptUserMode()
3841 .fault(EL1, faultDebugEL1)
3842 .fault(EL2, faultDebugEL2)
3843 .mapsTo(MISCREG_DBGWCR11);
3844 InitReg(MISCREG_DBGWCR12_EL1)
3845 .allPrivileges().exceptUserMode()
3846 .fault(EL1, faultDebugEL1)
3847 .fault(EL2, faultDebugEL2)
3848 .mapsTo(MISCREG_DBGWCR12);
3849 InitReg(MISCREG_DBGWCR13_EL1)
3850 .allPrivileges().exceptUserMode()
3851 .fault(EL1, faultDebugEL1)
3852 .fault(EL2, faultDebugEL2)
3853 .mapsTo(MISCREG_DBGWCR13);
3854 InitReg(MISCREG_DBGWCR14_EL1)
3855 .allPrivileges().exceptUserMode()
3856 .fault(EL1, faultDebugEL1)
3857 .fault(EL2, faultDebugEL2)
3858 .mapsTo(MISCREG_DBGWCR14);
3859 InitReg(MISCREG_DBGWCR15_EL1)
3860 .allPrivileges().exceptUserMode()
3861 .fault(EL1, faultDebugEL1)
3862 .fault(EL2, faultDebugEL2)
3863 .mapsTo(MISCREG_DBGWCR15);
3864 InitReg(MISCREG_MDCCSR_EL0)
3865 .allPrivileges().writes(0)
3866 .faultRead(EL0, faultMdccsrEL0)
3867 .faultRead(EL1, faultMdccsrEL1)
3868 .faultRead(EL2, faultMdccsrEL2)
3869 .mapsTo(MISCREG_DBGDSCRint);
3870 InitReg(MISCREG_MDDTR_EL0)
3871 .allPrivileges();
3872 InitReg(MISCREG_MDDTRTX_EL0)
3873 .allPrivileges();
3874 InitReg(MISCREG_MDDTRRX_EL0)
3875 .allPrivileges();
3876 InitReg(MISCREG_DBGVCR32_EL2)
3877 .hyp().mon()
3878 .fault(EL2, faultDebugEL2)
3879 .mapsTo(MISCREG_DBGVCR);
3880 InitReg(MISCREG_MDRAR_EL1)
3881 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3882 .mapsTo(MISCREG_DBGDRAR);
3883 InitReg(MISCREG_OSLAR_EL1)
3884 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3885 .mapsTo(MISCREG_DBGOSLAR);
3886 InitReg(MISCREG_OSLSR_EL1)
3887 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3888 .mapsTo(MISCREG_DBGOSLSR);
3889 InitReg(MISCREG_OSDLR_EL1)
3890 .allPrivileges()
3891 .mapsTo(MISCREG_DBGOSDLR);
3892 InitReg(MISCREG_DBGPRCR_EL1)
3893 .allPrivileges()
3894 .mapsTo(MISCREG_DBGPRCR);
3895 InitReg(MISCREG_DBGCLAIMSET_EL1)
3896 .allPrivileges()
3897 .mapsTo(MISCREG_DBGCLAIMSET);
3898 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3899 .allPrivileges()
3900 .mapsTo(MISCREG_DBGCLAIMCLR);
3901 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3902 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3903 .mapsTo(MISCREG_DBGAUTHSTATUS);
3904 InitReg(MISCREG_TEECR32_EL1);
3905 InitReg(MISCREG_TEEHBR32_EL1);
3906
3907 // AArch64 registers (Op0=1,3);
3908 InitReg(MISCREG_MIDR_EL1)
3909 .allPrivileges().exceptUserMode().writes(0)
3910 .faultRead(EL0, faultIdst)
3911 .mapsTo(MISCREG_MIDR);
3912 InitReg(MISCREG_MPIDR_EL1)
3913 .allPrivileges().exceptUserMode().writes(0)
3914 .faultRead(EL0, faultIdst)
3915 .mapsTo(MISCREG_MPIDR);
3916 InitReg(MISCREG_REVIDR_EL1)
3917 .faultRead(EL0, faultIdst)
3918 .faultRead(EL1, HCR_TRAP(tid1))
3919 .allPrivileges().exceptUserMode().writes(0);
3920 InitReg(MISCREG_ID_PFR0_EL1)
3921 .allPrivileges().exceptUserMode().writes(0)
3922 .faultRead(EL0, faultIdst)
3923 .faultRead(EL1, HCR_TRAP(tid3))
3924 .mapsTo(MISCREG_ID_PFR0);
3925 InitReg(MISCREG_ID_PFR1_EL1)
3926 .allPrivileges().exceptUserMode().writes(0)
3927 .faultRead(EL0, faultIdst)
3928 .faultRead(EL1, HCR_TRAP(tid3))
3929 .mapsTo(MISCREG_ID_PFR1);
3930 InitReg(MISCREG_ID_DFR0_EL1)
3931 .allPrivileges().exceptUserMode().writes(0)
3932 .faultRead(EL0, faultIdst)
3933 .faultRead(EL1, HCR_TRAP(tid3))
3934 .mapsTo(MISCREG_ID_DFR0);
3935 InitReg(MISCREG_ID_AFR0_EL1)
3936 .allPrivileges().exceptUserMode().writes(0)
3937 .faultRead(EL0, faultIdst)
3938 .faultRead(EL1, HCR_TRAP(tid3))
3939 .mapsTo(MISCREG_ID_AFR0);
3940 InitReg(MISCREG_ID_MMFR0_EL1)
3941 .allPrivileges().exceptUserMode().writes(0)
3942 .faultRead(EL0, faultIdst)
3943 .faultRead(EL1, HCR_TRAP(tid3))
3944 .mapsTo(MISCREG_ID_MMFR0);
3945 InitReg(MISCREG_ID_MMFR1_EL1)
3946 .allPrivileges().exceptUserMode().writes(0)
3947 .faultRead(EL0, faultIdst)
3948 .faultRead(EL1, HCR_TRAP(tid3))
3949 .mapsTo(MISCREG_ID_MMFR1);
3950 InitReg(MISCREG_ID_MMFR2_EL1)
3951 .allPrivileges().exceptUserMode().writes(0)
3952 .faultRead(EL0, faultIdst)
3953 .faultRead(EL1, HCR_TRAP(tid3))
3954 .mapsTo(MISCREG_ID_MMFR2);
3955 InitReg(MISCREG_ID_MMFR3_EL1)
3956 .allPrivileges().exceptUserMode().writes(0)
3957 .faultRead(EL0, faultIdst)
3958 .faultRead(EL1, HCR_TRAP(tid3))
3959 .mapsTo(MISCREG_ID_MMFR3);
3960 InitReg(MISCREG_ID_MMFR4_EL1)
3961 .allPrivileges().exceptUserMode().writes(0)
3962 .faultRead(EL0, faultIdst)
3963 .faultRead(EL1, HCR_TRAP(tid3))
3964 .mapsTo(MISCREG_ID_MMFR4);
3965 InitReg(MISCREG_ID_ISAR0_EL1)
3966 .allPrivileges().exceptUserMode().writes(0)
3967 .faultRead(EL0, faultIdst)
3968 .faultRead(EL1, HCR_TRAP(tid3))
3969 .mapsTo(MISCREG_ID_ISAR0);
3970 InitReg(MISCREG_ID_ISAR1_EL1)
3971 .allPrivileges().exceptUserMode().writes(0)
3972 .faultRead(EL0, faultIdst)
3973 .faultRead(EL1, HCR_TRAP(tid3))
3974 .mapsTo(MISCREG_ID_ISAR1);
3975 InitReg(MISCREG_ID_ISAR2_EL1)
3976 .allPrivileges().exceptUserMode().writes(0)
3977 .faultRead(EL0, faultIdst)
3978 .faultRead(EL1, HCR_TRAP(tid3))
3979 .mapsTo(MISCREG_ID_ISAR2);
3980 InitReg(MISCREG_ID_ISAR3_EL1)
3981 .allPrivileges().exceptUserMode().writes(0)
3982 .faultRead(EL0, faultIdst)
3983 .faultRead(EL1, HCR_TRAP(tid3))
3984 .mapsTo(MISCREG_ID_ISAR3);
3985 InitReg(MISCREG_ID_ISAR4_EL1)
3986 .allPrivileges().exceptUserMode().writes(0)
3987 .faultRead(EL0, faultIdst)
3988 .faultRead(EL1, HCR_TRAP(tid3))
3989 .mapsTo(MISCREG_ID_ISAR4);
3990 InitReg(MISCREG_ID_ISAR5_EL1)
3991 .allPrivileges().exceptUserMode().writes(0)
3992 .faultRead(EL0, faultIdst)
3993 .faultRead(EL1, HCR_TRAP(tid3))
3994 .mapsTo(MISCREG_ID_ISAR5);
3995 InitReg(MISCREG_ID_ISAR6_EL1)
3996 .allPrivileges().exceptUserMode().writes(0)
3997 .faultRead(EL0, faultIdst)
3998 .faultRead(EL1, HCR_TRAP(tid3))
3999 .mapsTo(MISCREG_ID_ISAR6);
4000 InitReg(MISCREG_MVFR0_EL1)
4001 .faultRead(EL0, faultIdst)
4002 .faultRead(EL1, HCR_TRAP(tid3))
4003 .allPrivileges().exceptUserMode().writes(0)
4004 .mapsTo(MISCREG_MVFR0);
4005 InitReg(MISCREG_MVFR1_EL1)
4006 .faultRead(EL0, faultIdst)
4007 .faultRead(EL1, HCR_TRAP(tid3))
4008 .allPrivileges().exceptUserMode().writes(0)
4009 .mapsTo(MISCREG_MVFR1);
4010 InitReg(MISCREG_MVFR2_EL1)
4011 .faultRead(EL0, faultIdst)
4012 .faultRead(EL1, HCR_TRAP(tid3))
4013 .allPrivileges().exceptUserMode().writes(0);
4014 InitReg(MISCREG_ID_AA64PFR0_EL1)
4015 .reset([this,release=release,tc=tc](){
4016 AA64PFR0 pfr0_el1 = 0;
4017 pfr0_el1.el0 = 0x2;
4018 pfr0_el1.el1 = 0x2;
4019 pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0;
4020 pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0;
4021 pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0;
4022 pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0;
4023 pfr0_el1.gic = FullSystem && getGICv3CPUInterface(tc) ? 0x1 : 0;
4024 return pfr0_el1;
4025 }())
4026 .unserialize(0)
4027 .faultRead(EL0, faultIdst)
4028 .faultRead(EL1, HCR_TRAP(tid3))
4029 .allPrivileges().writes(0);
4030 InitReg(MISCREG_ID_AA64PFR1_EL1)
4031 .reset(release->has(ArmExtension::FEAT_SME) ?
4032 0x1 << 24 : 0)
4033 .unserialize(0)
4034 .faultRead(EL0, faultIdst)
4035 .faultRead(EL1, HCR_TRAP(tid3))
4036 .allPrivileges().writes(0);
4037 InitReg(MISCREG_ID_AA64DFR0_EL1)
4038 .reset([p](){
4039 AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
4040 dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
4041 return dfr0_el1;
4042 }())
4043 .faultRead(EL0, faultIdst)
4044 .faultRead(EL1, HCR_TRAP(tid3))
4045 .allPrivileges().writes(0);
4046 InitReg(MISCREG_ID_AA64DFR1_EL1)
4047 .reset(p.id_aa64dfr1_el1)
4048 .faultRead(EL0, faultIdst)
4049 .faultRead(EL1, HCR_TRAP(tid3))
4050 .allPrivileges().writes(0);
4051 InitReg(MISCREG_ID_AA64AFR0_EL1)
4052 .reset(p.id_aa64afr0_el1)
4053 .faultRead(EL0, faultIdst)
4054 .faultRead(EL1, HCR_TRAP(tid3))
4055 .allPrivileges().writes(0);
4056 InitReg(MISCREG_ID_AA64AFR1_EL1)
4057 .reset(p.id_aa64afr1_el1)
4058 .faultRead(EL0, faultIdst)
4059 .faultRead(EL1, HCR_TRAP(tid3))
4060 .allPrivileges().writes(0);
4061 InitReg(MISCREG_ID_AA64ISAR0_EL1)
4062 .reset([p,release=release](){
4063 AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
4064 if (release->has(ArmExtension::CRYPTO)) {
4065 isar0_el1.crc32 = 1;
4066 isar0_el1.sha2 = 1;
4067 isar0_el1.sha1 = 1;
4068 isar0_el1.aes = 2;
4069 } else {
4070 isar0_el1.crc32 = 0;
4071 isar0_el1.sha2 = 0;
4072 isar0_el1.sha1 = 0;
4073 isar0_el1.aes = 0;
4074 }
4075 isar0_el1.dp = release->has(ArmExtension::FEAT_DOTPROD) ? 0x1 : 0x0;
4076 isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0;
4077 isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
4078 isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
4079 isar0_el1.tlb = release->has(ArmExtension::FEAT_TLBIOS) ? 0x1 : 0x0;
4080 isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
4081 0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
4082 0x1 : 0x0;
4083 isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 : 0x0;
4084 return isar0_el1;
4085 }())
4086 .faultRead(EL0, faultIdst)
4087 .faultRead(EL1, HCR_TRAP(tid3))
4088 .allPrivileges().writes(0);
4089 InitReg(MISCREG_ID_AA64ISAR1_EL1)
4090 .reset([p,release=release](){
4091 AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
4092 isar1_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 0x1 : 0x0;
4093 isar1_el1.apa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0;
4094 isar1_el1.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
4095 isar1_el1.fcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
4096 isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0;
4097 return isar1_el1;
4098 }())
4099 .faultRead(EL0, faultIdst)
4100 .faultRead(EL1, HCR_TRAP(tid3))
4101 .allPrivileges().writes(0);
4102 InitReg(MISCREG_ID_AA64MMFR0_EL1)
4103 .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
4104 AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
4105 mmfr0_el1.asidbits = asidbits ? 0x2 : 0x0;
4106 mmfr0_el1.parange = encodePhysAddrRange64(parange);
4107 return mmfr0_el1;
4108 }())
4109 .faultRead(EL0, faultIdst)
4110 .faultRead(EL1, HCR_TRAP(tid3))
4111 .allPrivileges().writes(0);
4112 InitReg(MISCREG_ID_AA64MMFR1_EL1)
4113 .reset([p,release=release](){
4114 AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
4115 mmfr1_el1.vmidbits = release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0;
4116 mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
4117 mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0;
4118 mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
4119 mmfr1_el1.hcx = release->has(ArmExtension::FEAT_HCX) ? 0x1 : 0x0;
4120 return mmfr1_el1;
4121 }())
4122 .faultRead(EL0, faultIdst)
4123 .faultRead(EL1, HCR_TRAP(tid3))
4124 .allPrivileges().writes(0);
4125 InitReg(MISCREG_ID_AA64MMFR2_EL1)
4126 .reset([p,release=release](){
4127 AA64MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
4128 mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
4129 mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0;
4130 mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 : 0x0;
4131 mmfr2_el1.evt = release->has(ArmExtension::FEAT_EVT) ? 0x2 : 0x0;
4132 return mmfr2_el1;
4133 }())
4134 .faultRead(EL0, faultIdst)
4135 .faultRead(EL1, HCR_TRAP(tid3))
4136 .allPrivileges().writes(0);
4137
4138 InitReg(MISCREG_APDAKeyHi_EL1)
4139 .fault(EL1, faultPauthEL1)
4140 .fault(EL2, faultPauthEL2)
4141 .allPrivileges().exceptUserMode();
4142 InitReg(MISCREG_APDAKeyLo_EL1)
4143 .fault(EL1, faultPauthEL1)
4144 .fault(EL2, faultPauthEL2)
4145 .allPrivileges().exceptUserMode();
4146 InitReg(MISCREG_APDBKeyHi_EL1)
4147 .fault(EL1, faultPauthEL1)
4148 .fault(EL2, faultPauthEL2)
4149 .allPrivileges().exceptUserMode();
4150 InitReg(MISCREG_APDBKeyLo_EL1)
4151 .fault(EL1, faultPauthEL1)
4152 .fault(EL2, faultPauthEL2)
4153 .allPrivileges().exceptUserMode();
4154 InitReg(MISCREG_APGAKeyHi_EL1)
4155 .fault(EL1, faultPauthEL1)
4156 .fault(EL2, faultPauthEL2)
4157 .allPrivileges().exceptUserMode();
4158 InitReg(MISCREG_APGAKeyLo_EL1)
4159 .fault(EL1, faultPauthEL1)
4160 .fault(EL2, faultPauthEL2)
4161 .allPrivileges().exceptUserMode();
4162 InitReg(MISCREG_APIAKeyHi_EL1)
4163 .fault(EL1, faultPauthEL1)
4164 .fault(EL2, faultPauthEL2)
4165 .allPrivileges().exceptUserMode();
4166 InitReg(MISCREG_APIAKeyLo_EL1)
4167 .fault(EL1, faultPauthEL1)
4168 .fault(EL2, faultPauthEL2)
4169 .allPrivileges().exceptUserMode();
4170 InitReg(MISCREG_APIBKeyHi_EL1)
4171 .fault(EL1, faultPauthEL1)
4172 .fault(EL2, faultPauthEL2)
4173 .allPrivileges().exceptUserMode();
4174 InitReg(MISCREG_APIBKeyLo_EL1)
4175 .fault(EL1, faultPauthEL1)
4176 .fault(EL2, faultPauthEL2)
4177 .allPrivileges().exceptUserMode();
4178
4179 InitReg(MISCREG_CCSIDR_EL1)
4180 .faultRead(EL0, faultIdst)
4181 .faultRead(EL1, faultCacheEL1)
4182 .allPrivileges().writes(0);
4183 InitReg(MISCREG_CLIDR_EL1)
4184 .faultRead(EL0, faultIdst)
4185 .faultRead(EL1, faultCacheEL1)
4186 .allPrivileges().writes(0);
4187 InitReg(MISCREG_AIDR_EL1)
4188 .faultRead(EL0, faultIdst)
4189 .faultRead(EL1, HCR_TRAP(tid1))
4190 .allPrivileges().writes(0);
4191 InitReg(MISCREG_CSSELR_EL1)
4192 .allPrivileges().exceptUserMode()
4193 .fault(EL1, faultCacheEL1)
4194 .mapsTo(MISCREG_CSSELR_NS);
4195 InitReg(MISCREG_CTR_EL0)
4196 .faultRead(EL0, faultCtrEL0)
4197 .faultRead(EL1, HCR_TRAP(tid2))
4198 .reads(1)
4199 .mapsTo(MISCREG_CTR);
4200 InitReg(MISCREG_DCZID_EL0)
4201 .reset(0x04) // DC ZVA clear 64-byte chunks
4202 .reads(1);
4203 InitReg(MISCREG_VPIDR_EL2)
4204 .hyp().mon()
4205 .mapsTo(MISCREG_VPIDR);
4206 InitReg(MISCREG_VMPIDR_EL2)
4207 .hyp().mon()
4208 .res0(mask(63, 40) | mask(29, 25))
4209 .res1(mask(31, 31))
4210 .mapsTo(MISCREG_VMPIDR);
4211 InitReg(MISCREG_SCTLR_EL1)
4212 .allPrivileges().exceptUserMode()
4213 .faultRead(EL1, HCR_TRAP(trvm))
4214 .faultWrite(EL1, HCR_TRAP(tvm))
4215 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4216 | (IESB ? 0 : 0x200000)
4217 | (EnDA ? 0 : 0x8000000)
4218 | (EnIB ? 0 : 0x40000000)
4219 | (EnIA ? 0 : 0x80000000))
4220 .res1(0x500800 | (SPAN ? 0 : 0x800000)
4221 | (nTLSMD ? 0 : 0x8000000)
4222 | (LSMAOE ? 0 : 0x10000000))
4223 .mapsTo(MISCREG_SCTLR_NS);
4224 InitReg(MISCREG_SCTLR_EL12)
4225 .fault(EL2, defaultFaultE2H_EL2)
4226 .fault(EL3, defaultFaultE2H_EL3)
4227 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4228 | (IESB ? 0 : 0x200000)
4229 | (EnDA ? 0 : 0x8000000)
4230 | (EnIB ? 0 : 0x40000000)
4231 | (EnIA ? 0 : 0x80000000))
4232 .res1(0x500800 | (SPAN ? 0 : 0x800000)
4233 | (nTLSMD ? 0 : 0x8000000)
4234 | (LSMAOE ? 0 : 0x10000000))
4235 .mapsTo(MISCREG_SCTLR_EL1);
4236 InitReg(MISCREG_ACTLR_EL1)
4237 .allPrivileges().exceptUserMode()
4238 .fault(EL1, HCR_TRAP(tacr))
4239 .mapsTo(MISCREG_ACTLR_NS);
4240 InitReg(MISCREG_CPACR_EL1)
4241 .allPrivileges().exceptUserMode()
4242 .fault(EL1, faultCpacrEL1)
4243 .fault(EL2, faultCpacrEL2)
4244 .mapsTo(MISCREG_CPACR);
4245 InitReg(MISCREG_CPACR_EL12)
4246 .fault(EL2, faultCpacrVheEL2)
4247 .fault(EL3, defaultFaultE2H_EL3)
4248 .mapsTo(MISCREG_CPACR_EL1);
4249 InitReg(MISCREG_SCTLR_EL2)
4250 .hyp().mon()
4251 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4252 | (IESB ? 0 : 0x200000)
4253 | (EnDA ? 0 : 0x8000000)
4254 | (EnIB ? 0 : 0x40000000)
4255 | (EnIA ? 0 : 0x80000000))
4256 .res1(0x30c50830)
4257 .mapsTo(MISCREG_HSCTLR);
4258 InitReg(MISCREG_ACTLR_EL2)
4259 .hyp().mon()
4260 .mapsTo(MISCREG_HACTLR);
4261 InitReg(MISCREG_HCR_EL2)
4262 .hyp().mon()
4263 .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4264 InitReg(MISCREG_HCRX_EL2)
4265 .hyp().mon()
4266 .fault(EL2, faultHcrxEL2);
4267 InitReg(MISCREG_MDCR_EL2)
4268 .hyp().mon()
4269 .fault(EL2, faultDebugEL2)
4270 .mapsTo(MISCREG_HDCR);
4271 InitReg(MISCREG_CPTR_EL2)
4272 .hyp().mon()
4273 .fault(EL2, faultCpacrEL2)
4274 .mapsTo(MISCREG_HCPTR);
4275 InitReg(MISCREG_HSTR_EL2)
4276 .hyp().mon()
4277 .mapsTo(MISCREG_HSTR);
4278 InitReg(MISCREG_HACR_EL2)
4279 .hyp().mon()
4280 .mapsTo(MISCREG_HACR);
4281 InitReg(MISCREG_SCTLR_EL3)
4282 .reset(0x30c50830)
4283 .mon()
4284 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4285 | (IESB ? 0 : 0x200000)
4286 | (EnDA ? 0 : 0x8000000)
4287 | (EnIB ? 0 : 0x40000000)
4288 | (EnIA ? 0 : 0x80000000))
4289 .res1(0x30c50830);
4290 InitReg(MISCREG_ACTLR_EL3)
4291 .mon();
4292 InitReg(MISCREG_SCR_EL3)
4293 .mon()
4294 .mapsTo(MISCREG_SCR); // NAM D7-2005
4295 InitReg(MISCREG_SDER32_EL3)
4296 .mon()
4297 .mapsTo(MISCREG_SDER);
4298 InitReg(MISCREG_CPTR_EL3)
4299 .mon();
4300 InitReg(MISCREG_MDCR_EL3)
4301 .mon()
4302 .mapsTo(MISCREG_SDCR);
4303 InitReg(MISCREG_TTBR0_EL1)
4304 .allPrivileges().exceptUserMode()
4305 .faultRead(EL1, HCR_TRAP(trvm))
4306 .faultWrite(EL1, HCR_TRAP(tvm))
4307 .mapsTo(MISCREG_TTBR0_NS);
4308 InitReg(MISCREG_TTBR0_EL12)
4309 .fault(EL2, defaultFaultE2H_EL2)
4310 .fault(EL3, defaultFaultE2H_EL3)
4311 .mapsTo(MISCREG_TTBR0_EL1);
4312 InitReg(MISCREG_TTBR1_EL1)
4313 .allPrivileges().exceptUserMode()
4314 .faultRead(EL1, HCR_TRAP(trvm))
4315 .faultWrite(EL1, HCR_TRAP(tvm))
4316 .mapsTo(MISCREG_TTBR1_NS);
4317 InitReg(MISCREG_TTBR1_EL12)
4318 .fault(EL2, defaultFaultE2H_EL2)
4319 .fault(EL3, defaultFaultE2H_EL3)
4320 .mapsTo(MISCREG_TTBR1_EL1);
4321 InitReg(MISCREG_TCR_EL1)
4322 .allPrivileges().exceptUserMode()
4323 .faultRead(EL1, HCR_TRAP(trvm))
4324 .faultWrite(EL1, HCR_TRAP(tvm))
4325 .mapsTo(MISCREG_TTBCR_NS);
4326 InitReg(MISCREG_TCR_EL12)
4327 .fault(EL2, defaultFaultE2H_EL2)
4328 .fault(EL3, defaultFaultE2H_EL3)
4329 .mapsTo(MISCREG_TTBCR_NS);
4330 InitReg(MISCREG_TTBR0_EL2)
4331 .hyp().mon()
4332 .mapsTo(MISCREG_HTTBR);
4333 InitReg(MISCREG_TTBR1_EL2)
4334 .hyp().mon();
4335 InitReg(MISCREG_TCR_EL2)
4336 .hyp().mon()
4337 .mapsTo(MISCREG_HTCR);
4338 InitReg(MISCREG_VTTBR_EL2)
4339 .hyp().mon()
4340 .mapsTo(MISCREG_VTTBR);
4341 InitReg(MISCREG_VTCR_EL2)
4342 .hyp().mon()
4343 .mapsTo(MISCREG_VTCR);
4344 InitReg(MISCREG_VSTTBR_EL2)
4345 .hypSecure().mon();
4346 InitReg(MISCREG_VSTCR_EL2)
4347 .hypSecure().mon();
4348 InitReg(MISCREG_TTBR0_EL3)
4349 .mon();
4350 InitReg(MISCREG_TCR_EL3)
4351 .mon();
4352 InitReg(MISCREG_DACR32_EL2)
4353 .hyp().mon()
4354 .mapsTo(MISCREG_DACR_NS);
4355 InitReg(MISCREG_SPSR_EL1)
4356 .allPrivileges().exceptUserMode()
4357 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4358 InitReg(MISCREG_SPSR_EL12)
4359 .fault(EL2, defaultFaultE2H_EL2)
4360 .fault(EL3, defaultFaultE2H_EL3)
4361 .mapsTo(MISCREG_SPSR_SVC);
4362 InitReg(MISCREG_ELR_EL1)
4363 .allPrivileges().exceptUserMode();
4364 InitReg(MISCREG_ELR_EL12)
4365 .fault(EL2, defaultFaultE2H_EL2)
4366 .fault(EL3, defaultFaultE2H_EL3)
4367 .mapsTo(MISCREG_ELR_EL1);
4368 InitReg(MISCREG_SP_EL0)
4369 .allPrivileges().exceptUserMode()
4370 .fault(EL1, faultSpEL0)
4371 .fault(EL2, faultSpEL0)
4372 .fault(EL3, faultSpEL0);
4373 InitReg(MISCREG_SPSEL)
4374 .allPrivileges().exceptUserMode();
4375 InitReg(MISCREG_CURRENTEL)
4376 .allPrivileges().exceptUserMode().writes(0);
4377 InitReg(MISCREG_PAN)
4378 .allPrivileges(release->has(ArmExtension::FEAT_PAN))
4379 .exceptUserMode();
4380 InitReg(MISCREG_UAO)
4381 .allPrivileges().exceptUserMode();
4382 InitReg(MISCREG_NZCV)
4383 .allPrivileges();
4384 InitReg(MISCREG_DAIF)
4385 .allPrivileges()
4386 .fault(EL0, faultDaif);
4387 InitReg(MISCREG_FPCR)
4388 .allPrivileges()
4389 .fault(EL0, faultFpcrEL0)
4390 .fault(EL1, faultFpcrEL1)
4391 .fault(EL2, faultFpcrEL2)
4392 .fault(EL3, faultFpcrEL3);
4393 InitReg(MISCREG_FPSR)
4394 .allPrivileges()
4395 .fault(EL0, faultFpcrEL0)
4396 .fault(EL1, faultFpcrEL1)
4397 .fault(EL2, faultFpcrEL2)
4398 .fault(EL3, faultFpcrEL3);
4399 InitReg(MISCREG_DSPSR_EL0)
4400 .allPrivileges();
4401 InitReg(MISCREG_DLR_EL0)
4402 .allPrivileges();
4403 InitReg(MISCREG_SPSR_EL2)
4404 .hyp().mon()
4405 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4406 InitReg(MISCREG_ELR_EL2)
4407 .hyp().mon();
4408 InitReg(MISCREG_SP_EL1)
4409 .hyp().mon();
4410 InitReg(MISCREG_SPSR_IRQ_AA64)
4411 .hyp().mon();
4412 InitReg(MISCREG_SPSR_ABT_AA64)
4413 .hyp().mon();
4414 InitReg(MISCREG_SPSR_UND_AA64)
4415 .hyp().mon();
4416 InitReg(MISCREG_SPSR_FIQ_AA64)
4417 .hyp().mon();
4418 InitReg(MISCREG_SPSR_EL3)
4419 .mon()
4420 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4421 InitReg(MISCREG_ELR_EL3)
4422 .mon();
4423 InitReg(MISCREG_SP_EL2)
4424 .mon();
4425 InitReg(MISCREG_AFSR0_EL1)
4426 .allPrivileges().exceptUserMode()
4427 .faultRead(EL1, HCR_TRAP(trvm))
4428 .faultWrite(EL1, HCR_TRAP(tvm))
4429 .mapsTo(MISCREG_ADFSR_NS);
4430 InitReg(MISCREG_AFSR0_EL12)
4431 .fault(EL2, defaultFaultE2H_EL2)
4432 .fault(EL3, defaultFaultE2H_EL3)
4433 .mapsTo(MISCREG_ADFSR_NS);
4434 InitReg(MISCREG_AFSR1_EL1)
4435 .allPrivileges().exceptUserMode()
4436 .faultRead(EL1, HCR_TRAP(trvm))
4437 .faultWrite(EL1, HCR_TRAP(tvm))
4438 .mapsTo(MISCREG_AIFSR_NS);
4439 InitReg(MISCREG_AFSR1_EL12)
4440 .fault(EL2, defaultFaultE2H_EL2)
4441 .fault(EL3, defaultFaultE2H_EL3)
4442 .mapsTo(MISCREG_AIFSR_NS);
4443 InitReg(MISCREG_ESR_EL1)
4444 .faultRead(EL1, HCR_TRAP(trvm))
4445 .faultWrite(EL1, HCR_TRAP(tvm))
4446 .allPrivileges().exceptUserMode();
4447 InitReg(MISCREG_ESR_EL12)
4448 .fault(EL2, defaultFaultE2H_EL2)
4449 .fault(EL3, defaultFaultE2H_EL3)
4450 .mapsTo(MISCREG_ESR_EL1);
4451 InitReg(MISCREG_IFSR32_EL2)
4452 .hyp().mon()
4453 .mapsTo(MISCREG_IFSR_NS);
4454 InitReg(MISCREG_AFSR0_EL2)
4455 .hyp().mon()
4456 .mapsTo(MISCREG_HADFSR);
4457 InitReg(MISCREG_AFSR1_EL2)
4458 .hyp().mon()
4459 .mapsTo(MISCREG_HAIFSR);
4460 InitReg(MISCREG_ESR_EL2)
4461 .hyp().mon()
4462 .mapsTo(MISCREG_HSR);
4463 InitReg(MISCREG_FPEXC32_EL2)
4464 .fault(EL2, faultFpcrEL2)
4465 .fault(EL3, faultFpcrEL3)
4466 .mapsTo(MISCREG_FPEXC);
4467 InitReg(MISCREG_AFSR0_EL3)
4468 .mon();
4469 InitReg(MISCREG_AFSR1_EL3)
4470 .mon();
4471 InitReg(MISCREG_ESR_EL3)
4472 .mon();
4473 InitReg(MISCREG_FAR_EL1)
4474 .allPrivileges().exceptUserMode()
4475 .faultRead(EL1, HCR_TRAP(trvm))
4476 .faultWrite(EL1, HCR_TRAP(tvm))
4477 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4478 InitReg(MISCREG_FAR_EL12)
4479 .fault(EL2, defaultFaultE2H_EL2)
4480 .fault(EL3, defaultFaultE2H_EL3)
4481 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4482 InitReg(MISCREG_FAR_EL2)
4483 .hyp().mon()
4484 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4485 InitReg(MISCREG_HPFAR_EL2)
4486 .hyp().mon()
4487 .mapsTo(MISCREG_HPFAR);
4488 InitReg(MISCREG_FAR_EL3)
4489 .mon();
4490 InitReg(MISCREG_IC_IALLUIS)
4491 .warnNotFail()
4492 .faultWrite(EL1, faultPouIsEL1)
4493 .writes(1).exceptUserMode();
4494 InitReg(MISCREG_PAR_EL1)
4495 .allPrivileges().exceptUserMode()
4496 .mapsTo(MISCREG_PAR_NS);
4497 InitReg(MISCREG_IC_IALLU)
4498 .warnNotFail()
4499 .faultWrite(EL1, faultPouEL1)
4500 .writes(1).exceptUserMode();
4501 InitReg(MISCREG_DC_IVAC_Xt)
4502 .faultWrite(EL1, HCR_TRAP(tpc))
4503 .writes(1).exceptUserMode();
4504 InitReg(MISCREG_DC_ISW_Xt)
4505 .warnNotFail()
4506 .faultWrite(EL1, HCR_TRAP(tsw))
4507 .writes(1).exceptUserMode();
4508 InitReg(MISCREG_AT_S1E1R_Xt)
4509 .faultWrite(EL1, HCR_TRAP(at))
4510 .writes(1).exceptUserMode();
4511 InitReg(MISCREG_AT_S1E1W_Xt)
4512 .faultWrite(EL1, HCR_TRAP(at))
4513 .writes(1).exceptUserMode();
4514 InitReg(MISCREG_AT_S1E0R_Xt)
4515 .faultWrite(EL1, HCR_TRAP(at))
4516 .writes(1).exceptUserMode();
4517 InitReg(MISCREG_AT_S1E0W_Xt)
4518 .faultWrite(EL1, HCR_TRAP(at))
4519 .writes(1).exceptUserMode();
4520 InitReg(MISCREG_DC_CSW_Xt)
4521 .warnNotFail()
4522 .faultWrite(EL1, HCR_TRAP(tsw))
4523 .writes(1).exceptUserMode();
4524 InitReg(MISCREG_DC_CISW_Xt)
4525 .warnNotFail()
4526 .faultWrite(EL1, HCR_TRAP(tsw))
4527 .writes(1).exceptUserMode();
4528 InitReg(MISCREG_DC_ZVA_Xt)
4529 .writes(1)
4530 .faultWrite(EL0, faultDczvaEL0)
4531 .faultWrite(EL1, HCR_TRAP(tdz));
4532 InitReg(MISCREG_IC_IVAU_Xt)
4533 .faultWrite(EL0, faultPouEL0)
4534 .faultWrite(EL1, faultPouEL1)
4535 .writes(1);
4536 InitReg(MISCREG_DC_CVAC_Xt)
4537 .faultWrite(EL0, faultCvacEL0)
4538 .faultWrite(EL1, HCR_TRAP(tpc))
4539 .writes(1);
4540 InitReg(MISCREG_DC_CVAU_Xt)
4541 .faultWrite(EL0, faultPouEL0)
4542 .faultWrite(EL1, faultPouEL1)
4543 .writes(1);
4544 InitReg(MISCREG_DC_CIVAC_Xt)
4545 .faultWrite(EL0, faultCvacEL0)
4546 .faultWrite(EL1, HCR_TRAP(tpc))
4547 .writes(1);
4548 InitReg(MISCREG_AT_S1E2R_Xt)
4549 .monNonSecureWrite().hypWrite();
4550 InitReg(MISCREG_AT_S1E2W_Xt)
4551 .monNonSecureWrite().hypWrite();
4552 InitReg(MISCREG_AT_S12E1R_Xt)
4553 .hypWrite().monSecureWrite().monNonSecureWrite();
4554 InitReg(MISCREG_AT_S12E1W_Xt)
4555 .hypWrite().monSecureWrite().monNonSecureWrite();
4556 InitReg(MISCREG_AT_S12E0R_Xt)
4557 .hypWrite().monSecureWrite().monNonSecureWrite();
4558 InitReg(MISCREG_AT_S12E0W_Xt)
4559 .hypWrite().monSecureWrite().monNonSecureWrite();
4560 InitReg(MISCREG_AT_S1E3R_Xt)
4561 .monSecureWrite().monNonSecureWrite();
4562 InitReg(MISCREG_AT_S1E3W_Xt)
4563 .monSecureWrite().monNonSecureWrite();
4564 InitReg(MISCREG_TLBI_VMALLE1OS)
4565 .faultWrite(EL1, faultTlbiOsEL1)
4566 .writes(1).exceptUserMode();
4567 InitReg(MISCREG_TLBI_VAE1OS_Xt)
4568 .faultWrite(EL1, faultTlbiOsEL1)
4569 .writes(1).exceptUserMode();
4570 InitReg(MISCREG_TLBI_ASIDE1OS_Xt)
4571 .faultWrite(EL1, faultTlbiOsEL1)
4572 .writes(1).exceptUserMode();
4573 InitReg(MISCREG_TLBI_VAAE1OS_Xt)
4574 .faultWrite(EL1, faultTlbiOsEL1)
4575 .writes(1).exceptUserMode();
4576 InitReg(MISCREG_TLBI_VALE1OS_Xt)
4577 .faultWrite(EL1, faultTlbiOsEL1)
4578 .writes(1).exceptUserMode();
4579 InitReg(MISCREG_TLBI_VAALE1OS_Xt)
4580 .faultWrite(EL1, faultTlbiOsEL1)
4581 .writes(1).exceptUserMode();
4582 InitReg(MISCREG_TLBI_VMALLE1IS)
4583 .faultWrite(EL1, faultTlbiIsEL1)
4584 .writes(1).exceptUserMode();
4585 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4586 .faultWrite(EL1, faultTlbiIsEL1)
4587 .writes(1).exceptUserMode();
4588 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4589 .faultWrite(EL1, faultTlbiIsEL1)
4590 .writes(1).exceptUserMode();
4591 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4592 .faultWrite(EL1, faultTlbiIsEL1)
4593 .writes(1).exceptUserMode();
4594 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4595 .faultWrite(EL1, faultTlbiIsEL1)
4596 .writes(1).exceptUserMode();
4597 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4598 .faultWrite(EL1, faultTlbiIsEL1)
4599 .writes(1).exceptUserMode();
4600 InitReg(MISCREG_TLBI_VMALLE1)
4601 .faultWrite(EL1, HCR_TRAP(ttlb))
4602 .writes(1).exceptUserMode();
4603 InitReg(MISCREG_TLBI_VAE1_Xt)
4604 .faultWrite(EL1, HCR_TRAP(ttlb))
4605 .writes(1).exceptUserMode();
4606 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4607 .faultWrite(EL1, HCR_TRAP(ttlb))
4608 .writes(1).exceptUserMode();
4609 InitReg(MISCREG_TLBI_VAAE1_Xt)
4610 .faultWrite(EL1, HCR_TRAP(ttlb))
4611 .writes(1).exceptUserMode();
4612 InitReg(MISCREG_TLBI_VALE1_Xt)
4613 .faultWrite(EL1, HCR_TRAP(ttlb))
4614 .writes(1).exceptUserMode();
4615 InitReg(MISCREG_TLBI_VAALE1_Xt)
4616 .faultWrite(EL1, HCR_TRAP(ttlb))
4617 .writes(1).exceptUserMode();
4618 InitReg(MISCREG_TLBI_IPAS2E1OS_Xt)
4619 .hypWrite().monSecureWrite().monNonSecureWrite();
4620 InitReg(MISCREG_TLBI_IPAS2LE1OS_Xt)
4621 .hypWrite().monSecureWrite().monNonSecureWrite();
4622 InitReg(MISCREG_TLBI_ALLE2OS)
4623 .monNonSecureWrite().hypWrite();
4624 InitReg(MISCREG_TLBI_VAE2OS_Xt)
4625 .monNonSecureWrite().hypWrite();
4626 InitReg(MISCREG_TLBI_ALLE1OS)
4627 .hypWrite().monSecureWrite().monNonSecureWrite();
4628 InitReg(MISCREG_TLBI_VALE2OS_Xt)
4629 .monNonSecureWrite().hypWrite();
4630 InitReg(MISCREG_TLBI_VMALLS12E1OS)
4631 .hypWrite().monSecureWrite().monNonSecureWrite();
4632 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4633 .hypWrite().monSecureWrite().monNonSecureWrite();
4634 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4635 .hypWrite().monSecureWrite().monNonSecureWrite();
4636 InitReg(MISCREG_TLBI_ALLE2IS)
4637 .monNonSecureWrite().hypWrite();
4638 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4639 .monNonSecureWrite().hypWrite();
4640 InitReg(MISCREG_TLBI_ALLE1IS)
4641 .hypWrite().monSecureWrite().monNonSecureWrite();
4642 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4643 .monNonSecureWrite().hypWrite();
4644 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4645 .hypWrite().monSecureWrite().monNonSecureWrite();
4646 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4647 .hypWrite().monSecureWrite().monNonSecureWrite();
4648 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4649 .hypWrite().monSecureWrite().monNonSecureWrite();
4650 InitReg(MISCREG_TLBI_ALLE2)
4651 .monNonSecureWrite().hypWrite();
4652 InitReg(MISCREG_TLBI_VAE2_Xt)
4653 .monNonSecureWrite().hypWrite();
4654 InitReg(MISCREG_TLBI_ALLE1)
4655 .hypWrite().monSecureWrite().monNonSecureWrite();
4656 InitReg(MISCREG_TLBI_VALE2_Xt)
4657 .monNonSecureWrite().hypWrite();
4658 InitReg(MISCREG_TLBI_VMALLS12E1)
4659 .hypWrite().monSecureWrite().monNonSecureWrite();
4660 InitReg(MISCREG_TLBI_ALLE3OS)
4661 .monSecureWrite().monNonSecureWrite();
4662 InitReg(MISCREG_TLBI_VAE3OS_Xt)
4663 .monSecureWrite().monNonSecureWrite();
4664 InitReg(MISCREG_TLBI_VALE3OS_Xt)
4665 .monSecureWrite().monNonSecureWrite();
4666 InitReg(MISCREG_TLBI_ALLE3IS)
4667 .monSecureWrite().monNonSecureWrite();
4668 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4669 .monSecureWrite().monNonSecureWrite();
4670 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4671 .monSecureWrite().monNonSecureWrite();
4672 InitReg(MISCREG_TLBI_ALLE3)
4673 .monSecureWrite().monNonSecureWrite();
4674 InitReg(MISCREG_TLBI_VAE3_Xt)
4675 .monSecureWrite().monNonSecureWrite();
4676 InitReg(MISCREG_TLBI_VALE3_Xt)
4677 .monSecureWrite().monNonSecureWrite();
4678 InitReg(MISCREG_PMINTENSET_EL1)
4679 .allPrivileges().exceptUserMode()
4680 .mapsTo(MISCREG_PMINTENSET);
4681 InitReg(MISCREG_PMINTENCLR_EL1)
4682 .allPrivileges().exceptUserMode()
4683 .mapsTo(MISCREG_PMINTENCLR);
4684 InitReg(MISCREG_PMCR_EL0)
4685 .allPrivileges()
4686 .mapsTo(MISCREG_PMCR);
4687 InitReg(MISCREG_PMCNTENSET_EL0)
4688 .allPrivileges()
4689 .mapsTo(MISCREG_PMCNTENSET);
4690 InitReg(MISCREG_PMCNTENCLR_EL0)
4691 .allPrivileges()
4692 .mapsTo(MISCREG_PMCNTENCLR);
4693 InitReg(MISCREG_PMOVSCLR_EL0)
4694 .allPrivileges();
4695// .mapsTo(MISCREG_PMOVSCLR);
4696 InitReg(MISCREG_PMSWINC_EL0)
4697 .writes(1).user()
4698 .mapsTo(MISCREG_PMSWINC);
4699 InitReg(MISCREG_PMSELR_EL0)
4700 .allPrivileges()
4701 .mapsTo(MISCREG_PMSELR);
4702 InitReg(MISCREG_PMCEID0_EL0)
4703 .reads(1).user()
4704 .mapsTo(MISCREG_PMCEID0);
4705 InitReg(MISCREG_PMCEID1_EL0)
4706 .reads(1).user()
4707 .mapsTo(MISCREG_PMCEID1);
4708 InitReg(MISCREG_PMCCNTR_EL0)
4709 .allPrivileges()
4710 .mapsTo(MISCREG_PMCCNTR);
4711 InitReg(MISCREG_PMXEVTYPER_EL0)
4712 .allPrivileges()
4713 .mapsTo(MISCREG_PMXEVTYPER);
4714 InitReg(MISCREG_PMCCFILTR_EL0)
4715 .allPrivileges();
4716 InitReg(MISCREG_PMXEVCNTR_EL0)
4717 .allPrivileges()
4718 .mapsTo(MISCREG_PMXEVCNTR);
4719 InitReg(MISCREG_PMUSERENR_EL0)
4720 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4721 .mapsTo(MISCREG_PMUSERENR);
4722 InitReg(MISCREG_PMOVSSET_EL0)
4723 .allPrivileges()
4724 .mapsTo(MISCREG_PMOVSSET);
4725 InitReg(MISCREG_MAIR_EL1)
4726 .allPrivileges().exceptUserMode()
4727 .faultRead(EL1, HCR_TRAP(trvm))
4728 .faultWrite(EL1, HCR_TRAP(tvm))
4729 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4730 InitReg(MISCREG_MAIR_EL12)
4731 .fault(EL2, defaultFaultE2H_EL2)
4732 .fault(EL3, defaultFaultE2H_EL3)
4733 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4734 InitReg(MISCREG_AMAIR_EL1)
4735 .allPrivileges().exceptUserMode()
4736 .faultRead(EL1, HCR_TRAP(trvm))
4737 .faultWrite(EL1, HCR_TRAP(tvm))
4738 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4739 InitReg(MISCREG_AMAIR_EL12)
4740 .fault(EL2, defaultFaultE2H_EL2)
4741 .fault(EL3, defaultFaultE2H_EL3)
4742 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4743 InitReg(MISCREG_MAIR_EL2)
4744 .hyp().mon()
4745 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4746 InitReg(MISCREG_AMAIR_EL2)
4747 .hyp().mon()
4748 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4749 InitReg(MISCREG_MAIR_EL3)
4750 .mon();
4751 InitReg(MISCREG_AMAIR_EL3)
4752 .mon();
4753 InitReg(MISCREG_L2CTLR_EL1)
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_L2ECTLR_EL1)
4756 .allPrivileges().exceptUserMode();
4757 InitReg(MISCREG_VBAR_EL1)
4758 .allPrivileges().exceptUserMode()
4759 .mapsTo(MISCREG_VBAR_NS);
4760 InitReg(MISCREG_VBAR_EL12)
4761 .fault(EL2, defaultFaultE2H_EL2)
4762 .fault(EL3, defaultFaultE2H_EL3)
4763 .mapsTo(MISCREG_VBAR_NS);
4764 InitReg(MISCREG_RVBAR_EL1)
4765 .reset(FullSystem && system->highestEL() == EL1 ?
4766 system->resetAddr() : 0)
4767 .privRead(FullSystem && system->highestEL() == EL1);
4768 InitReg(MISCREG_ISR_EL1)
4769 .allPrivileges().exceptUserMode().writes(0);
4770 InitReg(MISCREG_VBAR_EL2)
4771 .hyp().mon()
4772 .res0(0x7ff)
4773 .mapsTo(MISCREG_HVBAR);
4774 InitReg(MISCREG_RVBAR_EL2)
4775 .reset(FullSystem && system->highestEL() == EL2 ?
4776 system->resetAddr() : 0)
4777 .hypRead(FullSystem && system->highestEL() == EL2);
4778 InitReg(MISCREG_VBAR_EL3)
4779 .mon();
4780 InitReg(MISCREG_RVBAR_EL3)
4781 .reset(FullSystem && system->highestEL() == EL3 ?
4782 system->resetAddr() : 0)
4783 .mon().writes(0);
4784 InitReg(MISCREG_RMR_EL3)
4785 .mon();
4786 InitReg(MISCREG_CONTEXTIDR_EL1)
4787 .allPrivileges().exceptUserMode()
4788 .faultRead(EL1, HCR_TRAP(trvm))
4789 .faultWrite(EL1, HCR_TRAP(tvm))
4790 .mapsTo(MISCREG_CONTEXTIDR_NS);
4791 InitReg(MISCREG_CONTEXTIDR_EL12)
4792 .fault(EL2, defaultFaultE2H_EL2)
4793 .fault(EL3, defaultFaultE2H_EL3)
4794 .mapsTo(MISCREG_CONTEXTIDR_NS);
4795 InitReg(MISCREG_TPIDR_EL1)
4796 .allPrivileges().exceptUserMode()
4797 .mapsTo(MISCREG_TPIDRPRW_NS);
4798 InitReg(MISCREG_TPIDR_EL0)
4799 .allPrivileges()
4800 .mapsTo(MISCREG_TPIDRURW_NS);
4801 InitReg(MISCREG_TPIDRRO_EL0)
4802 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4803 .mapsTo(MISCREG_TPIDRURO_NS);
4804 InitReg(MISCREG_TPIDR_EL2)
4805 .hyp().mon()
4806 .mapsTo(MISCREG_HTPIDR);
4807 InitReg(MISCREG_TPIDR_EL3)
4808 .mon();
4809 // BEGIN Generic Timer (AArch64)
4810 InitReg(MISCREG_CNTFRQ_EL0)
4811 .reads(1)
4812 .faultRead(EL0, faultGenericTimerEL0)
4813 .highest(system)
4814 .privSecureWrite(aarch32EL3)
4815 .mapsTo(MISCREG_CNTFRQ);
4816 InitReg(MISCREG_CNTPCT_EL0)
4817 .unverifiable()
4818 .faultRead(EL0, faultCntpctEL0)
4819 .faultRead(EL1, faultCntpctEL1)
4820 .reads(1)
4821 .mapsTo(MISCREG_CNTPCT);
4822 InitReg(MISCREG_CNTVCT_EL0)
4823 .unverifiable()
4824 .faultRead(EL0, faultCntvctEL0)
4825 .faultRead(EL1, faultCntvctEL1)
4826 .reads(1)
4827 .mapsTo(MISCREG_CNTVCT);
4828 InitReg(MISCREG_CNTP_CTL_EL0)
4829 .allPrivileges()
4830 .fault(EL0, faultCntpCtlEL0)
4831 .fault(EL1, faultCntpCtlEL1)
4832 .res0(0xfffffffffffffff8)
4833 .mapsTo(MISCREG_CNTP_CTL_NS);
4834 InitReg(MISCREG_CNTP_CVAL_EL0)
4835 .allPrivileges()
4836 .fault(EL0, faultCntpCtlEL0)
4837 .fault(EL1, faultCntpCtlEL1)
4838 .mapsTo(MISCREG_CNTP_CVAL_NS);
4839 InitReg(MISCREG_CNTP_TVAL_EL0)
4840 .allPrivileges()
4841 .fault(EL0, faultCntpCtlEL0)
4842 .fault(EL1, faultCntpCtlEL1)
4843 .res0(0xffffffff00000000)
4844 .mapsTo(MISCREG_CNTP_TVAL_NS);
4845 InitReg(MISCREG_CNTV_CTL_EL0)
4846 .allPrivileges()
4847 .fault(EL0, faultCntvCtlEL0)
4848 .fault(EL1, faultCntvCtlEL1)
4849 .res0(0xfffffffffffffff8)
4850 .mapsTo(MISCREG_CNTV_CTL);
4851 InitReg(MISCREG_CNTV_CVAL_EL0)
4852 .allPrivileges()
4853 .fault(EL0, faultCntvCtlEL0)
4854 .fault(EL1, faultCntvCtlEL1)
4855 .mapsTo(MISCREG_CNTV_CVAL);
4856 InitReg(MISCREG_CNTV_TVAL_EL0)
4857 .allPrivileges()
4858 .fault(EL0, faultCntvCtlEL0)
4859 .fault(EL1, faultCntvCtlEL1)
4860 .res0(0xffffffff00000000)
4861 .mapsTo(MISCREG_CNTV_TVAL);
4862 InitReg(MISCREG_CNTP_CTL_EL02)
4863 .fault(EL2, defaultFaultE2H_EL2)
4864 .fault(EL3, defaultFaultE2H_EL3)
4865 .res0(0xfffffffffffffff8)
4866 .mapsTo(MISCREG_CNTP_CTL_NS);
4867 InitReg(MISCREG_CNTP_CVAL_EL02)
4868 .fault(EL2, defaultFaultE2H_EL2)
4869 .fault(EL3, defaultFaultE2H_EL3)
4870 .mapsTo(MISCREG_CNTP_CVAL_NS);
4871 InitReg(MISCREG_CNTP_TVAL_EL02)
4872 .fault(EL2, defaultFaultE2H_EL2)
4873 .fault(EL3, defaultFaultE2H_EL3)
4874 .res0(0xffffffff00000000)
4875 .mapsTo(MISCREG_CNTP_TVAL_NS);
4876 InitReg(MISCREG_CNTV_CTL_EL02)
4877 .fault(EL2, defaultFaultE2H_EL2)
4878 .fault(EL3, defaultFaultE2H_EL3)
4879 .res0(0xfffffffffffffff8)
4880 .mapsTo(MISCREG_CNTV_CTL);
4881 InitReg(MISCREG_CNTV_CVAL_EL02)
4882 .fault(EL2, defaultFaultE2H_EL2)
4883 .fault(EL3, defaultFaultE2H_EL3)
4884 .mapsTo(MISCREG_CNTV_CVAL);
4885 InitReg(MISCREG_CNTV_TVAL_EL02)
4886 .fault(EL2, defaultFaultE2H_EL2)
4887 .fault(EL3, defaultFaultE2H_EL3)
4888 .res0(0xffffffff00000000)
4889 .mapsTo(MISCREG_CNTV_TVAL);
4890 InitReg(MISCREG_CNTKCTL_EL1)
4891 .allPrivileges()
4892 .exceptUserMode()
4893 .res0(0xfffffffffffdfc00)
4894 .mapsTo(MISCREG_CNTKCTL);
4895 InitReg(MISCREG_CNTKCTL_EL12)
4896 .fault(EL2, defaultFaultE2H_EL2)
4897 .fault(EL3, defaultFaultE2H_EL3)
4898 .res0(0xfffffffffffdfc00)
4899 .mapsTo(MISCREG_CNTKCTL);
4900 InitReg(MISCREG_CNTPS_CTL_EL1)
4901 .mon()
4902 .privSecure()
4903 .fault(EL1, faultCntpsCtlEL1)
4904 .res0(0xfffffffffffffff8);
4905 InitReg(MISCREG_CNTPS_CVAL_EL1)
4906 .mon()
4907 .privSecure()
4908 .fault(EL1, faultCntpsCtlEL1);
4909 InitReg(MISCREG_CNTPS_TVAL_EL1)
4910 .mon()
4911 .privSecure()
4912 .fault(EL1, faultCntpsCtlEL1)
4913 .res0(0xffffffff00000000);
4914 InitReg(MISCREG_CNTHCTL_EL2)
4915 .mon()
4916 .hyp()
4917 .res0(0xfffffffffffc0000)
4918 .mapsTo(MISCREG_CNTHCTL);
4919 InitReg(MISCREG_CNTHP_CTL_EL2)
4920 .mon()
4921 .hyp()
4922 .res0(0xfffffffffffffff8)
4923 .mapsTo(MISCREG_CNTHP_CTL);
4924 InitReg(MISCREG_CNTHP_CVAL_EL2)
4925 .mon()
4926 .hyp()
4927 .mapsTo(MISCREG_CNTHP_CVAL);
4928 InitReg(MISCREG_CNTHP_TVAL_EL2)
4929 .mon()
4930 .hyp()
4931 .res0(0xffffffff00000000)
4932 .mapsTo(MISCREG_CNTHP_TVAL);
4933 InitReg(MISCREG_CNTHPS_CTL_EL2)
4934 .mon(sel2_implemented)
4935 .hypSecure(sel2_implemented)
4936 .res0(0xfffffffffffffff8);
4937 InitReg(MISCREG_CNTHPS_CVAL_EL2)
4938 .mon(sel2_implemented)
4939 .hypSecure(sel2_implemented);
4940 InitReg(MISCREG_CNTHPS_TVAL_EL2)
4941 .mon(sel2_implemented)
4942 .hypSecure(sel2_implemented)
4943 .res0(0xffffffff00000000);
4944 InitReg(MISCREG_CNTHV_CTL_EL2)
4945 .mon(vhe_implemented)
4946 .hyp()
4947 .res0(0xfffffffffffffff8);
4948 InitReg(MISCREG_CNTHV_CVAL_EL2)
4949 .mon(vhe_implemented)
4950 .hyp(vhe_implemented);
4951 InitReg(MISCREG_CNTHV_TVAL_EL2)
4952 .mon(vhe_implemented)
4953 .hyp(vhe_implemented)
4954 .res0(0xffffffff00000000);
4955 InitReg(MISCREG_CNTHVS_CTL_EL2)
4956 .mon(vhe_implemented && sel2_implemented)
4957 .hypSecure(vhe_implemented && sel2_implemented)
4958 .res0(0xfffffffffffffff8);
4959 InitReg(MISCREG_CNTHVS_CVAL_EL2)
4960 .mon(vhe_implemented && sel2_implemented)
4961 .hypSecure(vhe_implemented && sel2_implemented);
4962 InitReg(MISCREG_CNTHVS_TVAL_EL2)
4963 .mon(vhe_implemented && sel2_implemented)
4964 .hypSecure(vhe_implemented && sel2_implemented)
4965 .res0(0xffffffff00000000);
4966 // ENDIF Armv8.1-VHE
4967 InitReg(MISCREG_CNTVOFF_EL2)
4968 .mon()
4969 .hyp()
4970 .mapsTo(MISCREG_CNTVOFF);
4971 // END Generic Timer (AArch64)
4972 InitReg(MISCREG_PMEVCNTR0_EL0)
4973 .allPrivileges();
4974// .mapsTo(MISCREG_PMEVCNTR0);
4975 InitReg(MISCREG_PMEVCNTR1_EL0)
4976 .allPrivileges();
4977// .mapsTo(MISCREG_PMEVCNTR1);
4978 InitReg(MISCREG_PMEVCNTR2_EL0)
4979 .allPrivileges();
4980// .mapsTo(MISCREG_PMEVCNTR2);
4981 InitReg(MISCREG_PMEVCNTR3_EL0)
4982 .allPrivileges();
4983// .mapsTo(MISCREG_PMEVCNTR3);
4984 InitReg(MISCREG_PMEVCNTR4_EL0)
4985 .allPrivileges();
4986// .mapsTo(MISCREG_PMEVCNTR4);
4987 InitReg(MISCREG_PMEVCNTR5_EL0)
4988 .allPrivileges();
4989// .mapsTo(MISCREG_PMEVCNTR5);
4990 InitReg(MISCREG_PMEVTYPER0_EL0)
4991 .allPrivileges();
4992// .mapsTo(MISCREG_PMEVTYPER0);
4993 InitReg(MISCREG_PMEVTYPER1_EL0)
4994 .allPrivileges();
4995// .mapsTo(MISCREG_PMEVTYPER1);
4996 InitReg(MISCREG_PMEVTYPER2_EL0)
4997 .allPrivileges();
4998// .mapsTo(MISCREG_PMEVTYPER2);
4999 InitReg(MISCREG_PMEVTYPER3_EL0)
5000 .allPrivileges();
5001// .mapsTo(MISCREG_PMEVTYPER3);
5002 InitReg(MISCREG_PMEVTYPER4_EL0)
5003 .allPrivileges();
5004// .mapsTo(MISCREG_PMEVTYPER4);
5005 InitReg(MISCREG_PMEVTYPER5_EL0)
5006 .allPrivileges();
5007// .mapsTo(MISCREG_PMEVTYPER5);
5008 InitReg(MISCREG_IL1DATA0_EL1)
5009 .allPrivileges().exceptUserMode();
5010 InitReg(MISCREG_IL1DATA1_EL1)
5011 .allPrivileges().exceptUserMode();
5012 InitReg(MISCREG_IL1DATA2_EL1)
5013 .allPrivileges().exceptUserMode();
5014 InitReg(MISCREG_IL1DATA3_EL1)
5015 .allPrivileges().exceptUserMode();
5016 InitReg(MISCREG_DL1DATA0_EL1)
5017 .allPrivileges().exceptUserMode();
5018 InitReg(MISCREG_DL1DATA1_EL1)
5019 .allPrivileges().exceptUserMode();
5020 InitReg(MISCREG_DL1DATA2_EL1)
5021 .allPrivileges().exceptUserMode();
5022 InitReg(MISCREG_DL1DATA3_EL1)
5023 .allPrivileges().exceptUserMode();
5024 InitReg(MISCREG_DL1DATA4_EL1)
5025 .allPrivileges().exceptUserMode();
5026 InitReg(MISCREG_L2ACTLR_EL1)
5027 .allPrivileges().exceptUserMode();
5028 InitReg(MISCREG_CPUACTLR_EL1)
5029 .allPrivileges().exceptUserMode();
5030 InitReg(MISCREG_CPUECTLR_EL1)
5031 .allPrivileges().exceptUserMode();
5032 InitReg(MISCREG_CPUMERRSR_EL1)
5033 .allPrivileges().exceptUserMode();
5034 InitReg(MISCREG_L2MERRSR_EL1)
5035 .warnNotFail()
5036 .fault(faultUnimplemented);
5037 InitReg(MISCREG_CBAR_EL1)
5038 .allPrivileges().exceptUserMode().writes(0);
5039 InitReg(MISCREG_CONTEXTIDR_EL2)
5040 .mon().hyp();
5041
5042 // GICv3 AArch64
5043 InitReg(MISCREG_ICC_PMR_EL1)
5044 .res0(0xffffff00) // [31:8]
5045 .allPrivileges().exceptUserMode()
5046 .mapsTo(MISCREG_ICC_PMR);
5047 InitReg(MISCREG_ICC_IAR0_EL1)
5048 .allPrivileges().exceptUserMode().writes(0)
5049 .mapsTo(MISCREG_ICC_IAR0);
5050 InitReg(MISCREG_ICC_EOIR0_EL1)
5051 .allPrivileges().exceptUserMode().reads(0)
5052 .mapsTo(MISCREG_ICC_EOIR0);
5053 InitReg(MISCREG_ICC_HPPIR0_EL1)
5054 .allPrivileges().exceptUserMode().writes(0)
5055 .mapsTo(MISCREG_ICC_HPPIR0);
5056 InitReg(MISCREG_ICC_BPR0_EL1)
5057 .res0(0xfffffff8) // [31:3]
5058 .allPrivileges().exceptUserMode()
5059 .mapsTo(MISCREG_ICC_BPR0);
5060 InitReg(MISCREG_ICC_AP0R0_EL1)
5061 .allPrivileges().exceptUserMode()
5062 .mapsTo(MISCREG_ICC_AP0R0);
5063 InitReg(MISCREG_ICC_AP0R1_EL1)
5064 .allPrivileges().exceptUserMode()
5065 .mapsTo(MISCREG_ICC_AP0R1);
5066 InitReg(MISCREG_ICC_AP0R2_EL1)
5067 .allPrivileges().exceptUserMode()
5068 .mapsTo(MISCREG_ICC_AP0R2);
5069 InitReg(MISCREG_ICC_AP0R3_EL1)
5070 .allPrivileges().exceptUserMode()
5071 .mapsTo(MISCREG_ICC_AP0R3);
5072 InitReg(MISCREG_ICC_AP1R0_EL1)
5073 .banked64()
5074 .mapsTo(MISCREG_ICC_AP1R0);
5075 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
5076 .bankedChild()
5077 .allPrivileges().exceptUserMode()
5078 .mapsTo(MISCREG_ICC_AP1R0_NS);
5079 InitReg(MISCREG_ICC_AP1R0_EL1_S)
5080 .bankedChild()
5081 .allPrivileges().exceptUserMode()
5082 .mapsTo(MISCREG_ICC_AP1R0_S);
5083 InitReg(MISCREG_ICC_AP1R1_EL1)
5084 .banked64()
5085 .mapsTo(MISCREG_ICC_AP1R1);
5086 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
5087 .bankedChild()
5088 .allPrivileges().exceptUserMode()
5089 .mapsTo(MISCREG_ICC_AP1R1_NS);
5090 InitReg(MISCREG_ICC_AP1R1_EL1_S)
5091 .bankedChild()
5092 .allPrivileges().exceptUserMode()
5093 .mapsTo(MISCREG_ICC_AP1R1_S);
5094 InitReg(MISCREG_ICC_AP1R2_EL1)
5095 .banked64()
5096 .mapsTo(MISCREG_ICC_AP1R2);
5097 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
5098 .bankedChild()
5099 .allPrivileges().exceptUserMode()
5100 .mapsTo(MISCREG_ICC_AP1R2_NS);
5101 InitReg(MISCREG_ICC_AP1R2_EL1_S)
5102 .bankedChild()
5103 .allPrivileges().exceptUserMode()
5104 .mapsTo(MISCREG_ICC_AP1R2_S);
5105 InitReg(MISCREG_ICC_AP1R3_EL1)
5106 .banked64()
5107 .mapsTo(MISCREG_ICC_AP1R3);
5108 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
5109 .bankedChild()
5110 .allPrivileges().exceptUserMode()
5111 .mapsTo(MISCREG_ICC_AP1R3_NS);
5112 InitReg(MISCREG_ICC_AP1R3_EL1_S)
5113 .bankedChild()
5114 .allPrivileges().exceptUserMode()
5115 .mapsTo(MISCREG_ICC_AP1R3_S);
5116 InitReg(MISCREG_ICC_DIR_EL1)
5117 .res0(0xFF000000) // [31:24]
5118 .allPrivileges().exceptUserMode().reads(0)
5119 .mapsTo(MISCREG_ICC_DIR);
5120 InitReg(MISCREG_ICC_RPR_EL1)
5121 .allPrivileges().exceptUserMode().writes(0)
5122 .mapsTo(MISCREG_ICC_RPR);
5123 InitReg(MISCREG_ICC_SGI1R_EL1)
5124 .allPrivileges().exceptUserMode().reads(0)
5125 .faultWrite(EL1, faultIccSgiEL1)
5126 .faultWrite(EL2, faultIccSgiEL2)
5127 .mapsTo(MISCREG_ICC_SGI1R);
5128 InitReg(MISCREG_ICC_ASGI1R_EL1)
5129 .allPrivileges().exceptUserMode().reads(0)
5130 .faultWrite(EL1, faultIccSgiEL1)
5131 .faultWrite(EL2, faultIccSgiEL2)
5132 .mapsTo(MISCREG_ICC_ASGI1R);
5133 InitReg(MISCREG_ICC_SGI0R_EL1)
5134 .allPrivileges().exceptUserMode().reads(0)
5135 .faultWrite(EL1, faultIccSgiEL1)
5136 .faultWrite(EL2, faultIccSgiEL2)
5137 .mapsTo(MISCREG_ICC_SGI0R);
5138 InitReg(MISCREG_ICC_IAR1_EL1)
5139 .allPrivileges().exceptUserMode().writes(0)
5140 .mapsTo(MISCREG_ICC_IAR1);
5141 InitReg(MISCREG_ICC_EOIR1_EL1)
5142 .res0(0xFF000000) // [31:24]
5143 .allPrivileges().exceptUserMode().reads(0)
5144 .mapsTo(MISCREG_ICC_EOIR1);
5145 InitReg(MISCREG_ICC_HPPIR1_EL1)
5146 .allPrivileges().exceptUserMode().writes(0)
5147 .mapsTo(MISCREG_ICC_HPPIR1);
5148 InitReg(MISCREG_ICC_BPR1_EL1)
5149 .banked64()
5150 .mapsTo(MISCREG_ICC_BPR1);
5151 InitReg(MISCREG_ICC_BPR1_EL1_NS)
5152 .bankedChild()
5153 .res0(0xfffffff8) // [31:3]
5154 .allPrivileges().exceptUserMode()
5155 .mapsTo(MISCREG_ICC_BPR1_NS);
5156 InitReg(MISCREG_ICC_BPR1_EL1_S)
5157 .bankedChild()
5158 .res0(0xfffffff8) // [31:3]
5159 .secure().exceptUserMode()
5160 .mapsTo(MISCREG_ICC_BPR1_S);
5161 InitReg(MISCREG_ICC_CTLR_EL1)
5162 .banked64()
5163 .mapsTo(MISCREG_ICC_CTLR);
5164 InitReg(MISCREG_ICC_CTLR_EL1_NS)
5165 .bankedChild()
5166 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5167 .allPrivileges().exceptUserMode()
5168 .mapsTo(MISCREG_ICC_CTLR_NS);
5169 InitReg(MISCREG_ICC_CTLR_EL1_S)
5170 .bankedChild()
5171 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5172 .secure().exceptUserMode()
5173 .mapsTo(MISCREG_ICC_CTLR_S);
5174 InitReg(MISCREG_ICC_SRE_EL1)
5175 .banked()
5176 .mapsTo(MISCREG_ICC_SRE);
5177 InitReg(MISCREG_ICC_SRE_EL1_NS)
5178 .bankedChild()
5179 .res0(0xFFFFFFF8) // [31:3]
5180 .allPrivileges().exceptUserMode()
5181 .mapsTo(MISCREG_ICC_SRE_NS);
5182 InitReg(MISCREG_ICC_SRE_EL1_S)
5183 .bankedChild()
5184 .res0(0xFFFFFFF8) // [31:3]
5185 .secure().exceptUserMode()
5186 .mapsTo(MISCREG_ICC_SRE_S);
5187 InitReg(MISCREG_ICC_IGRPEN0_EL1)
5188 .res0(0xFFFFFFFE) // [31:1]
5189 .allPrivileges().exceptUserMode()
5190 .mapsTo(MISCREG_ICC_IGRPEN0);
5191 InitReg(MISCREG_ICC_IGRPEN1_EL1)
5192 .banked64()
5193 .mapsTo(MISCREG_ICC_IGRPEN1);
5194 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
5195 .bankedChild()
5196 .res0(0xFFFFFFFE) // [31:1]
5197 .allPrivileges().exceptUserMode()
5198 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
5199 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
5200 .bankedChild()
5201 .res0(0xFFFFFFFE) // [31:1]
5202 .secure().exceptUserMode()
5203 .mapsTo(MISCREG_ICC_IGRPEN1_S);
5204 InitReg(MISCREG_ICC_SRE_EL2)
5205 .hyp().mon()
5206 .mapsTo(MISCREG_ICC_HSRE);
5207 InitReg(MISCREG_ICC_CTLR_EL3)
5208 .mon()
5209 .mapsTo(MISCREG_ICC_MCTLR);
5210 InitReg(MISCREG_ICC_SRE_EL3)
5211 .mon()
5212 .mapsTo(MISCREG_ICC_MSRE);
5213 InitReg(MISCREG_ICC_IGRPEN1_EL3)
5214 .mon()
5215 .mapsTo(MISCREG_ICC_MGRPEN1);
5216
5217 InitReg(MISCREG_ICH_AP0R0_EL2)
5218 .hyp().mon()
5219 .mapsTo(MISCREG_ICH_AP0R0);
5220 InitReg(MISCREG_ICH_AP0R1_EL2)
5221 .hyp().mon()
5222 .mapsTo(MISCREG_ICH_AP0R1);
5223 InitReg(MISCREG_ICH_AP0R2_EL2)
5224 .hyp().mon()
5225 .mapsTo(MISCREG_ICH_AP0R2);
5226 InitReg(MISCREG_ICH_AP0R3_EL2)
5227 .hyp().mon()
5228 .mapsTo(MISCREG_ICH_AP0R3);
5229 InitReg(MISCREG_ICH_AP1R0_EL2)
5230 .hyp().mon()
5231 .mapsTo(MISCREG_ICH_AP1R0);
5232 InitReg(MISCREG_ICH_AP1R1_EL2)
5233 .hyp().mon()
5234 .mapsTo(MISCREG_ICH_AP1R1);
5235 InitReg(MISCREG_ICH_AP1R2_EL2)
5236 .hyp().mon()
5237 .mapsTo(MISCREG_ICH_AP1R2);
5238 InitReg(MISCREG_ICH_AP1R3_EL2)
5239 .hyp().mon()
5240 .mapsTo(MISCREG_ICH_AP1R3);
5241 InitReg(MISCREG_ICH_HCR_EL2)
5242 .hyp().mon()
5243 .mapsTo(MISCREG_ICH_HCR);
5244 InitReg(MISCREG_ICH_VTR_EL2)
5245 .hyp().mon().writes(0)
5246 .mapsTo(MISCREG_ICH_VTR);
5247 InitReg(MISCREG_ICH_MISR_EL2)
5248 .hyp().mon().writes(0)
5249 .mapsTo(MISCREG_ICH_MISR);
5250 InitReg(MISCREG_ICH_EISR_EL2)
5251 .hyp().mon().writes(0)
5252 .mapsTo(MISCREG_ICH_EISR);
5253 InitReg(MISCREG_ICH_ELRSR_EL2)
5254 .hyp().mon().writes(0)
5255 .mapsTo(MISCREG_ICH_ELRSR);
5256 InitReg(MISCREG_ICH_VMCR_EL2)
5257 .hyp().mon()
5258 .mapsTo(MISCREG_ICH_VMCR);
5259 InitReg(MISCREG_ICH_LR0_EL2)
5260 .hyp().mon()
5261 .mapsTo(MISCREG_ICH_LR0, MISCREG_ICH_LRC0);
5262 InitReg(MISCREG_ICH_LR1_EL2)
5263 .hyp().mon()
5264 .mapsTo(MISCREG_ICH_LR1, MISCREG_ICH_LRC1);
5265 InitReg(MISCREG_ICH_LR2_EL2)
5266 .hyp().mon()
5267 .mapsTo(MISCREG_ICH_LR2, MISCREG_ICH_LRC2);
5268 InitReg(MISCREG_ICH_LR3_EL2)
5269 .hyp().mon()
5270 .mapsTo(MISCREG_ICH_LR3, MISCREG_ICH_LRC3);
5271 InitReg(MISCREG_ICH_LR4_EL2)
5272 .hyp().mon()
5273 .mapsTo(MISCREG_ICH_LR4, MISCREG_ICH_LRC4);
5274 InitReg(MISCREG_ICH_LR5_EL2)
5275 .hyp().mon()
5276 .mapsTo(MISCREG_ICH_LR5, MISCREG_ICH_LRC5);
5277 InitReg(MISCREG_ICH_LR6_EL2)
5278 .hyp().mon()
5279 .mapsTo(MISCREG_ICH_LR6, MISCREG_ICH_LRC6);
5280 InitReg(MISCREG_ICH_LR7_EL2)
5281 .hyp().mon()
5282 .mapsTo(MISCREG_ICH_LR7, MISCREG_ICH_LRC7);
5283 InitReg(MISCREG_ICH_LR8_EL2)
5284 .hyp().mon()
5285 .mapsTo(MISCREG_ICH_LR8, MISCREG_ICH_LRC8);
5286 InitReg(MISCREG_ICH_LR9_EL2)
5287 .hyp().mon()
5288 .mapsTo(MISCREG_ICH_LR9, MISCREG_ICH_LRC9);
5289 InitReg(MISCREG_ICH_LR10_EL2)
5290 .hyp().mon()
5291 .mapsTo(MISCREG_ICH_LR10, MISCREG_ICH_LRC10);
5292 InitReg(MISCREG_ICH_LR11_EL2)
5293 .hyp().mon()
5294 .mapsTo(MISCREG_ICH_LR11, MISCREG_ICH_LRC11);
5295 InitReg(MISCREG_ICH_LR12_EL2)
5296 .hyp().mon()
5297 .mapsTo(MISCREG_ICH_LR12, MISCREG_ICH_LRC12);
5298 InitReg(MISCREG_ICH_LR13_EL2)
5299 .hyp().mon()
5300 .mapsTo(MISCREG_ICH_LR13, MISCREG_ICH_LRC13);
5301 InitReg(MISCREG_ICH_LR14_EL2)
5302 .hyp().mon()
5303 .mapsTo(MISCREG_ICH_LR14, MISCREG_ICH_LRC14);
5304 InitReg(MISCREG_ICH_LR15_EL2)
5305 .hyp().mon()
5306 .mapsTo(MISCREG_ICH_LR15, MISCREG_ICH_LRC15);
5307
5308 // GICv3 AArch32
5309 InitReg(MISCREG_ICC_AP0R0)
5310 .allPrivileges().exceptUserMode();
5311 InitReg(MISCREG_ICC_AP0R1)
5312 .allPrivileges().exceptUserMode();
5313 InitReg(MISCREG_ICC_AP0R2)
5314 .allPrivileges().exceptUserMode();
5315 InitReg(MISCREG_ICC_AP0R3)
5316 .allPrivileges().exceptUserMode();
5317 InitReg(MISCREG_ICC_AP1R0)
5318 .allPrivileges().exceptUserMode();
5319 InitReg(MISCREG_ICC_AP1R0_NS)
5320 .allPrivileges().exceptUserMode();
5321 InitReg(MISCREG_ICC_AP1R0_S)
5322 .allPrivileges().exceptUserMode();
5323 InitReg(MISCREG_ICC_AP1R1)
5324 .allPrivileges().exceptUserMode();
5325 InitReg(MISCREG_ICC_AP1R1_NS)
5326 .allPrivileges().exceptUserMode();
5327 InitReg(MISCREG_ICC_AP1R1_S)
5328 .allPrivileges().exceptUserMode();
5329 InitReg(MISCREG_ICC_AP1R2)
5330 .allPrivileges().exceptUserMode();
5331 InitReg(MISCREG_ICC_AP1R2_NS)
5332 .allPrivileges().exceptUserMode();
5333 InitReg(MISCREG_ICC_AP1R2_S)
5334 .allPrivileges().exceptUserMode();
5335 InitReg(MISCREG_ICC_AP1R3)
5336 .allPrivileges().exceptUserMode();
5337 InitReg(MISCREG_ICC_AP1R3_NS)
5338 .allPrivileges().exceptUserMode();
5339 InitReg(MISCREG_ICC_AP1R3_S)
5340 .allPrivileges().exceptUserMode();
5341 InitReg(MISCREG_ICC_ASGI1R)
5342 .allPrivileges().exceptUserMode().reads(0);
5343 InitReg(MISCREG_ICC_BPR0)
5344 .allPrivileges().exceptUserMode();
5345 InitReg(MISCREG_ICC_BPR1)
5346 .allPrivileges().exceptUserMode();
5347 InitReg(MISCREG_ICC_BPR1_NS)
5348 .allPrivileges().exceptUserMode();
5349 InitReg(MISCREG_ICC_BPR1_S)
5350 .allPrivileges().exceptUserMode();
5351 InitReg(MISCREG_ICC_CTLR)
5352 .allPrivileges().exceptUserMode();
5353 InitReg(MISCREG_ICC_CTLR_NS)
5354 .allPrivileges().exceptUserMode();
5355 InitReg(MISCREG_ICC_CTLR_S)
5356 .allPrivileges().exceptUserMode();
5357 InitReg(MISCREG_ICC_DIR)
5358 .allPrivileges().exceptUserMode().reads(0);
5359 InitReg(MISCREG_ICC_EOIR0)
5360 .allPrivileges().exceptUserMode().reads(0);
5361 InitReg(MISCREG_ICC_EOIR1)
5362 .allPrivileges().exceptUserMode().reads(0);
5363 InitReg(MISCREG_ICC_HPPIR0)
5364 .allPrivileges().exceptUserMode().writes(0);
5365 InitReg(MISCREG_ICC_HPPIR1)
5366 .allPrivileges().exceptUserMode().writes(0);
5367 InitReg(MISCREG_ICC_HSRE)
5368 .hyp().mon();
5369 InitReg(MISCREG_ICC_IAR0)
5370 .allPrivileges().exceptUserMode().writes(0);
5371 InitReg(MISCREG_ICC_IAR1)
5372 .allPrivileges().exceptUserMode().writes(0);
5373 InitReg(MISCREG_ICC_IGRPEN0)
5374 .allPrivileges().exceptUserMode();
5375 InitReg(MISCREG_ICC_IGRPEN1)
5376 .allPrivileges().exceptUserMode();
5377 InitReg(MISCREG_ICC_IGRPEN1_NS)
5378 .allPrivileges().exceptUserMode();
5379 InitReg(MISCREG_ICC_IGRPEN1_S)
5380 .allPrivileges().exceptUserMode();
5381 InitReg(MISCREG_ICC_MCTLR)
5382 .mon();
5383 InitReg(MISCREG_ICC_MGRPEN1)
5384 .mon();
5385 InitReg(MISCREG_ICC_MSRE)
5386 .mon();
5387 InitReg(MISCREG_ICC_PMR)
5388 .allPrivileges().exceptUserMode();
5389 InitReg(MISCREG_ICC_RPR)
5390 .allPrivileges().exceptUserMode().writes(0);
5391 InitReg(MISCREG_ICC_SGI0R)
5392 .allPrivileges().exceptUserMode().reads(0);
5393 InitReg(MISCREG_ICC_SGI1R)
5394 .allPrivileges().exceptUserMode().reads(0);
5395 InitReg(MISCREG_ICC_SRE)
5396 .allPrivileges().exceptUserMode();
5397 InitReg(MISCREG_ICC_SRE_NS)
5398 .allPrivileges().exceptUserMode();
5399 InitReg(MISCREG_ICC_SRE_S)
5400 .allPrivileges().exceptUserMode();
5401
5402 InitReg(MISCREG_ICH_AP0R0)
5403 .hyp().mon();
5404 InitReg(MISCREG_ICH_AP0R1)
5405 .hyp().mon();
5406 InitReg(MISCREG_ICH_AP0R2)
5407 .hyp().mon();
5408 InitReg(MISCREG_ICH_AP0R3)
5409 .hyp().mon();
5410 InitReg(MISCREG_ICH_AP1R0)
5411 .hyp().mon();
5412 InitReg(MISCREG_ICH_AP1R1)
5413 .hyp().mon();
5414 InitReg(MISCREG_ICH_AP1R2)
5415 .hyp().mon();
5416 InitReg(MISCREG_ICH_AP1R3)
5417 .hyp().mon();
5418 InitReg(MISCREG_ICH_HCR)
5419 .hyp().mon();
5420 InitReg(MISCREG_ICH_VTR)
5421 .hyp().mon().writes(0);
5422 InitReg(MISCREG_ICH_MISR)
5423 .hyp().mon().writes(0);
5424 InitReg(MISCREG_ICH_EISR)
5425 .hyp().mon().writes(0);
5426 InitReg(MISCREG_ICH_ELRSR)
5427 .hyp().mon().writes(0);
5428 InitReg(MISCREG_ICH_VMCR)
5429 .hyp().mon();
5430 InitReg(MISCREG_ICH_LR0)
5431 .hyp().mon();
5432 InitReg(MISCREG_ICH_LR1)
5433 .hyp().mon();
5434 InitReg(MISCREG_ICH_LR2)
5435 .hyp().mon();
5436 InitReg(MISCREG_ICH_LR3)
5437 .hyp().mon();
5438 InitReg(MISCREG_ICH_LR4)
5439 .hyp().mon();
5440 InitReg(MISCREG_ICH_LR5)
5441 .hyp().mon();
5442 InitReg(MISCREG_ICH_LR6)
5443 .hyp().mon();
5444 InitReg(MISCREG_ICH_LR7)
5445 .hyp().mon();
5446 InitReg(MISCREG_ICH_LR8)
5447 .hyp().mon();
5448 InitReg(MISCREG_ICH_LR9)
5449 .hyp().mon();
5450 InitReg(MISCREG_ICH_LR10)
5451 .hyp().mon();
5452 InitReg(MISCREG_ICH_LR11)
5453 .hyp().mon();
5454 InitReg(MISCREG_ICH_LR12)
5455 .hyp().mon();
5456 InitReg(MISCREG_ICH_LR13)
5457 .hyp().mon();
5458 InitReg(MISCREG_ICH_LR14)
5459 .hyp().mon();
5460 InitReg(MISCREG_ICH_LR15)
5461 .hyp().mon();
5462 InitReg(MISCREG_ICH_LRC0)
5463 .hyp().mon();
5464 InitReg(MISCREG_ICH_LRC1)
5465 .hyp().mon();
5466 InitReg(MISCREG_ICH_LRC2)
5467 .hyp().mon();
5468 InitReg(MISCREG_ICH_LRC3)
5469 .hyp().mon();
5470 InitReg(MISCREG_ICH_LRC4)
5471 .hyp().mon();
5472 InitReg(MISCREG_ICH_LRC5)
5473 .hyp().mon();
5474 InitReg(MISCREG_ICH_LRC6)
5475 .hyp().mon();
5476 InitReg(MISCREG_ICH_LRC7)
5477 .hyp().mon();
5478 InitReg(MISCREG_ICH_LRC8)
5479 .hyp().mon();
5480 InitReg(MISCREG_ICH_LRC9)
5481 .hyp().mon();
5482 InitReg(MISCREG_ICH_LRC10)
5483 .hyp().mon();
5484 InitReg(MISCREG_ICH_LRC11)
5485 .hyp().mon();
5486 InitReg(MISCREG_ICH_LRC12)
5487 .hyp().mon();
5488 InitReg(MISCREG_ICH_LRC13)
5489 .hyp().mon();
5490 InitReg(MISCREG_ICH_LRC14)
5491 .hyp().mon();
5492 InitReg(MISCREG_ICH_LRC15)
5493 .hyp().mon();
5494
5495 // SVE
5496 InitReg(MISCREG_ID_AA64ZFR0_EL1)
5497 .reset([this](){
5498 AA64ZFR0 zfr0_el1 = 0;
5499 zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0;
5500 zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0;
5501 zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0;
5502 return zfr0_el1;
5503 }())
5504 .faultRead(EL0, faultIdst)
5505 .faultRead(EL1, HCR_TRAP(tid3))
5506 .allPrivileges().exceptUserMode().writes(0);
5507 InitReg(MISCREG_ZCR_EL3)
5508 .reset(sveVL - 1)
5509 .fault(EL3, faultZcrEL3)
5510 .mon();
5511 InitReg(MISCREG_ZCR_EL2)
5512 .reset(sveVL - 1)
5513 .fault(EL2, faultZcrEL2)
5514 .fault(EL3, faultZcrEL3)
5515 .hyp().mon();
5516 InitReg(MISCREG_ZCR_EL12)
5517 .fault(EL2, defaultFaultE2H_EL2)
5518 .fault(EL3, defaultFaultE2H_EL3)
5519 .mapsTo(MISCREG_ZCR_EL1);
5520 InitReg(MISCREG_ZCR_EL1)
5521 .reset(sveVL - 1)
5522 .fault(EL1, faultZcrEL1)
5523 .fault(EL2, faultZcrEL2)
5524 .fault(EL3, faultZcrEL3)
5525 .allPrivileges().exceptUserMode();
5526
5527 // SME
5528 InitReg(MISCREG_ID_AA64SMFR0_EL1)
5529 .reset([](){
5530 AA64SMFR0 smfr0_el1 = 0;
5531 smfr0_el1.f32f32 = 0x1;
5532 // The following BF16F32 is actually not implemented due to a
5533 // lack of BF16 support in gem5's fplib. However, as per the
5534 // SME spec the _only_ allowed value is 0x1.
5535 smfr0_el1.b16f32 = 0x1;
5536 smfr0_el1.f16f32 = 0x1;
5537 smfr0_el1.i8i32 = 0xF;
5538 smfr0_el1.f64f64 = 0x1;
5539 smfr0_el1.i16i64 = 0xF;
5540 smfr0_el1.smEver = 0;
5541 smfr0_el1.fa64 = 0x1;
5542 return smfr0_el1;
5543 }())
5544 .faultRead(EL0, faultIdst)
5545 .faultRead(EL1, HCR_TRAP(tid3))
5546 .allPrivileges().writes(0);
5547 InitReg(MISCREG_SVCR)
5548 .res0([](){
5549 SVCR svcr_mask = 0;
5550 svcr_mask.sm = 1;
5551 svcr_mask.za = 1;
5552 return ~svcr_mask;
5553 }())
5554 .fault(EL0, faultSmenEL0)
5555 .fault(EL1, faultSmenEL1)
5556 .fault(EL2, faultTsmSmen)
5557 .fault(EL3, faultEsm)
5558 .allPrivileges();
5559 InitReg(MISCREG_SMIDR_EL1)
5560 .reset([](){
5561 SMIDR smidr_el1 = 0;
5562 smidr_el1.affinity = 0;
5563 smidr_el1.smps = 0;
5564 smidr_el1.implementer = 0x41;
5565 return smidr_el1;
5566 }())
5567 .faultRead(EL0, faultIdst)
5568 .faultRead(EL1, HCR_TRAP(tid1))
5569 .allPrivileges().writes(0);
5570 InitReg(MISCREG_SMPRI_EL1)
5571 .res0(mask(63, 4))
5572 .fault(EL1, faultEsm)
5573 .fault(EL2, faultEsm)
5574 .fault(EL3, faultEsm)
5575 .allPrivileges().exceptUserMode();
5576 InitReg(MISCREG_SMPRIMAP_EL2)
5577 .fault(EL2, faultEsm)
5578 .fault(EL3, faultEsm)
5579 .hyp().mon();
5580 InitReg(MISCREG_SMCR_EL3)
5581 .reset([this](){
5582 // We want to support FEAT_SME_FA64. Therefore, we enable it in
5583 // all SMCR_ELx registers by default. Runtime software might
5584 // change this later, but given that gem5 doesn't disable
5585 // instructions based on this flag we default to the most
5586 // representative value.
5587 SMCR smcr_el3 = 0;
5588 smcr_el3.fa64 = 1;
5589 smcr_el3.len = smeVL - 1;
5590 return smcr_el3;
5591 }())
5592 .fault(EL3, faultEsm)
5593 .mon();
5594 InitReg(MISCREG_SMCR_EL2)
5595 .reset([this](){
5596 // We want to support FEAT_SME_FA64. Therefore, we enable it in
5597 // all SMCR_ELx registers by default. Runtime software might
5598 // change this later, but given that gem5 doesn't disable
5599 // instructions based on this flag we default to the most
5600 // representative value.
5601 SMCR smcr_el2 = 0;
5602 smcr_el2.fa64 = 1;
5603 smcr_el2.len = smeVL - 1;
5604 return smcr_el2;
5605 }())
5606 .fault(EL2, faultTsmSmen)
5607 .fault(EL3, faultEsm)
5608 .hyp().mon();
5609 InitReg(MISCREG_SMCR_EL12)
5610 .allPrivileges().exceptUserMode();
5611 InitReg(MISCREG_SMCR_EL1)
5612 .reset([this](){
5613 // We want to support FEAT_SME_FA64. Therefore, we enable it in
5614 // all SMCR_ELx registers by default. Runtime software might
5615 // change this later, but given that gem5 doesn't disable
5616 // instructions based on this flag we default to the most
5617 // representative value.
5618 SMCR smcr_el1 = 0;
5619 smcr_el1.fa64 = 1;
5620 smcr_el1.len = smeVL - 1;
5621 return smcr_el1;
5622 }())
5623 .fault(EL1, faultSmenEL1)
5624 .fault(EL2, faultTsmSmen)
5625 .fault(EL3, faultEsm)
5626 .allPrivileges().exceptUserMode();
5627 InitReg(MISCREG_TPIDR2_EL0)
5628 .allPrivileges();
5629 InitReg(MISCREG_MPAMSM_EL1)
5630 .allPrivileges().exceptUserMode();
5631
5632 InitReg(MISCREG_RNDR)
5633 .faultRead(EL0, faultRng)
5634 .faultRead(EL1, faultRng)
5635 .faultRead(EL2, faultRng)
5636 .faultRead(EL3, faultRng)
5637 .unverifiable()
5638 .allPrivileges().writes(0);
5639 InitReg(MISCREG_RNDRRS)
5640 .faultRead(EL0, faultRng)
5641 .faultRead(EL1, faultRng)
5642 .faultRead(EL2, faultRng)
5643 .faultRead(EL3, faultRng)
5644 .unverifiable()
5645 .allPrivileges().writes(0);
5646
5647 // Dummy registers
5648 InitReg(MISCREG_NOP)
5649 .allPrivileges();
5650 InitReg(MISCREG_RAZ)
5651 .allPrivileges().exceptUserMode().writes(0);
5652 InitReg(MISCREG_UNKNOWN);
5653 InitReg(MISCREG_IMPDEF_UNIMPL)
5654 .fault(EL1, faultImpdefUnimplEL1)
5655 .fault(EL2, faultUnimplemented)
5656 .fault(EL3, faultUnimplemented)
5657 .warnNotFail(impdefAsNop);
5658
5659 // RAS extension (unimplemented)
5660 InitReg(MISCREG_ERRIDR_EL1)
5661 .warnNotFail()
5662 .fault(faultUnimplemented);
5663 InitReg(MISCREG_ERRSELR_EL1)
5664 .warnNotFail()
5665 .fault(faultUnimplemented);
5666 InitReg(MISCREG_ERXFR_EL1)
5667 .warnNotFail()
5668 .fault(faultUnimplemented);
5669 InitReg(MISCREG_ERXCTLR_EL1)
5670 .warnNotFail()
5671 .fault(faultUnimplemented);
5672 InitReg(MISCREG_ERXSTATUS_EL1)
5673 .warnNotFail()
5674 .fault(faultUnimplemented);
5675 InitReg(MISCREG_ERXADDR_EL1)
5676 .warnNotFail()
5677 .fault(faultUnimplemented);
5678 InitReg(MISCREG_ERXMISC0_EL1)
5679 .warnNotFail()
5680 .fault(faultUnimplemented);
5681 InitReg(MISCREG_ERXMISC1_EL1)
5682 .warnNotFail()
5683 .fault(faultUnimplemented);
5684 InitReg(MISCREG_DISR_EL1)
5685 .warnNotFail()
5686 .fault(faultUnimplemented);
5687 InitReg(MISCREG_VSESR_EL2)
5688 .warnNotFail()
5689 .fault(faultUnimplemented);
5690 InitReg(MISCREG_VDISR_EL2)
5691 .warnNotFail()
5692 .fault(faultUnimplemented);
5693
5694 // FGT extension (unimplemented)
5695 InitReg(MISCREG_HFGRTR_EL2)
5696 .unimplemented()
5697 .warnNotFail();
5698 InitReg(MISCREG_HFGWTR_EL2)
5699 .unimplemented()
5700 .warnNotFail();
5701
5702 // Register mappings for some unimplemented registers:
5703 // ESR_EL1 -> DFSR
5704 // RMR_EL1 -> RMR
5705 // RMR_EL2 -> HRMR
5706 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5707 // DBGDTRRX_EL0 -> DBGDTRRXint
5708 // DBGDTRTX_EL0 -> DBGDTRRXint
5709 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5710
5711 // Populate the idxToMiscRegNum map
5712 assert(idxToMiscRegNum.empty());
5713 for (const auto& [key, val] : miscRegNumToIdx) {
5714 idxToMiscRegNum.insert({val, key});
5715 }
5716
5717 completed = true;
5718}
5719
5720} // namespace ArmISA
5721} // namespace gem5
HCR_TRAP
#define HCR_TRAP(bitfield)
Definition misc.cc:1756
gem5::ArmISA::ArmStaticInst::undefined
Fault undefined(bool disabled=false) const
Definition static_inst.hh:631
gem5::ArmISA::ISA::system
ArmSystem * system
Definition isa.hh:74
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition isa.hh:114
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition misc.cc:2289
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition isa.hh:103
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition isa.hh:92
gem5::ArmISA::MiscRegLUTEntryInitializer
Metadata table accessible via the value of the register.
Definition misc.hh:1240
gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition misc.hh:1305
gem5::ArmISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition misc.cc:2244
gem5::ArmISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition misc.hh:1551
gem5::ArmISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition misc.hh:1311
gem5::ArmISA::MiscRegLUTEntryInitializer::raz
chain raz(uint64_t mask=(uint64_t) -1) const
Definition misc.hh:1270
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition misc.hh:1399
gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition misc.hh:1538
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition misc.hh:1490
gem5::ArmISA::MiscRegLUTEntryInitializer::reset
chain reset(uint64_t res_val) const
Definition misc.hh:1252
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition misc.hh:1484
gem5::ArmISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition misc.hh:1317
gem5::ArmISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition misc.hh:1258
gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition misc.hh:1329
gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition misc.hh:1519
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition misc.hh:1472
gem5::ArmISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition misc.hh:1264
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition misc.hh:1512
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition misc.hh:1478
gem5::ArmISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition misc.hh:1496
gem5::ArmISA::MiscRegLUTEntryInitializer::unserialize
chain unserialize(bool v=true) const
Definition misc.hh:1299
gem5::ArmISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition misc.hh:1465
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition system.hh:76
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition system.hh:187
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition system.hh:191
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition system.cc:132
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition misc64.hh:157
gem5::MiscRegOp64::miscRead
bool miscRead() const
Definition misc64.hh:173
gem5::SimObject::Params
SimObjectParams Params
Definition sim_object.hh:170
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition thread_context.hh:89
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
std::vector
STL vector class.
Definition stl.hh:37
thread_context.hh
full_system.hh
gic_v3_cpu_interface.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
gem5::SimObject::params
const Params & params() const
Definition sim_object.hh:176
warn
#define warn(...)
Definition logging.hh:256
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition utility.cc:273
gem5::ArmISA::resetCPSR
static CPSR resetCPSR(ArmSystem *system)
Definition misc.cc:2256
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition types.hh:295
gem5::ArmISA::encodeAArch64SysReg
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg)
Definition misc.cc:2188
gem5::ArmISA::unflattenResultMiscReg
int unflattenResultMiscReg[NUM_MISCREGS]
If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
Definition misc.cc:704
gem5::ArmISA::asidbits
Bitfield< 7, 4 > asidbits
Definition misc_types.hh:156
gem5::ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:659
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition utility.cc:1302
gem5::ArmISA::ttlb
Bitfield< 25 > ttlb
Definition misc_types.hh:313
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition utility.cc:124
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition misc.cc:2162
gem5::ArmISA::i
Bitfield< 7 > i
Definition misc_types.hh:67
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition misc_types.hh:199
gem5::ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition misc.cc:534
gem5::ArmISA::tid1
Bitfield< 16 > tid1
Definition misc_types.hh:323
gem5::ArmISA::tid3
Bitfield< 18 > tid3
Definition misc_types.hh:321
gem5::ArmISA::tacr
Bitfield< 21 > tacr
Definition misc_types.hh:318
gem5::ArmISA::checkFaultAccessAArch64SysReg
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:729
gem5::ArmISA::tdz
Bitfield< 28 > tdz
Definition misc_types.hh:310
gem5::ArmISA::parange
Bitfield< 3, 0 > parange
Definition misc_types.hh:157
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition types.hh:106
gem5::ArmISA::tsw
Bitfield< 22 > tsw
Definition misc_types.hh:316
gem5::ArmISA::tid2
Bitfield< 17 > tid2
Definition misc_types.hh:322
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition misc_types.hh:179
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition utility.cc:86
gem5::ArmISA::tpc
Bitfield< 23 > tpc
Definition misc_types.hh:315
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition misc_types.hh:388
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition utility.cc:258
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition misc.cc:707
gem5::ArmISA::trvm
Bitfield< 30 > trvm
Definition misc_types.hh:308
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition misc.hh:743
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition misc.hh:1121
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition misc.hh:755
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition misc.hh:496
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition misc.hh:175
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition misc.hh:250
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition misc.hh:445
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition misc.hh:566
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition misc.hh:164
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition misc.hh:1041
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition misc.hh:236
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition misc.hh:595
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition misc.hh:508
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition misc.hh:368
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition misc.hh:142
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition misc.hh:193
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition misc.hh:107
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition misc.hh:553
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition misc.hh:606
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition misc.hh:323
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition misc.hh:1117
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition misc.hh:272
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition misc.hh:781
gem5::ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition misc.hh:1049
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition misc.hh:167
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition misc.hh:253
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition misc.hh:889
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition misc.hh:381
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition misc.hh:83
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition misc.hh:89
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition misc.hh:729
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition misc.hh:899
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition misc.hh:710
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition misc.hh:909
gem5::ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition misc.hh:614
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition misc.hh:157
gem5::ArmISA::MISCREG_TLBI_VMALLE1OS
@ MISCREG_TLBI_VMALLE1OS
Definition misc.hh:685
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition misc.hh:294
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition misc.hh:545
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition misc.hh:1014
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition misc.hh:275
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition misc.hh:441
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition misc.hh:505
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition misc.hh:444
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition misc.hh:835
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition misc.hh:324
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition misc.hh:1120
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition misc.hh:589
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition misc.hh:739
gem5::ArmISA::MISCREG_TLBI_ALLE2OS
@ MISCREG_TLBI_ALLE2OS
Definition misc.hh:707
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition misc.hh:549
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition misc.hh:788
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition misc.hh:702
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition misc.hh:304
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition misc.hh:778
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition misc.hh:289
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition misc.hh:184
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition misc.hh:330
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition misc.hh:371
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition misc.hh:80
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition misc.hh:160
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition misc.hh:94
gem5::ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition misc.hh:928
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition misc.hh:784
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition misc.hh:885
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition misc.hh:623
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition misc.hh:610
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition misc.hh:666
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition misc.hh:556
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition misc.hh:516
gem5::ArmISA::MISCREG_RNDRRS
@ MISCREG_RNDRRS
Definition misc.hh:1097
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition misc.hh:145
gem5::ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition misc.hh:927
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1OS_Xt
@ MISCREG_TLBI_IPAS2LE1OS_Xt
Definition misc.hh:705
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition misc.hh:1033
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition misc.hh:101
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition misc.hh:78
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition misc.hh:824
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition misc.hh:544
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition misc.hh:249
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition misc.hh:523
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition misc.hh:535
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition misc.hh:447
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition misc.hh:416
gem5::ArmISA::MISCREG_TLBI_VAE3OS_Xt
@ MISCREG_TLBI_VAE3OS_Xt
Definition misc.hh:726
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition misc.hh:191
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition misc.hh:331
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition misc.hh:1018
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition misc.hh:1078
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition misc.hh:904
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition misc.hh:73
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition misc.hh:1076
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition misc.hh:202
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition misc.hh:418
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition misc.hh:196
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition misc.hh:644
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition misc.hh:454
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition misc.hh:84
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition misc.hh:468
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition misc.hh:748
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition misc.hh:716
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition misc.hh:481
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition misc.hh:558
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition misc.hh:343
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition misc.hh:464
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition misc.hh:300
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition misc.hh:900
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition misc.hh:395
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition misc.hh:745
gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition misc.hh:1015
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition misc.hh:859
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition misc.hh:767
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition misc.hh:432
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition misc.hh:764
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition misc.hh:283
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition misc.hh:169
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition misc.hh:185
gem5::ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition misc.hh:1003
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition misc.hh:794
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition misc.hh:994
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition misc.hh:1017
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition misc.hh:256
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition misc.hh:631
gem5::ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition misc.hh:1050
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition misc.hh:868
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition misc.hh:863
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition misc.hh:105
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition misc.hh:291
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition misc.hh:720
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition misc.hh:403
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition misc.hh:150
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition misc.hh:221
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition misc.hh:677
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition misc.hh:819
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition misc.hh:88
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition misc.hh:936
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition misc.hh:76
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition misc.hh:188
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition misc.hh:1038
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition misc.hh:517
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition misc.hh:550
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition misc.hh:113
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition misc.hh:749
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition misc.hh:470
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition misc.hh:1058
gem5::ArmISA::MISCREG_SMIDR_EL1
@ MISCREG_SMIDR_EL1
Definition misc.hh:1085
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1OS
@ MISCREG_TLBI_VMALLS12E1OS
Definition misc.hh:715
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition misc.hh:240
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition misc.hh:661
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition misc.hh:265
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition misc.hh:498
gem5::ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition misc.hh:1047
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition misc.hh:679
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition misc.hh:350
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition misc.hh:316
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition misc.hh:752
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition misc.hh:431
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition misc.hh:850
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition misc.hh:532
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition misc.hh:235
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition misc.hh:246
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition misc.hh:719
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition misc.hh:394
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition misc.hh:351
gem5::ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition misc.hh:1001
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition misc.hh:119
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition misc.hh:281
gem5::ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition misc.hh:1069
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition misc.hh:599
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition misc.hh:261
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition misc.hh:346
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition misc.hh:688
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition misc.hh:825
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition misc.hh:791
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition misc.hh:847
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition misc.hh:345
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition misc.hh:328
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition misc.hh:568
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition misc.hh:231
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition misc.hh:198
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition misc.hh:771
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition misc.hh:114
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition misc.hh:500
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition misc.hh:192
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition misc.hh:821
gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition misc.hh:895
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition misc.hh:137
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition misc.hh:70
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition misc.hh:546
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition misc.hh:108
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition misc.hh:708
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition misc.hh:616
gem5::ArmISA::MISCREG_SMCR_EL1
@ MISCREG_SMCR_EL1
Definition misc.hh:1091
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition misc.hh:628
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition misc.hh:100
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition misc.hh:472
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition misc.hh:915
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition misc.hh:588
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition misc.hh:255
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition misc.hh:284
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition misc.hh:645
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition misc.hh:1125
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition misc.hh:279
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition misc.hh:878
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition misc.hh:742
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition misc.hh:427
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition misc.hh:527
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition misc.hh:336
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition misc.hh:636
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition misc.hh:156
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition misc.hh:681
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition misc.hh:180
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition misc.hh:607
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition misc.hh:369
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition misc.hh:266
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition misc.hh:365
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition misc.hh:492
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition misc.hh:773
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition misc.hh:122
gem5::ArmISA::MISCREG_HFGRTR_EL2
@ MISCREG_HFGRTR_EL2
Definition misc.hh:1130
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition misc.hh:984
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition misc.hh:239
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition misc.hh:699
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition misc.hh:409
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition misc.hh:576
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition misc.hh:181
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition misc.hh:420
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition misc.hh:646
gem5::ArmISA::MISCREG_TLBI_VAALE1OS_Xt
@ MISCREG_TLBI_VAALE1OS_Xt
Definition misc.hh:695
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition misc.hh:355
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition misc.hh:829
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition misc.hh:870
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition misc.hh:519
gem5::ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition misc.hh:1016
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition misc.hh:641
gem5::ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition misc.hh:987
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition misc.hh:74
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition misc.hh:212
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition misc.hh:524
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition misc.hh:194
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition misc.hh:179
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition misc.hh:522
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition misc.hh:506
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition misc.hh:706
gem5::ArmISA::MISCREG_TLBI_ALLE1OS
@ MISCREG_TLBI_ALLE1OS
Definition misc.hh:711
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition misc.hh:69
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition misc.hh:230
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition misc.hh:305
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition misc.hh:473
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition misc.hh:559
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition misc.hh:822
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition misc.hh:311
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition misc.hh:919
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition misc.hh:673
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition misc.hh:582
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition misc.hh:161
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition misc.hh:533
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition misc.hh:776
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition misc.hh:515
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition misc.hh:1122
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition misc.hh:387
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition misc.hh:493
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition misc.hh:1035
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition misc.hh:72
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition misc.hh:495
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition misc.hh:649
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition misc.hh:787
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition misc.hh:320
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition misc.hh:479
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition misc.hh:158
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition misc.hh:339
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition misc.hh:816
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition misc.hh:405
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition misc.hh:914
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition misc.hh:485
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition misc.hh:229
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition misc.hh:482
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition misc.hh:873
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition misc.hh:584
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition misc.hh:786
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition misc.hh:1031
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition misc.hh:499
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition misc.hh:414
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition misc.hh:578
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition misc.hh:675
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition misc.hh:201
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition misc.hh:374
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition misc.hh:1013
gem5::ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition misc.hh:1065
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition misc.hh:203
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition misc.hh:674
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition misc.hh:183
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition misc.hh:391
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition misc.hh:502
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition misc.hh:120
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition misc.hh:818
gem5::ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition misc.hh:1066
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition misc.hh:594
gem5::ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition misc.hh:930
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition misc.hh:487
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition misc.hh:232
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition misc.hh:655
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition misc.hh:1123
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition misc.hh:769
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition misc.hh:746
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition misc.hh:690
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition misc.hh:854
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition misc.hh:159
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition misc.hh:676
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition misc.hh:356
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition misc.hh:803
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition misc.hh:1005
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition misc.hh:428
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition misc.hh:430
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition misc.hh:653
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition misc.hh:280
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition misc.hh:856
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition misc.hh:288
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition misc.hh:569
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition misc.hh:669
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition misc.hh:207
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition misc.hh:766
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition misc.hh:573
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition misc.hh:342
gem5::ArmISA::MISCREG_SMCR_EL3
@ MISCREG_SMCR_EL3
Definition misc.hh:1088
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition misc.hh:621
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition misc.hh:830
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition misc.hh:111
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition misc.hh:1010
gem5::ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition misc.hh:1043
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition misc.hh:812
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition misc.hh:540
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition misc.hh:652
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition misc.hh:579
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition misc.hh:759
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition misc.hh:754
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition misc.hh:332
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition misc.hh:455
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition misc.hh:575
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition misc.hh:536
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition misc.hh:92
gem5::ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition misc.hh:925
gem5::ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition misc.hh:1109
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition misc.hh:359
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition misc.hh:1040
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition misc.hh:354
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition misc.hh:604
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition misc.hh:437
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition misc.hh:315
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition misc.hh:75
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition misc.hh:521
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition misc.hh:777
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition misc.hh:125
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition misc.hh:696
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition misc.hh:471
gem5::ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition misc.hh:932
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition misc.hh:838
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition misc.hh:871
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition misc.hh:831
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition misc.hh:763
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition misc.hh:200
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition misc.hh:622
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition misc.hh:358
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition misc.hh:1118
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition misc.hh:722
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition misc.hh:290
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition misc.hh:463
gem5::ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition misc.hh:992
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition misc.hh:483
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition misc.hh:66
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition misc.hh:627
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition misc.hh:247
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition misc.hh:163
gem5::ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition misc.hh:935
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition misc.hh:400
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition misc.hh:587
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition misc.hh:258
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition misc.hh:881
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition misc.hh:189
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition misc.hh:277
gem5::ArmISA::MISCREG_SMPRI_EL1
@ MISCREG_SMPRI_EL1
Definition misc.hh:1086
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition misc.hh:220
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition misc.hh:823
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition misc.hh:424
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition misc.hh:225
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition misc.hh:465
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition misc.hh:879
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition misc.hh:448
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition misc.hh:790
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition misc.hh:392
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition misc.hh:154
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition misc.hh:867
gem5::ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition misc.hh:1000
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition misc.hh:419
gem5::ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition misc.hh:931
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition misc.hh:640
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition misc.hh:982
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition misc.hh:744
gem5::ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition misc.hh:1052
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition misc.hh:792
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition misc.hh:721
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition misc.hh:714
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition misc.hh:380
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition misc.hh:894
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition misc.hh:475
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition misc.hh:738
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition misc.hh:585
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition misc.hh:121
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition misc.hh:605
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition misc.hh:820
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition misc.hh:383
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition misc.hh:725
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition misc.hh:626
gem5::ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition misc.hh:635
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition misc.hh:96
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition misc.hh:619
gem5::ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition misc.hh:785
gem5::ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition misc.hh:244
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition misc.hh:732
gem5::ArmISA::MISCREG_ICC_AP1R1_S
@ MISCREG_ICC_AP1R1_S
Definition misc.hh:990
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition misc.hh:733
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition misc.hh:800
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition misc.hh:215
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition misc.hh:136
gem5::ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition misc.hh:828
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition misc.hh:686
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition misc.hh:366
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition misc.hh:598
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition misc.hh:548
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition misc.hh:490
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition misc.hh:480
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition misc.hh:344
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition misc.hh:474
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition misc.hh:141
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition misc.hh:138
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition misc.hh:849
gem5::ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition misc.hh:541
gem5::ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition misc.hh:124
gem5::ArmISA::MISCREG_TLBI_VAAE1OS_Xt
@ MISCREG_TLBI_VAAE1OS_Xt
Definition misc.hh:691
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition misc.hh:223
gem5::ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition misc.hh:237
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition misc.hh:139
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition misc.hh:1073
gem5::ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition misc.hh:901
gem5::ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition misc.hh:1036
gem5::ArmISA::MISCREG_MPAMSM_EL1
@ MISCREG_MPAMSM_EL1
Definition misc.hh:1093
gem5::ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition misc.hh:1011
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition misc.hh:883
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition misc.hh:531
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition misc.hh:504
gem5::ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition misc.hh:373
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition misc.hh:547
gem5::ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition misc.hh:1002
gem5::ArmISA::MISCREG_ICH_LR2_EL2
@ MISCREG_ICH_LR2_EL2
Definition misc.hh:923
gem5::ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition misc.hh:832
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition misc.hh:329
gem5::ArmISA::MISCREG_SMPRIMAP_EL2
@ MISCREG_SMPRIMAP_EL2
Definition misc.hh:1087
gem5::ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition misc.hh:1006
gem5::ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition misc.hh:425
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition misc.hh:462
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition misc.hh:760
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition misc.hh:401
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition misc.hh:518
gem5::ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition misc.hh:286
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition misc.hh:561
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition misc.hh:404
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition misc.hh:363
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition misc.hh:723
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition misc.hh:478
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition misc.hh:560
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition misc.hh:801
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition misc.hh:248
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition misc.hh:663
gem5::ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition misc.hh:985
gem5::ArmISA::MISCREG_TPIDR2_EL0
@ MISCREG_TPIDR2_EL0
Definition misc.hh:1092
gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition misc.hh:862
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition misc.hh:704
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition misc.hh:357
gem5::ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition misc.hh:118
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition misc.hh:882
gem5::ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition misc.hh:152
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition misc.hh:632
gem5::ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition misc.hh:379
gem5::ArmISA::MISCREG_ICH_LR5_EL2
@ MISCREG_ICH_LR5_EL2
Definition misc.hh:926
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition misc.hh:839
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition misc.hh:429
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition misc.hh:608
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition misc.hh:795
gem5::ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition misc.hh:182
gem5::ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition misc.hh:176
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition misc.hh:205
gem5::ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition misc.hh:1124
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition misc.hh:460
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition misc.hh:390
gem5::ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition misc.hh:446
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition misc.hh:513
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition misc.hh:555
gem5::ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition misc.hh:301
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition misc.hh:491
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition misc.hh:218
gem5::ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition misc.hh:423
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS
@ MISCREG_ICC_AP1R1_EL1_NS
Definition misc.hh:872
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition misc.hh:842
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition misc.hh:1023
gem5::ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition misc.hh:103
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition misc.hh:574
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition misc.hh:296
gem5::ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition misc.hh:1020
gem5::ArmISA::MISCREG_ICH_LRC5
@ MISCREG_ICH_LRC5
Definition misc.hh:1063
gem5::ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition misc.hh:415
gem5::ArmISA::MISCREG_ICH_LR6
@ MISCREG_ICH_LR6
Definition misc.hh:1048
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition misc.hh:347
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition misc.hh:662
gem5::ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition misc.hh:991
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition misc.hh:168
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition misc.hh:853
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition misc.hh:638
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition misc.hh:848
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition misc.hh:665
gem5::ArmISA::MISCREG_TLBI_VALE3OS_Xt
@ MISCREG_TLBI_VALE3OS_Xt
Definition misc.hh:728
gem5::ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition misc.hh:913
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition misc.hh:335
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition misc.hh:326
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition misc.hh:750
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition misc.hh:892
gem5::ArmISA::MISCREG_ICC_CTLR_S
@ MISCREG_ICC_CTLR_S
Definition misc.hh:1004
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition misc.hh:654
gem5::ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition misc.hh:440
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition misc.hh:325
gem5::ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition misc.hh:1037
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition misc.hh:398
gem5::ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition misc.hh:908
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition misc.hh:682
gem5::ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition misc.hh:1024
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition misc.hh:671
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition misc.hh:808
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition misc.hh:309
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition misc.hh:340
gem5::ArmISA::MISCREG_ICH_LRC12
@ MISCREG_ICH_LRC12
Definition misc.hh:1070
gem5::ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition misc.hh:186
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition misc.hh:852
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition misc.hh:333
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition misc.hh:625
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition misc.hh:452
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition misc.hh:647
gem5::ArmISA::MISCREG_ICH_LRC9
@ MISCREG_ICH_LRC9
Definition misc.hh:1067
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition misc.hh:618
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition misc.hh:855
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition misc.hh:656
gem5::ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition misc.hh:378
gem5::ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition misc.hh:319
gem5::ArmISA::MISCREG_TLBI_VALE2OS_Xt
@ MISCREG_TLBI_VALE2OS_Xt
Definition misc.hh:713
gem5::ArmISA::MISCREG_ICH_LR13_EL2
@ MISCREG_ICH_LR13_EL2
Definition misc.hh:934
gem5::ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition misc.hh:902
gem5::ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition misc.hh:102
gem5::ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition misc.hh:891
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition misc.hh:348
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition misc.hh:779
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition misc.hh:591
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition misc.hh:807
gem5::ArmISA::MISCREG_SMCR_EL2
@ MISCREG_SMCR_EL2
Definition misc.hh:1089
gem5::ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition misc.hh:833
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition misc.hh:307
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition misc.hh:310
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition misc.hh:262
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition misc.hh:680
gem5::ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition misc.hh:1032
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition misc.hh:214
gem5::ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition misc.hh:983
gem5::ArmISA::MISCREG_TLBI_ASIDE1OS_Xt
@ MISCREG_TLBI_ASIDE1OS_Xt
Definition misc.hh:689
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition misc.hh:197
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition misc.hh:349
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition misc.hh:375
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition misc.hh:1080
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition misc.hh:740
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition misc.hh:844
gem5::ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition misc.hh:880
gem5::ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition misc.hh:600
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition misc.hh:770
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition misc.hh:109
gem5::ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition misc.hh:110
gem5::ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition misc.hh:903
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition misc.hh:612
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition misc.hh:162
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition misc.hh:639
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition misc.hh:334
gem5::ArmISA::MISCREG_ICH_LR12
@ MISCREG_ICH_LR12
Definition misc.hh:1054
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition misc.hh:170
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition misc.hh:537
gem5::ArmISA::MISCREG_ICH_LR3_EL2
@ MISCREG_ICH_LR3_EL2
Definition misc.hh:924
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition misc.hh:453
gem5::ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition misc.hh:530
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition misc.hh:810
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition misc.hh:282
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition misc.hh:165
gem5::ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition misc.hh:912
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition misc.hh:701
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition misc.hh:238
gem5::ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition misc.hh:1034
gem5::ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition misc.hh:298
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition misc.hh:869
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition misc.hh:174
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition misc.hh:434
gem5::ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition misc.hh:861
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition misc.hh:263
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition misc.hh:659
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition misc.hh:586
gem5::ArmISA::MISCREG_ICH_LR8_EL2
@ MISCREG_ICH_LR8_EL2
Definition misc.hh:929
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition misc.hh:799
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition misc.hh:466
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition misc.hh:106
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition misc.hh:458
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition misc.hh:469
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition misc.hh:520
gem5::ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition misc.hh:1012
gem5::ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition misc.hh:827
gem5::ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition misc.hh:1057
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition misc.hh:670
gem5::ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition misc.hh:1028
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition misc.hh:762
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S
@ MISCREG_ICC_AP1R2_EL1_S
Definition misc.hh:876
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition misc.hh:486
gem5::ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition misc.hh:886
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition misc.hh:303
gem5::ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition misc.hh:910
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition misc.hh:173
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition misc.hh:484
gem5::ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition misc.hh:450
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition misc.hh:590
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition misc.hh:836
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition misc.hh:292
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition misc.hh:510
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition misc.hh:211
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition misc.hh:658
gem5::ArmISA::MISCREG_TPIDRURW
@ MISCREG_TPIDRURW
Definition misc.hh:407
gem5::ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition misc.hh:187
gem5::ArmISA::MISCREG_ICH_LRC6
@ MISCREG_ICH_LRC6
Definition misc.hh:1064
gem5::ArmISA::MISCREG_ICH_LR1_EL2
@ MISCREG_ICH_LR1_EL2
Definition misc.hh:922
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition misc.hh:233
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition misc.hh:242
gem5::ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition misc.hh:104
gem5::ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition misc.hh:1029
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition misc.hh:593
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition misc.hh:396
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition misc.hh:276
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition misc.hh:361
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition misc.hh:297
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition misc.hh:252
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition misc.hh:551
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition misc.hh:389
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition misc.hh:805
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition misc.hh:758
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition misc.hh:210
gem5::ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition misc.hh:1039
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition misc.hh:814
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition misc.hh:793
gem5::ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition misc.hh:268
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition misc.hh:753
gem5::ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition misc.hh:998
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition misc.hh:327
gem5::ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition misc.hh:264
gem5::ArmISA::MISCREG_ICH_LR2
@ MISCREG_ICH_LR2
Definition misc.hh:1044
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition misc.hh:402
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition misc.hh:204
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition misc.hh:664
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition misc.hh:372
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition misc.hh:195
gem5::ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition misc.hh:153
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition misc.hh:421
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition misc.hh:615
gem5::ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition misc.hh:864
gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition misc.hh:897
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition misc.hh:511
gem5::ArmISA::MISCREG_ICC_AP1R2_S
@ MISCREG_ICC_AP1R2_S
Definition misc.hh:993
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition misc.hh:581
gem5::ArmISA::MISCREG_ICH_LRC13
@ MISCREG_ICH_LRC13
Definition misc.hh:1071
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition misc.hh:352
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS
@ MISCREG_ICC_AP1R2_EL1_NS
Definition misc.hh:875
gem5::ArmISA::MISCREG_TLBI_VAE2OS_Xt
@ MISCREG_TLBI_VAE2OS_Xt
Definition misc.hh:709
gem5::ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition misc.hh:920
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition misc.hh:314
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition misc.hh:730
gem5::ArmISA::MISCREG_ICH_LRC14
@ MISCREG_ICH_LRC14
Definition misc.hh:1072
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition misc.hh:271
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition misc.hh:353
gem5::ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition misc.hh:1007
gem5::ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition misc.hh:155
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition misc.hh:727
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition misc.hh:761
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition misc.hh:884
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition misc.hh:596
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition misc.hh:131
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition misc.hh:461
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition misc.hh:438
gem5::ArmISA::MISCREG_ICH_LR12_EL2
@ MISCREG_ICH_LR12_EL2
Definition misc.hh:933
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition misc.hh:538
gem5::ArmISA::MISCREG_ICH_LRC3
@ MISCREG_ICH_LRC3
Definition misc.hh:1061
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition misc.hh:668
gem5::ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition misc.hh:388
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition misc.hh:318
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition misc.hh:678
gem5::ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition misc.hh:178
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition misc.hh:213
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition misc.hh:143
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition misc.hh:571
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition misc.hh:171
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition misc.hh:642
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition misc.hh:321
gem5::ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition misc.hh:826
gem5::ArmISA::MISCREG_ICH_LR3
@ MISCREG_ICH_LR3
Definition misc.hh:1045
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition misc.hh:477
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition misc.hh:337
gem5::ArmISA::MISCREG_TLBINEEDSYNC
@ MISCREG_TLBINEEDSYNC
Definition misc.hh:97
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition misc.hh:562
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition misc.hh:620
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition misc.hh:751
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition misc.hh:367
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition misc.hh:112
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition misc.hh:435
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition misc.hh:526
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition misc.hh:362
gem5::ArmISA::MISCREG_ICH_LR9
@ MISCREG_ICH_LR9
Definition misc.hh:1051
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition misc.hh:772
gem5::ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition misc.hh:190
gem5::ArmISA::MISCREG_ICC_SRE_NS
@ MISCREG_ICC_SRE_NS
Definition misc.hh:1025
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition misc.hh:274
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition misc.hh:217
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition misc.hh:797
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition misc.hh:783
gem5::ArmISA::MISCREG_HFGWTR_EL2
@ MISCREG_HFGWTR_EL2
Definition misc.hh:1131
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition misc.hh:1077
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition misc.hh:129
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition misc.hh:525
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition misc.hh:71
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition misc.hh:322
gem5::ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition misc.hh:756
gem5::ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition misc.hh:269
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition misc.hh:77
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition misc.hh:259
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition misc.hh:509
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition misc.hh:144
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition misc.hh:270
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition misc.hh:609
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition misc.hh:251
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition misc.hh:241
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition misc.hh:497
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition misc.hh:898
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition misc.hh:981
gem5::ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition misc.hh:245
gem5::ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition misc.hh:306
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition misc.hh:370
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition misc.hh:736
gem5::ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition misc.hh:442
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition misc.hh:603
gem5::ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition misc.hh:1008
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition misc.hh:206
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition misc.hh:302
gem5::ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition misc.hh:443
gem5::ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition misc.hh:422
gem5::ArmISA::MISCREG_HCRX_EL2
@ MISCREG_HCRX_EL2
Definition misc.hh:592
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition misc.hh:817
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition misc.hh:338
gem5::ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition misc.hh:866
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition misc.hh:597
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition misc.hh:780
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition misc.hh:86
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition misc.hh:624
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition misc.hh:476
gem5::ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition misc.hh:149
gem5::ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition misc.hh:1126
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition misc.hh:199
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition misc.hh:1022
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition misc.hh:563
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition misc.hh:907
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition misc.hh:694
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition misc.hh:226
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition misc.hh:127
gem5::ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition misc.hh:917
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition misc.hh:267
gem5::ArmISA::MISCREG_TLBI_VAE1OS_Xt
@ MISCREG_TLBI_VAE1OS_Xt
Definition misc.hh:687
gem5::ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition misc.hh:278
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition misc.hh:360
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition misc.hh:564
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition misc.hh:570
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition misc.hh:313
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition misc.hh:565
gem5::ArmISA::MISCREG_SMCR_EL12
@ MISCREG_SMCR_EL12
Definition misc.hh:1090
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition misc.hh:130
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition misc.hh:534
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition misc.hh:488
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition misc.hh:735
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition misc.hh:557
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition misc.hh:234
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition misc.hh:273
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition misc.hh:507
gem5::ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition misc.hh:988
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition misc.hh:834
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition misc.hh:494
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition misc.hh:630
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition misc.hh:712
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition misc.hh:116
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition misc.hh:79
gem5::ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition misc.hh:1042
gem5::ArmISA::MISCREG_ICH_LRC2
@ MISCREG_ICH_LRC2
Definition misc.hh:1060
gem5::ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition misc.hh:148
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition misc.hh:552
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition misc.hh:91
gem5::ArmISA::MISCREG_ICC_AP1R3_S
@ MISCREG_ICC_AP1R3_S
Definition misc.hh:996
gem5::ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition misc.hh:385
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition misc.hh:684
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition misc.hh:617
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition misc.hh:572
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition misc.hh:295
gem5::ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition misc.hh:151
gem5::ArmISA::MISCREG_ICC_SRE_EL1_S
@ MISCREG_ICC_SRE_EL1_S
Definition misc.hh:896
gem5::ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition misc.hh:918
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition misc.hh:798
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition misc.hh:683
gem5::ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition misc.hh:888
gem5::ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition misc.hh:865
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition misc.hh:718
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition misc.hh:512
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition misc.hh:308
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition misc.hh:222
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition misc.hh:393
gem5::ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition misc.hh:921
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition misc.hh:851
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition misc.hh:583
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition misc.hh:672
gem5::ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition misc.hh:860
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition misc.hh:890
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition misc.hh:135
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition misc.hh:386
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition misc.hh:397
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition misc.hh:514
gem5::ArmISA::MISCREG_TLBI_VALE1OS_Xt
@ MISCREG_TLBI_VALE1OS_Xt
Definition misc.hh:693
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition misc.hh:737
gem5::ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition misc.hh:1019
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition misc.hh:132
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition misc.hh:364
gem5::ArmISA::MISCREG_ICC_AP1R0_NS
@ MISCREG_ICC_AP1R0_NS
Definition misc.hh:986
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition misc.hh:287
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition misc.hh:874
gem5::ArmISA::MISCREG_TPIDRURO
@ MISCREG_TPIDRURO
Definition misc.hh:410
gem5::ArmISA::MISCREG_ICH_LRC1
@ MISCREG_ICH_LRC1
Definition misc.hh:1059
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition misc.hh:254
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition misc.hh:692
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition misc.hh:629
gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition misc.hh:887
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition misc.hh:837
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition misc.hh:877
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition misc.hh:436
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition misc.hh:260
gem5::ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition misc.hh:1021
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition misc.hh:657
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition misc.hh:806
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition misc.hh:134
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition misc.hh:146
gem5::ArmISA::MISCREG_ID_AA64SMFR0_EL1
@ MISCREG_ID_AA64SMFR0_EL1
Definition misc.hh:1083
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition misc.hh:997
gem5::ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition misc.hh:911
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition misc.hh:815
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition misc.hh:85
gem5::ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition misc.hh:789
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition misc.hh:765
gem5::ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition misc.hh:916
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition misc.hh:731
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition misc.hh:698
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition misc.hh:489
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition misc.hh:459
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition misc.hh:667
gem5::ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition misc.hh:529
gem5::ArmISA::MISCREG_ICC_SRE_S
@ MISCREG_ICC_SRE_S
Definition misc.hh:1026
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition misc.hh:501
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition misc.hh:717
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition misc.hh:228
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition misc.hh:796
gem5::ArmISA::MISCREG_ICH_LR14
@ MISCREG_ICH_LR14
Definition misc.hh:1056
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition misc.hh:1114
gem5::ArmISA::MISCREG_ICH_LRC10
@ MISCREG_ICH_LRC10
Definition misc.hh:1068
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition misc.hh:399
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition misc.hh:133
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition misc.hh:503
gem5::ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition misc.hh:1119
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition misc.hh:734
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition misc.hh:299
gem5::ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition misc.hh:451
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition misc.hh:768
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition misc.hh:601
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition misc.hh:650
gem5::ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition misc.hh:285
gem5::ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition misc.hh:637
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition misc.hh:660
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition misc.hh:93
gem5::ArmISA::MISCREG_ICH_LR4
@ MISCREG_ICH_LR4
Definition misc.hh:1046
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition misc.hh:216
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition misc.hh:577
gem5::ArmISA::MISCREG_ICH_LRC4
@ MISCREG_ICH_LRC4
Definition misc.hh:1062
gem5::ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition misc.hh:117
gem5::ArmISA::MISCREG_TLBI_IPAS2E1OS_Xt
@ MISCREG_TLBI_IPAS2E1OS_Xt
Definition misc.hh:703
gem5::ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition misc.hh:382
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition misc.hh:317
gem5::ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition misc.hh:757
gem5::ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition misc.hh:999
gem5::ArmISA::MISCREG_ICH_LR11
@ MISCREG_ICH_LR11
Definition misc.hh:1053
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition misc.hh:293
gem5::ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition misc.hh:1030
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition misc.hh:554
gem5::ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition misc.hh:634
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition misc.hh:700
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition misc.hh:224
gem5::ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition misc.hh:177
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition misc.hh:643
gem5::ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition misc.hh:426
gem5::ArmISA::MISCREG_ICH_LR13
@ MISCREG_ICH_LR13
Definition misc.hh:1055
gem5::ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition misc.hh:412
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition misc.hh:467
gem5::ArmISA::MISCREG_VSTTBR_EL2
@ MISCREG_VSTTBR_EL2
Definition misc.hh:613
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition misc.hh:433
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition misc.hh:90
gem5::ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition misc.hh:147
gem5::ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition misc.hh:406
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition misc.hh:804
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition misc.hh:87
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition misc.hh:741
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition misc.hh:408
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition misc.hh:580
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition misc.hh:775
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition misc.hh:219
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition misc.hh:893
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition misc.hh:539
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition misc.hh:128
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition misc.hh:651
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition misc.hh:411
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition misc.hh:140
gem5::ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition misc.hh:528
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition misc.hh:341
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition misc.hh:697
gem5::ArmISA::MISCREG_ICC_AP1R1_NS
@ MISCREG_ICC_AP1R1_NS
Definition misc.hh:989
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition misc.hh:813
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition misc.hh:67
gem5::ArmISA::MISCREG_TPIDRPRW
@ MISCREG_TPIDRPRW
Definition misc.hh:413
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition misc.hh:243
gem5::ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition misc.hh:123
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition misc.hh:611
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition misc.hh:166
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition misc.hh:95
gem5::ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition misc.hh:384
gem5::ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition misc.hh:1009
gem5::ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition misc.hh:1127
gem5::ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition misc.hh:126
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition misc.hh:115
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition misc.hh:567
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition misc.hh:449
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition misc.hh:257
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition misc.hh:602
gem5::ArmISA::MISCREG_TLBI_ALLE3OS
@ MISCREG_TLBI_ALLE3OS
Definition misc.hh:724
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition misc.hh:648
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition misc.hh:227
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition misc.hh:68
gem5::ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition misc.hh:376
gem5::ArmISA::MISCREG_ICC_AP1R3_NS
@ MISCREG_ICC_AP1R3_NS
Definition misc.hh:995
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition misc.hh:782
gem5::ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition misc.hh:1079
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition misc.hh:172
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition misc.hh:633
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition misc.hh:312
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition misc.hh:377
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition misc.hh:747
gem5::ArmISA::tvm
Bitfield< 26 > tvm
Definition misc_types.hh:312
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition misc_types.hh:73
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition misc.hh:1166
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition misc.hh:1158
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition misc.hh:1182
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition misc.hh:1170
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition misc.hh:1172
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition misc.hh:1179
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition misc.hh:1152
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition misc.hh:1147
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition misc.hh:1183
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition misc.hh:1175
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition misc.hh:1171
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition misc.hh:1169
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition misc.hh:1165
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition misc.hh:1167
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition misc.hh:1164
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition misc.hh:1180
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition misc.hh:1174
gem5::ArmISA::decodeCP14Reg
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition misc.cc:520
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition utility.cc:888
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition misc.cc:723
gem5::ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:671
gem5::ArmISA::aarch64
Bitfield< 34 > aarch64
Definition types.hh:81
gem5::ArmISA::canWriteCoprocReg
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to write coprocessor registers.
Definition misc.cc:612
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition utility.cc:222
gem5::ArmISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:689
gem5::ArmISA::decodeCP15Reg64
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition misc.cc:553
gem5::ArmISA::lookUpMiscReg
std::vector< struct MiscRegLUTEntry > lookUpMiscReg(NUM_MISCREGS)
Definition misc.hh:1627
gem5::ArmISA::defaultFaultE2H_EL2
static Fault defaultFaultE2H_EL2(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:2219
gem5::ArmISA::canReadCoprocReg
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to read coprocessor registers.
Definition misc.cc:565
gem5::ArmISA::defaultFaultE2H_EL3
static Fault defaultFaultE2H_EL3(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:2231
gem5::MipsISA::p
Bitfield< 0 > p
Definition pra_constants.hh:326
gem5::SparcISA::priv
Bitfield< 2 > priv
Definition misc.hh:131
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition types.hh:92
gem5::X86ISA::system
Bitfield< 15 > system
Definition misc.hh:1004
gem5::X86ISA::val
Bitfield< 63 > val
Definition misc.hh:776
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition gpu_translation_state.hh:38
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition thread_context.cc:222
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition root.cc:220
gem5::RegVal
uint64_t RegVal
Definition types.hh:173
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition types.hh:253
gem5::ArmISA::MiscRegLUTEntry
MiscReg metadata.
Definition misc.hh:1190
gem5::ArmISA::MiscRegLUTEntry::defaultFault
static Fault defaultFault(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:2208
gem5::ArmISA::MiscRegLUTEntry::faultRead
std::array< FaultCB, EL3+1 > faultRead
Definition misc.hh:1205
gem5::ArmISA::MiscRegLUTEntry::info
std::bitset< NUM_MISCREG_INFOS > info
Definition misc.hh:1198
gem5::ArmISA::MiscRegLUTEntry::faultWrite
std::array< FaultCB, EL3+1 > faultWrite
Definition misc.hh:1206
gem5::ArmISA::MiscRegLUTEntry::checkFault
Fault checkFault(ThreadContext *tc, const MiscRegOp64 &inst, ExceptionLevel el)
Definition misc.cc:2199
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